From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by mx.groups.io with SMTP id smtpd.web11.1932.1589580821758625040 for ; Fri, 15 May 2020 15:13:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=m3uSeOd+; spf=pass (domain: nuviainc.com, ip: 209.85.221.67, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f67.google.com with SMTP id i15so5124674wrx.10 for ; Fri, 15 May 2020 15:13:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=G9o/C113pHXA/dhqoanuueW/wjWhe8EhGN75A4Vw6iY=; b=m3uSeOd+EaFuJTMs5JHPAJTFX78CoVF8tk3n9BjgpgjlsZY/e4TygUne70de3DVyA+ UzLN3yurxU0rPG+ed8QIyMCJtijqZQkHMwpwDIkizEq3doLedFew0wkILmqQgPqKs9Xm tfjVEOTfd0Xk8gFrO4pNaGfN7hDnuHP+Ru4Bk1SOrQd0ZltB0NqohvPz0zceAkY4hy+P 5WunRYdPhaoFLcd4lpBdZD5x4SSDERiLNSjjEDSjhpKexmmVpJyJwRmlSIfsmiX43u/n iOUKM5I0WQwKpsrZfsuDiGnojl/2YryyuD7nOToR3qG9pOoj8bU//53WQShPITPO28sn Brgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=G9o/C113pHXA/dhqoanuueW/wjWhe8EhGN75A4Vw6iY=; b=ntAGw5e6BDxkIcDfbciaVzwdROmLNiEXGveibLQocVMc3aJmqJdEeNqbnAqhbxzbId S9RXpNo53RtCWLBFL1i5naw1LKu+vj9nfN6PbUXEwsP0K0wnXydawn4wJrP48Uvu4iI6 jK9jvOmU+D8lKUY56re1ZeMguYJokfZZYvYep1VDPxEiFZ2RTZUf8aPW/SA00HPH4isq EBx1YAiAxHXsvRA7ONSyMyM2cxwnBdKK3ujQAhK13moM7tj+oQcWb4wn7xkaAaDvryU5 omIhKJEQ/DqacU4i8nYGwO5jy2dKlRpfYvjwzJAaXkzCvQrfSHdxustgqEOz7rmAtHBs G0lw== X-Gm-Message-State: AOAM533SrQctV6Wqm7ROcm2o2OQJSX8z/2ITEUOG6QS2NresnlLXlM2H 4DvsxxtaZlPubOzUBGTVbTS3oQ== X-Google-Smtp-Source: ABdhPJzdebqGniY/B9F59vEfF6rpFZP4hAE4T+9A/gGgqJ9mQdK2YJClqEw6lYbZBk31+C5QmeP43g== X-Received: by 2002:adf:8023:: with SMTP id 32mr6789260wrk.247.1589580820175; Fri, 15 May 2020 15:13:40 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id k131sm5786006wma.2.2020.05.15.15.13.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 15:13:39 -0700 (PDT) Date: Fri, 15 May 2020 23:13:37 +0100 From: "Leif Lindholm" To: Pankaj Bansal Cc: Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: Re: [PATCH edk2-platforms v5 12/24] Silicon/NXP: Move RAM retrieval from SocLib Message-ID: <20200515221337.GZ21486@vanye> References: <20200515052952.20914-1-pankaj.bansal@oss.nxp.com> <20200515052952.20914-2-pankaj.bansal@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <20200515052952.20914-2-pankaj.bansal@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, May 15, 2020 at 10:59:52 +0530, Pankaj Bansal wrote: > From: Pankaj Bansal > > RAM retrieval using SMC commands is common to all Layerscape SOCs. > Therefore, move it to common MemoryInit Pei Lib. > > Signed-off-by: Pankaj Bansal Thanks! Reviewed-by: Leif Lindholm 12-24/24 pushed as c2cb5a4d1b54..459cfc6bd38e. / Leif > --- > > Notes: > V5: > - Add SMC_DRAM_TOTAL_DRAM_ARG1 to denote the x1 argument to pass to > SMC call to retrieve the total DRAM size > - cast away the return from GetDramRegionsInfo using (VOID)GetDramRegionsInfo > - remove unused variable Status from MemoryPeim. > > V4: > - fixed line adds white space error in MemoryInitPeiLib.h > - Added SMC_OK and SMC_UOK Macros to denote the return values from > SMC calls > - Added explanation for SMC_DRAM_BANK_INFO and DRAM_REGION_INFO in > MemoryInitPeiLib.h > - Modified GetDramSize to check for return value of SMC call against > SMC_OK. Also added comments when returning 0 from this function > - Modified GetDramRegionsInfo for loop and return values as per Leif's > suggestion. Also added DEBUG_ERROR in case of return BUFFER_TOO_SMALL. > - Added SMC_OK in GetDramRegionsInfo > - Check for GetDramRegionsInfo return value in MemoryPeim > - regios -> regions > > V3: > - sort headers alphabetically > - Moved DRAM region retrieval and Total DRAM size retrieval to separate > functions > - Fixed MemoryPeim function description > - Modified check on FoundSystemMem = TRUE to check the RAM region against > MemoryPeim function input arguments UefiMemoryBase and UefiMemorySize > - (!DramRegions[Index].Size) => (DramRegions[Index].Size == 0) > - (FoundSystemMem) => (FoundSystemMem == TRUE) > - Added explanation for starting for loop from the last DRAM region > > Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 7 +- > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 - > Silicon/NXP/Include/DramInfo.h | 38 ---- > Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h | 40 ++++ > Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 203 ++++++++++++++++---- > Silicon/NXP/Library/SocLib/Chassis.c | 67 ------- > 6 files changed, 211 insertions(+), 145 deletions(-) > > diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf > index a5bd39415def..ad2371115b17 100644 > --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf > +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf > @@ -18,7 +18,6 @@ > [Sources] > MemoryInitPeiLib.c > > - > [Packages] > ArmPkg/ArmPkg.dec > ArmPlatformPkg/ArmPlatformPkg.dec > @@ -30,6 +29,7 @@ > [LibraryClasses] > ArmMmuLib > ArmPlatformLib > + ArmSmcLib > DebugLib > HobLib > PcdLib > @@ -40,6 +40,11 @@ > [FeaturePcd] > gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob > > +[FixedPcd] > + gArmTokenSpaceGuid.PcdFdBaseAddress > + gArmTokenSpaceGuid.PcdFdSize > + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize > + > [Pcd] > gArmTokenSpaceGuid.PcdSystemMemoryBase > gArmTokenSpaceGuid.PcdSystemMemorySize > diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > index b7c7fc78cc8f..99d89498e0e2 100644 > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > @@ -20,7 +20,6 @@ > Silicon/NXP/NxpQoriqLs.dec > > [LibraryClasses] > - ArmSmcLib > BaseLib > DebugLib > IoAccessLib > diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h > deleted file mode 100644 > index a934aaeff1f5..000000000000 > --- a/Silicon/NXP/Include/DramInfo.h > +++ /dev/null > @@ -1,38 +0,0 @@ > -/** @file > -* Header defining the structure for Dram Information > -* > -* Copyright 2019 NXP > -* > -* SPDX-License-Identifier: BSD-2-Clause-Patent > -* > -**/ > - > -#ifndef DRAM_INFO_H_ > -#define DRAM_INFO_H_ > - > -#include > - > -#define SMC_DRAM_BANK_INFO (0xC200FF12) > - > -typedef struct { > - UINTN BaseAddress; > - UINTN Size; > -} DRAM_REGION_INFO; > - > -typedef struct { > - UINT32 NumOfDrams; > - UINT32 Reserved; > - DRAM_REGION_INFO DramRegion[3]; > -} DRAM_INFO; > - > -EFI_STATUS > -GetDramBankInfo ( > - IN OUT DRAM_INFO *DramInfo > - ); > - > -VOID > -UpdateDpaaDram ( > - IN OUT DRAM_INFO *DramInfo > - ); > - > -#endif /* DRAM_INFO_H_ */ > diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h > new file mode 100644 > index 000000000000..520277d45c95 > --- /dev/null > +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h > @@ -0,0 +1,40 @@ > +/** @file > +* > +* Copyright 2020 NXP > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#ifndef MEMORY_INIT_PEI_LIB_H_ > +#define MEMORY_INIT_PEI_LIB_H_ > + > +#include > + > +// Specifies the Maximum regions onto which DDR memory can be mapped in > +// a Platform > +#define MAX_DRAM_REGIONS 3 > + > +// Unique SMC call to retrieve the total DDR RAM size installed in system > +// and the SOC memory map regions to which DDR RAM is mapped > +// This SMC call works in this way: > +// x1 = -1 : return x0: SMC_OK, x1: total DDR Ram size > +// x1 >= number of DRAM regions to which DDR RAM is mapped : return x0: SMC_UNK > +// 0 <= x1 < number of DRAM regions to which DDR RAM is mapped : return > +// x0: SMC_OK, x1: Base address of DRAM region, > +// x2: Size of DRAM region > +#define SMC_DRAM_BANK_INFO (0xC200FF12) > + > +#define SMC_DRAM_TOTAL_DRAM_ARG1 (-1) > + > +// Return values from SMC calls. return values are always in x0 > +#define SMC_OK (0) > +#define SMC_UNK (-1) > + > +// Regions in SOC memory map to which DDR RAM is mapped. > +typedef struct { > + UINTN BaseAddress; > + UINTN Size; > +} DRAM_REGION_INFO; > + > +#endif // MEMORY_INIT_PEI_LIB_H_ > diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c > index 3ea773678667..e4fdc403f121 100644 > --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c > +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c > @@ -12,13 +12,15 @@ > > #include > #include > +#include > #include > #include > #include > #include > #include > > -#include > +#include "MemoryInitPeiLib.h" > + > > VOID > BuildMemoryTypeInformationHob ( > @@ -44,22 +46,88 @@ InitMmu ( > } > } > > -/*++ > +STATIC > +UINTN > +GetDramSize ( > + IN VOID > + ) > +{ > + ARM_SMC_ARGS ArmSmcArgs; > > -Routine Description: > + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO; > + ArmSmcArgs.Arg1 = SMC_DRAM_TOTAL_DRAM_ARG1; > > + ArmCallSmc (&ArmSmcArgs); > > + if (ArmSmcArgs.Arg0 == SMC_OK) { > + return ArmSmcArgs.Arg1; > + } > > -Arguments: > + // return 0 means no DDR found. > + return 0; > +} > > - FileHandle - Handle of the file being invoked. > - PeiServices - Describes the list of possible PEI Services. > +STATIC > +EFI_STATUS > +GetDramRegionsInfo ( > + OUT DRAM_REGION_INFO *DramRegions, > + IN UINT32 NumRegions > + ) > +{ > + ARM_SMC_ARGS ArmSmcArgs; > + UINT32 Index; > + UINTN RemainingDramSize; > + UINTN BaseAddress; > + UINTN Size; > > -Returns: > + RemainingDramSize = GetDramSize (); > + DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", RemainingDramSize)); > > - Status - EFI_SUCCESS if the boot mode could be set > + // Ensure Total Dram Size is valid > + ASSERT (RemainingDramSize != 0); > > ---*/ > + for (Index = 0; Index < NumRegions; Index++) { > + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO; > + ArmSmcArgs.Arg1 = Index; > + > + ArmCallSmc (&ArmSmcArgs); > + > + if (ArmSmcArgs.Arg0 == SMC_OK) { > + BaseAddress = ArmSmcArgs.Arg1; > + Size = ArmSmcArgs.Arg2; > + ASSERT (BaseAddress && Size); > + > + DramRegions[Index].BaseAddress = BaseAddress; > + DramRegions[Index].Size = Size; > + RemainingDramSize -= Size; > + > + DEBUG ((DEBUG_INFO, "DRAM Region[%d]: start 0x%lx, size 0x%lx\n", > + Index, BaseAddress, Size)); > + > + if (RemainingDramSize == 0) { > + return EFI_SUCCESS; > + } > + } else { > + break; > + } > + } > + > + DEBUG ((DEBUG_ERROR, "RemainingDramSize = %u !! Ensure that all DDR regions " > + "have been accounted for\n", RemainingDramSize)); > + > + return EFI_BUFFER_TOO_SMALL; > +} > + > +/** > + Get the installed RAM information. > + Initialize MMU and Memory HOBs (Resource Descriptor HOBs) > + > + @param[in] UefiMemoryBase Base address of region used by UEFI in > + permanent memory > + @param[in] UefiMemorySize Size of the region used by UEFI in permanent memory > + > + @return EFI_SUCCESS Successfuly Initialize MMU and Memory HOBs. > +**/ > EFI_STATUS > EFIAPI > MemoryPeim ( > @@ -67,11 +135,16 @@ MemoryPeim ( > IN UINT64 UefiMemorySize > ) > { > - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; > - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > - EFI_PEI_HOB_POINTERS NextHob; > - BOOLEAN Found; > - DRAM_INFO DramInfo; > + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; > + INT32 Index; > + UINTN BaseAddress; > + UINTN Size; > + UINTN Top; > + DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS]; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + UINTN FdBase; > + UINTN FdTop; > + BOOLEAN FoundSystemMem; > > // Get Virtual Memory Map from the Platform Library > ArmPlatformGetVirtualMemoryMap (&MemoryTable); > @@ -94,40 +167,94 @@ MemoryPeim ( > EFI_RESOURCE_ATTRIBUTE_TESTED > ); > > - if (GetDramBankInfo (&DramInfo)) { > - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n")); > - return EFI_UNSUPPORTED; > - } > + FoundSystemMem = FALSE; > + ZeroMem (DramRegions, sizeof (DramRegions)); > > - while (DramInfo.NumOfDrams--) { > - // > - // Check if the resource for the main system memory has been declared > - // > - Found = FALSE; > - NextHob.Raw = GetHobList (); > - while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) { > - if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) && > - (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) && > - (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <= > - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size)) > - { > - Found = TRUE; > - break; > - } > - NextHob.Raw = GET_NEXT_HOB (NextHob); > + (VOID)GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions)); > + > + FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress); > + FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize); > + > + // Declare memory regions to system > + // The DRAM region info is sorted based on the RAM address is SOC memory map. > + // i.e. DramRegions[0] is at lower address, as compared to DramRegions[1]. > + // The goal to start from last region is to find the topmost RAM region that > + // can contain UEFI DXE region i.e. PcdSystemMemoryUefiRegionSize. > + // If UEFI were to allocate any reserved or runtime region, it would be > + // allocated from topmost RAM region. > + // This ensures that maximum amount of lower RAM (32 bit addresses) are left > + // for OS to allocate to devices that can only work with 32bit physical > + // addresses. E.g. legacy devices that need to DMA to 32bit addresses. > + for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) { > + if (DramRegions[Index].Size == 0) { > + continue; > } > > - if (!Found) { > - // Reserved the memory space occupied by the firmware volume > + BaseAddress = DramRegions[Index].BaseAddress; > + Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size; > + > + // EDK2 does not have the concept of boot firmware copied into DRAM. > + // To avoid the DXE core to overwrite this area we must create a memory > + // allocation HOB for the region, but this only works if we split off the > + // underlying resource descriptor as well. > + if (FdBase >= BaseAddress && FdTop <= Top) { > + // Update Size > + Size = FdBase - BaseAddress; > + if (Size) { > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + BaseAddress, > + Size > + ); > + } > + // create the System Memory HOB for the firmware > BuildResourceDescriptorHob ( > EFI_RESOURCE_SYSTEM_MEMORY, > ResourceAttributes, > - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress, > - DramInfo.DramRegion[DramInfo.NumOfDrams].Size > + FdBase, > + PcdGet32 (PcdFdSize) > ); > + // Create the System Memory HOB for the remaining region (top of the FD)s > + Size = Top - FdTop; > + if (Size) { > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + FdTop, > + Size > + ); > + }; > + // Mark the memory covering the Firmware Device as boot services data > + BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress), > + FixedPcdGet32 (PcdFdSize), > + EfiBootServicesData); > + } else { > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + DramRegions[Index].BaseAddress, > + DramRegions[Index].Size > + ); > + } > + > + if (FoundSystemMem == TRUE) { > + continue; > + } > + > + Size = DramRegions[Index].Size; > + > + if (FdBase >= BaseAddress && FdTop <= Top) { > + Size -= (UINTN)FixedPcdGet32 (PcdFdSize); > + } > + > + if ((UefiMemoryBase >= BaseAddress) && (Size >= UefiMemorySize)) { > + FoundSystemMem = TRUE; > } > } > > + ASSERT (FoundSystemMem == TRUE); > + > // Build Memory Allocation Hob > InitMmu (MemoryTable); > > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c > index 847331a63152..1ef99e8de25f 100644 > --- a/Silicon/NXP/Library/SocLib/Chassis.c > +++ b/Silicon/NXP/Library/SocLib/Chassis.c > @@ -22,7 +22,6 @@ > #include > #include > > -#include > #include "NxpChassis.h" > > UINT32 > @@ -75,69 +74,3 @@ SmmuInit ( > MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); > } > > -UINTN > -GetDramSize ( > - IN VOID > - ) > -{ > - ARM_SMC_ARGS ArmSmcArgs; > - > - ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO; > - ArmSmcArgs.Arg1 = -1; > - > - ArmCallSmc (&ArmSmcArgs); > - > - if (ArmSmcArgs.Arg0) { > - return 0; > - } else { > - return ArmSmcArgs.Arg1; > - } > -} > - > -EFI_STATUS > -GetDramBankInfo ( > - IN OUT DRAM_INFO *DramInfo > - ) > -{ > - ARM_SMC_ARGS ArmSmcArgs; > - UINT32 I; > - UINTN DramSize; > - > - DramSize = GetDramSize (); > - DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize)); > - > - // Ensure DramSize has been set > - ASSERT (DramSize != 0); > - > - I = 0; > - > - do { > - ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO; > - ArmSmcArgs.Arg1 = I; > - > - ArmCallSmc (&ArmSmcArgs); > - if (ArmSmcArgs.Arg0) { > - if (I > 0) { > - break; > - } else { > - ASSERT (ArmSmcArgs.Arg0 == 0); > - } > - } > - > - DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1; > - DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2; > - > - DramSize -= DramInfo->DramRegion[I].Size; > - > - DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", > - I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size)); > - > - I++; > - } while (DramSize); > - > - DramInfo->NumOfDrams = I; > - > - DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams)); > - > - return EFI_SUCCESS; > -} > -- > 2.17.1 >