From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.groups.io with SMTP id smtpd.web12.1378.1589821945283125905 for ; Mon, 18 May 2020 10:12:25 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=ExxQ1kvk; spf=pass (domain: nuviainc.com, ip: 209.85.221.68, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f68.google.com with SMTP id v12so12710200wrp.12 for ; Mon, 18 May 2020 10:12:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=RiQAN7ctpoeUdKv9FyQNJaO+ILuS0KV7hg2atCwYE5o=; b=ExxQ1kvkLNrQCte26R5IWptiRKzWGKQx4fpLjQIXWt+TzDuQVQ9hWOzap0gJFx4aW1 rV/GaG5U79FAumAe39iSEiVuVDtoCFtdGWWHN+6d3/Vr0Rx/0GA89i6S2ktYzdjsPhjb Zq5z0bEkoUjGNzTrusF9rRUNQANcolwvyhP/5bbg7HmbbdwhWWC2R2kEMzhP2yV67bs5 us1Gv99BBw+hcpI8A41vvwD7ogHD04R9Pxh1o10ot9XzvJDN8WPBzwsFhTZfqSpjlhjT pnIBK84M3tsvDWm3qjU4eFUuMEDBYMJ/2Gc4gI8hibw8Y3B/xwVtKtWB1FzU4pl/k5sf ywaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=RiQAN7ctpoeUdKv9FyQNJaO+ILuS0KV7hg2atCwYE5o=; b=Iz8MHmETmEYkRnyOwv8UQGOsZybWyW0a4IHeAg+eC4ycnCOTmpQsYqhO2DLuKQpc18 ZXprjJja9XXVqFV/SpcuYc+s5kuEN19/7rMRU5eoNOp06PPM5VziA/Vu5lgt0h8I6OSC scHkGVLqLC3p05E/Kuogx17y4DBAaK2mwpCkQUZyQJ2G1aZlP7CulJY9vi+Y2FmF2B+T gZfb2lP/wq5fAnzVsqUrTI0XrBP1Q2eCC+JYUF2ryWbnAz6g87flpjyW/0UXBYDRjzGx LzDAQohKpmoanocuOSZs+i05fF2DCTfz4rQhfIcCMgmfCyhv2rPY0o8Bz6/iy7HD1pJv brDw== X-Gm-Message-State: AOAM532RxutITHLOTSnQusARM1IGn0rFzlrS9zoB4afEvotJgEF49dvJ vc+Z+t3kuhEOKElpduz1CIOfRQ== X-Google-Smtp-Source: ABdhPJxGDbPbNKYkZrpj22/1fgiE1U6P9CNIyxnhXeIUu3ePNGTJgbEJ577Qg1TN+urV0VdflC3o2w== X-Received: by 2002:adf:e74a:: with SMTP id c10mr21232166wrn.109.1589821943867; Mon, 18 May 2020 10:12:23 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id h20sm267531wma.6.2020.05.18.10.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2020 10:12:23 -0700 (PDT) Date: Mon, 18 May 2020 18:12:21 +0100 From: "Leif Lindholm" To: Marcin Wojtas Cc: devel@edk2.groups.io, ard.biesheuvel@arm.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: Re: [edk2-platforms: PATCH v2 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings Message-ID: <20200518171221.GC10467@vanye> References: <1589576758-28501-1-git-send-email-mw@semihalf.com> <1589576758-28501-2-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1589576758-28501-2-git-send-email-mw@semihalf.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, May 15, 2020 at 23:05:56 +0200, Marcin Wojtas wrote: > This patch introduce following modifications, allowing to > overcome the instabilities observed with certain USB2.0 endpoints: > * Add additional step which enables the Impedance and PLL calibration. > * Enable old squelch detector instead of the new analog squelch detector > circuit and update host disconnect threshold value. > * Update LS TX driver strength coarse and fine adjustment values. > > Signed-off-by: Grzegorz Jaszczyk > Signed-off-by: Marcin Wojtas I'm OK with the current version of the code, but just noticed this. No one can give Signed-off-by for another. If Grzegorz is the author, that should be noted in a From: tag. Git format-patch does this automatically if the commit's Author metadata is set. This applies to all 3 patches. / Leif > --- > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 10 +++++++++- > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 18 ++++++++++++++---- > 2 files changed, 23 insertions(+), 5 deletions(-) > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > index 20e3133..8659110 100644 > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > @@ -44,6 +44,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define UTMI_CALIB_CTRL_REG 0x8 > #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 > #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) > +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 > +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET) > +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 > +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET) > #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 > #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) > #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 > @@ -54,8 +58,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) > +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 > +#define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) > > #define UTMI_RX_CH_CTRL0_REG 0x14 > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) > #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 > #define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) > #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 > @@ -63,7 +71,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #define UTMI_RX_CH_CTRL1_REG 0x18 > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 > -#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > index 3881ebd..42f38db 100644 > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > @@ -118,23 +118,33 @@ UtmiPhyConfig ( > > /* Impedance Calibration Threshold Setting */ > RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, > - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > + 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); > > + /* Start Impedance and PLL Calibration */ > + Mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; > + Data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); > + Mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; > + Data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > + > /* Set LS TX driver strength coarse control */ > Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > - /* Set LS TX driver fine adjustment */ > + Mask |= UTMI_TX_CH_CTRL_AMP_MASK; > + Data |= 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); > > /* Enable SQ */ > Mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; > - Data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > + Data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > /* Enable analog squelch detect */ > Mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; > - Data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > + Data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > + Mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; > + Data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; > RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask); > > /* Set External squelch calibration number */ > -- > 2.7.4 >