From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web12.955.1589825777544892671 for ; Mon, 18 May 2020 11:16:17 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=VCw7SDea; spf=pass (domain: nuviainc.com, ip: 209.85.128.67, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f67.google.com with SMTP id f134so472458wmf.1 for ; Mon, 18 May 2020 11:16:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=vmpPgYh5w79MtS9cTjQdGsrDrY3k+HKvAsIQ8zYh1ws=; b=VCw7SDeavbsYiKU6UosphGVW5O2M9P+ws9s59fXJjcIrb5ntUDWWHPTaGpNobnIZY0 4UJ0P+FCMMinEXx1lZjE0yadX1B4ySviK3NQ7q5BQbSH+dISbaHRgU0yFiBn1H6arJ+D cVzawrhW2nnHmq8HdJ5CKD9el8f++mozP1NlHMF2VTtbNSEqNAEhm147kQuh0awyTURW rvl814YMIQf8Jz40LbPYykaN4WX5rIrgeh9+VDrg3/ZU9Sy52kDw2KwGuS9yd8lSJUwJ j3PsXZw6jsC3yd5DXuNFOv80tzDjZEUVu3rQRC+ucBWouo1rCDQFDeM9iLXOvQbATrqr jC2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=vmpPgYh5w79MtS9cTjQdGsrDrY3k+HKvAsIQ8zYh1ws=; b=ishwz+GPEEYwYvKb2VJpOcxPrdnN+ft9ymRQPM37Ie+YiD/XDHLzTNf8su5fKpS9yV AnLfqZp/NCawoPXp/fNOf5ifXZGE5X4YGGzaZ79pCuvwEBtJyPv16hypQE0NAzT5DUzj ng2FBe9gjnJrM1uMjBcBUGZyX6YjklgNrYmzdQdPt1ci9kuWATnE3B2MTwU9h+xP3Qad znmN6n3aZfD7vmqocwwr72ZwDMFalRIlj1rNPT33lVar4KuNoJY4Z1ew/VvTUwwch4TI ZRht3B3PeEhzeAWT5q167GJguravD3XAhzC5M4CEKb6XzfngDrRrl8lKsZU/me6Ja2Ab WFIw== X-Gm-Message-State: AOAM5325gBH7C4+9UtKhwYUX6xcQyYFdedvsEYo3eJ7rAQHAvcQ3deV6 cwjezAOZmYJuSm8uogLCw1Kqnw== X-Google-Smtp-Source: ABdhPJx8SnXby2zO/7fLHpXG5FSmXz7I0ZUTy6F8cniydRLxiIcKDwxde5QPl449Cj+OWk00Eo2H0g== X-Received: by 2002:a1c:3281:: with SMTP id y123mr671476wmy.30.1589825775953; Mon, 18 May 2020 11:16:15 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id r9sm409843wmg.47.2020.05.18.11.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2020 11:16:15 -0700 (PDT) Date: Mon, 18 May 2020 19:16:13 +0100 From: "Leif Lindholm" To: Marcin Wojtas Cc: edk2-devel-groups-io , ard.biesheuvel@arm.com, "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin Subject: Re: [edk2-platforms: PATCH v2 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings Message-ID: <20200518181613.GJ10467@vanye> References: <1589576758-28501-1-git-send-email-mw@semihalf.com> <1589576758-28501-2-git-send-email-mw@semihalf.com> <20200518171221.GC10467@vanye> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Mon, May 18, 2020 at 20:11:49 +0200, Marcin Wojtas wrote: > Hi Leif, > > pon., 18 maj 2020 o 19:12 Leif Lindholm napisał(a): > > > > On Fri, May 15, 2020 at 23:05:56 +0200, Marcin Wojtas wrote: > > > This patch introduce following modifications, allowing to > > > overcome the instabilities observed with certain USB2.0 endpoints: > > > * Add additional step which enables the Impedance and PLL calibration. > > > * Enable old squelch detector instead of the new analog squelch detector > > > circuit and update host disconnect threshold value. > > > * Update LS TX driver strength coarse and fine adjustment values. > > > > > > Signed-off-by: Grzegorz Jaszczyk > > > Signed-off-by: Marcin Wojtas > > > > I'm OK with the current version of the code, but just noticed this. > > No one can give Signed-off-by for another. > > If Grzegorz is the author, that should be noted in a From: tag. Git > > format-patch does this automatically if the commit's Author metadata > > is set. > > > > This applies to all 3 patches. > > > > The 3/3 has only only my signed-off tag (and my authorship). OK, I admit it, I was lazy and spotted this and only checked 2/3 and assumed it was all of them :) > Regarding the first 2, I did the actual change, but it was based on > the original U-Boot patch from Grzegorz. How about, instead of the tag, > I give him a credit in a following way: > > Based on the original U-Boot patch from Grzegorz Jaszczyk > > Would that work for you? I have no objections to that as such, but perhaps a link to the patch posting in an email archive, or the commit in a git repo, would be more generically useful. Best Regards, Leif > Best regards, > Marcin > > > > > > --- > > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 10 +++++++++- > > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 18 ++++++++++++++---- > > > 2 files changed, 23 insertions(+), 5 deletions(-) > > > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > index 20e3133..8659110 100644 > > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > @@ -44,6 +44,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > #define UTMI_CALIB_CTRL_REG 0x8 > > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 > > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) > > > +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 > > > +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET) > > > +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 > > > +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET) > > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 > > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) > > > #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 > > > @@ -54,8 +58,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) > > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 > > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) > > > +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 > > > +#define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) > > > > > > #define UTMI_RX_CH_CTRL0_REG 0x14 > > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 > > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) > > > #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 > > > #define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) > > > #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 > > > @@ -63,7 +71,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > #define UTMI_RX_CH_CTRL1_REG 0x18 > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 > > > -#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > > > +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) > > > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > index 3881ebd..42f38db 100644 > > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > @@ -118,23 +118,33 @@ UtmiPhyConfig ( > > > > > > /* Impedance Calibration Threshold Setting */ > > > RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, > > > - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > > > + 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > > > UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); > > > > > > + /* Start Impedance and PLL Calibration */ > > > + Mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; > > > + Data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); > > > + Mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; > > > + Data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); > > > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > > > + > > > /* Set LS TX driver strength coarse control */ > > > Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > > > Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > > > - /* Set LS TX driver fine adjustment */ > > > + Mask |= UTMI_TX_CH_CTRL_AMP_MASK; > > > + Data |= 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > > > Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > > > Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > > > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); > > > > > > /* Enable SQ */ > > > Mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; > > > - Data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > > + Data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > > /* Enable analog squelch detect */ > > > Mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; > > > - Data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > > + Data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > > + Mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; > > > + Data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; > > > RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask); > > > > > > /* Set External squelch calibration number */ > > > -- > > > 2.7.4 > > >