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This SOC is based on Layerscape Chassis v3.2. Signed-off-by: Pankaj Bansal --- Silicon/NXP/LX2160A/LX2160A.dec | 13 ++++ Silicon/NXP/LX2160A/LX2160A.dsc.inc | 50 ++++++++++++ Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf | 27 +++++++ Silicon/NXP/LX2160A/Include/Soc.h | 38 ++++++++++ Silicon/NXP/LX2160A/Library/SocLib/SocLib.c | 80 ++++++++++++++++++++ 5 files changed, 208 insertions(+) diff --git a/Silicon/NXP/LX2160A/LX2160A.dec b/Silicon/NXP/LX2160A/LX2160A.= dec new file mode 100644 index 000000000000..b39a44692361 --- /dev/null +++ b/Silicon/NXP/LX2160A/LX2160A.dec @@ -0,0 +1,13 @@ +# LX2160A.dec +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + +[Includes] + Include diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/LX2160A/LX21= 60A.dsc.inc new file mode 100644 index 000000000000..65c1b6e567b3 --- /dev/null +++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc @@ -0,0 +1,50 @@ +# LX2160A.dsc +# LX2160A Soc package. +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc + +[LibraryClasses.common] + SocLib|Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf + + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL= ib.inf + PL011UartClockLib|Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLi= b.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsDynamicDefault.common] + # + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6200000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xC0C0000 + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A0000 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2390000 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|91 + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C0000 + +[PcdsFeatureFlag] + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + +## diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf b/Silicon/NXP/LX= 2160A/Library/SocLib/SocLib.inf new file mode 100644 index 000000000000..70e14bbabe64 --- /dev/null +++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf @@ -0,0 +1,27 @@ +# @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocLib + FILE_GUID =3D e868c5ca-9729-43ae-bff4-438c67de8c68 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SocLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/Chassis3V2/Chassis3V2.dec + Silicon/NXP/LX2160A/LX2160A.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ChassisLib + DebugLib + +[Sources.common] + SocLib.c diff --git a/Silicon/NXP/LX2160A/Include/Soc.h b/Silicon/NXP/LX2160A/Includ= e/Soc.h new file mode 100644 index 000000000000..626e3a0cee07 --- /dev/null +++ b/Silicon/NXP/LX2160A/Include/Soc.h @@ -0,0 +1,38 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SOC_H__ +#define SOC_H__ + +#include + +/** + Soc Memory Map +**/ +#define LX2160A_DRAM0_PHYS_ADDRESS (BASE_2GB) +#define LX2160A_DRAM0_SIZE (SIZE_2GB) +#define LX2160A_DRAM1_PHYS_ADDRESS (BASE_128GB + BASE_2GB) +#define LX2160A_DRAM1_SIZE (SIZE_128GB - SIZE_2GB) // 126 GB +#define LX2160A_DRAM2_PHYS_ADDRESS (BASE_256GB + BASE_128GB) +#define LX2160A_DRAM2_SIZE (SIZE_128GB) + +#define LX2160A_CCSR_PHYS_ADDRESS (BASE_16MB) +#define LX2160A_CCSR_SIZE (SIZE_256MB - SIZE_16MB) // 240MB + +#define LX2160A_FSPI0_PHYS_ADDRESS (BASE_512MB) +#define LX2160A_FSPI0_SIZE (SIZE_256MB) + +#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRES= S + +/** + Reset Control Word (RCW) Bits +**/ +#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 + +typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG; + +#endif // SOC_H__ diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.c b/Silicon/NXP/LX21= 60A/Library/SocLib/SocLib.c new file mode 100644 index 000000000000..ed6b30ae8599 --- /dev/null +++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.c @@ -0,0 +1,80 @@ +/** @Soc.c + SoC specific Library containg functions to initialize various SoC compon= ents + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Return the input clock frequency to an IP Module. + This function reads the RCW bits and calculates the PLL multiplier/divi= der + values to be applied to various IP modules. + If a module is disabled or doesn't exist on platform, then return zero. + + @param[in] BaseClock Base clock to which PLL multiplier/divider values= is + to be applied. + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] Args Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within th= e + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +SocGetClock ( + IN UINT64 BaseClock, + IN NXP_IP_CLOCK ClockType, + IN VA_LIST Args + ) +{ + LX2160A_DEVICE_CONFIG *Dcfg; + UINT32 RcwSr; + UINT64 ReturnValue; + + ReturnValue =3D 0; + Dcfg =3D (LX2160A_DEVICE_CONFIG *)LX2160A_DCFG_ADDRESS; + + switch (ClockType) { + case NXP_UART_CLOCK: + RcwSr =3D DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]); + ReturnValue =3D (BaseClock * SYS_PLL_RAT (RcwSr)) >> 3; + break; + case NXP_I2C_CLOCK: + RcwSr =3D DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]); + ReturnValue =3D (BaseClock * SYS_PLL_RAT (RcwSr)) >> 4; + break; + default: + break; + } + + return ReturnValue; +} + +/** + Function to initialize SoC specific constructs + **/ +VOID +SocInit ( + VOID + ) +{ + ChassisInit (); + + return; +} --=20 2.17.1