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X-MS-Exchange-AntiSpam-MessageData: 8IETeJ2BdBcRxuqZ8VUQEWLG36i72IxY5PW2b34y/K8VqlSOyl7NDDg0On7xteKjasXoU92CGL5LZz/0jwUkb0Ugk5lcIDwaLVQzhKlV4Y52m71icoMqlsbJNPaXV9T/dQJ6ct9NP3PyrDlj7pw8OilXjnL7rkdqa0fftukCw8F0Y3onwP5l/SoGZrzoVkqHwcxTMqfseVXOZ+BGOdM4zymAaGCKTpvfv8qJovaDDHn9dOO8lKttezbAC5I/kZAxwh8rRif26EHI9e6VP+atEoBdFZ2V/9i4ecSaBczV6U/8CKFoRAswt7rDYnSqTit62XzT7gTNfRcBL3fNQCc/g62CPPyRFAMrQilrRy8iLTm2fPEnQb6nznMp7OBkFHP5XEUBw0I0IKTAbzSK8+vt1b5g2hgI72/slhNv+sQpW1Zjc2XsRWe/HcxMQ3GdmMlsuGlz5aCbdJ9lxhE4lE+O60CljosI7kjd5HFclHWSjdI= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 60b5b9b7-6585-4e88-d4b6-08d7fc711416 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2020 03:51:29.7147 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JyNT2VY5vRxPQZj/Ow4pSWbsNUP9drnnJBeIZX6uvnBWY0CrpV1Iw8pasOt8PFyeGYih/lBUcWhCyDXLgg/Ckg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5421 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Pankaj Bansal LX2160A Reference Design Board (RDB) is a high-performance development platform that supports the QorIQ LX2160A Layerscape Architecture SOCs. Signed-off-by: Pankaj Bansal --- Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec = | 23 +++ Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc = | 46 ++++++ Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf = | 168 ++++++++++++++++++++ Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf = | 41 +++++ Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c = | 150 +++++++++++++++++ Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c = | 85 ++++++++++ Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelpe= r.S | 45 ++++++ 7 files changed, 558 insertions(+) diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.dec new file mode 100644 index 000000000000..192eabc5b3f2 --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec @@ -0,0 +1,23 @@ +# LX2160aRdbPkg.dec +# LX2160a board package. +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + PACKAGE_NAME =3D LX2160aRdbPkg + PACKAGE_GUID =3D 6eba6648-d853-4eb3-9761-528b82d5ab04 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.dsc new file mode 100644 index 000000000000..c292f3b8bff4 --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc @@ -0,0 +1,46 @@ +# LX2160aRdbPkg.dsc +# +# LX2160ARDB Board package. +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_NAME =3D LX2160aRdbPkg + PLATFORM_GUID =3D 60169ec4-d2b4-44f8-825e-f8684fd42e4f + OUTPUT_DIRECTORY =3D Build/LX2160aRdbPkg + FLASH_DEFINITION =3D Platform/NXP/LX2160aRdbPkg/LX2160aRdb= Pkg.fdf + +!include Silicon/NXP/NxpQoriqLs.dsc.inc +!include Silicon/NXP/LX2160A/LX2160A.dsc.inc + +[LibraryClasses.common] + ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlat= formLib.inf + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal= TimeClockLib.inf + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # Architectural Protocols + # + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + } + + ## diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.fdf new file mode 100644 index 000000000000..6bd5d86ab2bd --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf @@ -0,0 +1,168 @@ +# LX2160aRdbPkg.fdf +# +# FLASH layout file for LX2160a board. +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.LX2160ARDB_EFI] +BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. +Size =3D 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x10000 +NumBlocks =3D 0x14 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### +0x00000000|0x00140000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +!include Platform/NXP/FVRules.fdf.inc +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 1037c42b-8452-4c41-aac7-41e6c31468da +BlockSize =3D 0x1 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.i= nf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.inf b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.i= nf new file mode 100644 index 000000000000..94c88f2be4fb --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -0,0 +1,41 @@ +# @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformLib + FILE_GUID =3D 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis3V2/Chassis3V2.dec + Silicon/NXP/LX2160A/LX2160A.dec + +[LibraryClasses] + ArmLib + SocLib + +[Sources.common] + ArmPlatformLibMem.c + ArmPlatformLib.c + +[Sources.AArch64] + AArch64/ArmPlatformHelper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c new file mode 100644 index 000000000000..c1bc5510cd6d --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -0,0 +1,150 @@ +/** ArmPlatformLib.c +* +* Contains board initialization functions. +* +* Copyright 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +#include +#include + +ARM_CORE_INFO mLX2160aMpCoreInfoTable[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs + + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] ... Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. + if ClockType is NXP_CORE_CLOCK, then second argum= ent + is interpreted as cluster number and third argume= nt is + interpreted as core number (within the cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +EFIAPI +NxpPlatformGetClock( + IN UINT32 ClockType, + ... + ) +{ + UINT64 Clock; + VA_LIST Args; + + Clock =3D 0; + + VA_START (Args, ClockType); + + switch (ClockType) { + case NXP_SYSTEM_CLOCK: + Clock =3D 100 * 1000 * 1000; // 100 MHz + break; + case NXP_I2C_CLOCK: + case NXP_UART_CLOCK: + Clock =3D NxpPlatformGetClock (NXP_SYSTEM_CLOCK); + Clock =3D SocGetClock (Clock, ClockType, Args); + break; + default: + break; + } + + VA_END (Args); + + return Clock; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/Pl= atformPei + in the PEI phase. + +**/ +EFI_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + SocInit (); + + return EFI_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + if (ArmIsMpCore()) { + *CoreCount =3D sizeof(mLX2160aMpCoreInfoTable) / sizeof(ARM_CORE_IN= FO);; + *ArmCoreTable =3D mLX2160aMpCoreInfoTable; + } else { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi =3D { NxpPlatformGetClock = }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + if (ArmIsMpCore()) { + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; + } else { + *PpiListSize =3D 0; + *PpiList =3D NULL; + } +} diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ibMem.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibM= em.c new file mode 100644 index 000000000000..0855003632a3 --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c @@ -0,0 +1,85 @@ +/** NxpQoriqLsMem.c +* +* Board memory specific Library. +* +* Copyright 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize + the MMU on your platform. + + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing + a Physical-to-Virtual Memory mapping. This = array + must be ended by a zero-filled entry + +**/ + +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + Index =3D 0; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTO= R) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + if (VirtualMemoryTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION_= _)); + return; + } + + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_DRAM0_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_DRAM1_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_DRAM2_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_DRAM2_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_DRAM2_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // CCSR Space + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_CCSR_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // FlexSPI + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_FSPI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_FSPI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_FSPI0_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // End of Table + ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTO= R)); + + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmP= latformHelper.S b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64= /ArmPlatformHelper.S new file mode 100644 index 000000000000..b7c6dbdc2e61 --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatform= Helper.S @@ -0,0 +1,45 @@ +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// + +#include +#include + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore)) + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq + ret --=20 2.17.1