From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.groups.io with SMTP id smtpd.web12.9936.1589970503509837973 for ; Wed, 20 May 2020 03:28:23 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=huj+QNwh; spf=pass (domain: nuviainc.com, ip: 209.85.128.65, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f65.google.com with SMTP id z4so2049182wmi.2 for ; Wed, 20 May 2020 03:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=h75nkbhTYtyJJTOXLQJCYo5pUIkcCdOrO0xFrVv9ewQ=; b=huj+QNwh9CmdGBy2jkN5f0qkRVlE6+lJasOgNpPEOB6h9sJZwG0qYM46ulE8vzlzvn RecZ/PukTnlpzFnAKcWH1ei9DE0o9pspaUoFRqEC8K7m59lGvVyp2/PHL3As97AjAd0M t+UVlosUgjHE3faMTtmkcjw6ZJJxFkiQCc5PihaXCDqfyjYKJsbhnvVWMq5ygQnfNxiw J5USph+TWlz37NqRfGJ6HKKp7D6ruP15HRq+THNaSZrlFLaZHGnEg6a+cJKIolfyAFD5 3TYmH1GlFQTVqoLT3yHjAHzrTA+AQ+90lwrIicY+ieusm3BhosYedz9Vj48BUhzLuZLk 9Znw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=h75nkbhTYtyJJTOXLQJCYo5pUIkcCdOrO0xFrVv9ewQ=; b=soNwJkjitBuowGcqH98lmR7Qal4/N1aNZEEp7HHOuqlGf3M2BxrK4I1+UBcpDlORVA sMePb+1UPFoNpfLPikVT5rd+dPNQ5E3i/INjVP5O8mkB/hP2qq8rWwLVubdbLY8mKEwj HcrtQ3w3xMaRnXuEgX65zNyWgeHdWsUc/RxMNvvB9d4DWEGcdGkneCv+FGyZ4FtPbBJg zoR5qktisC8geQ4qahU8RDwg0TORiXcECzr1T4zzTvDCjEe7ZnqV/U+pHqHQ1/58B1Lo rv+dCBXOEB7nlUe5x3MxC7dPeM1rji8u0GyXBlZs10aRKWy+9w4191jM3WCqx9dSKPD6 1/+A== X-Gm-Message-State: AOAM531U6RiLRkDzPhpQu0qIlq+HIgo+SWPFADZ+Wh+dwq5o2Wveae63 HqO5TvklXg5o1+EmsJbg79KLxw== X-Google-Smtp-Source: ABdhPJz3fAdc0YvI5AWtl9SauG6qJOT51TSRvpPUCLzKv2tGNV9ZWsPoHeW5QCGfBdfeOl99CDHcKw== X-Received: by 2002:a7b:c198:: with SMTP id y24mr3991256wmi.186.1589970502018; Wed, 20 May 2020 03:28:22 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id f123sm2575473wmf.44.2020.05.20.03.28.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 03:28:20 -0700 (PDT) Date: Wed, 20 May 2020 11:28:18 +0100 From: "Leif Lindholm" To: Ard Biesheuvel Cc: devel@edk2.groups.io, glin@suse.com, lersek@redhat.com, liming.gao@intel.com Subject: Re: [PATCH] ArmPkg/CompilerIntrinsicsLib: provide atomics intrinsics Message-ID: <20200520102818.GH1923@vanye> References: <20200520100503.22065-1-ard.biesheuvel@arm.com> MIME-Version: 1.0 In-Reply-To: <20200520100503.22065-1-ard.biesheuvel@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, May 20, 2020 at 12:05:03 +0200, Ard Biesheuvel wrote: > Gary reports that GCC 10 will emit calls to atomics intrinsics routines > unless -mno-outline-atomics is specified. This means GCC-10 introduces > new intrinsics, and even though it would be possible to work around this > by specifying the command line option, this would require a new GCC10 > toolchain profile to be created, which we prefer to avoid. > > So instead, add the new intrinsics to our library so they are provided > when necessary. > > Link: https://bugzilla.tianocore.org/show_bug.cgi?id=2723 > Signed-off-by: Ard Biesheuvel 1) Thanks! 2) My head hurts. Is there any chance we could merge the macro-expanded version? Of course, this isn't somewhere we expect churn, and this is probably real handy if we end up having to add more variants, but it feels a bit write-only at the moment. If we keep this form, could we sprinkle it with comments a bit? I can sort of see what it does, but I definitely can't follow it. / Leif > --- > ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf | 3 + > ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S | 91 ++++++++++++++++++++ > 2 files changed, 94 insertions(+) > > diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf > index d5bad9467758..fcf48c678119 100644 > --- a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf > +++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf > @@ -79,6 +79,9 @@ [Sources.ARM] > Arm/ldivmod.asm | MSFT > Arm/llsr.asm | MSFT > > +[Sources.AARCH64] > + AArch64/Atomics.S | GCC > + > [Packages] > MdePkg/MdePkg.dec > ArmPkg/ArmPkg.dec > diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S b/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S > new file mode 100644 > index 000000000000..5846131ab19e > --- /dev/null > +++ b/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S > @@ -0,0 +1,91 @@ > +#------------------------------------------------------------------------------ > +# > +# Copyright (c) 2020, Arm, Limited. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#------------------------------------------------------------------------------ > + > + .arch armv8-a > + > + .macro reg_alias, pfx, sz > + r0_\sz .req \pfx\()0 > + r1_\sz .req \pfx\()1 > + tmp0_\sz .req \pfx\()16 > + tmp1_\sz .req \pfx\()17 > + .endm > + > + .macro fn_start, name:req > + .section .text.\name > + .type \name, %function > +\name\(): > + .endm > + > + .macro emit_ld_sz, sz:req, insn:req, opc:req, model:req, s, a, l > + fn_start __aarch64_\insn\()\sz\()\model > + mov tmp0_\sz, r0_\sz > +0: ld\a\()xr\s r0_\sz, [x1] > + .ifnc \insn, swp > + \opc tmp1_\sz, r0_\sz, tmp0_\sz > + .else > + \opc tmp1_\sz, tmp0_\sz > + .endif > + st\l\()xr\s w15, tmp1_\sz, [x1] > + cbnz w15, 0b > + ret > + .endm > + > + .macro emit_ld, insn:req, opc:req, model:req, a, l > + emit_ld_sz 1, \insn, \opc, \model, b, \a, \l > + emit_ld_sz 2, \insn, \opc, \model, h, \a, \l > + emit_ld_sz 4, \insn, \opc, \model, , \a, \l > + emit_ld_sz 8, \insn, \opc, \model, , \a, \l > + .endm > + > + .macro emit_cas_sz, sz:req, model:req, uxt:req, s, a, l > + fn_start __aarch64_cas\sz\()\model > + \uxt tmp0_\sz, r0_\sz > +0: ld\a\()xr\s r0_\sz, [x2] > + cmp r0_\sz, tmp0_\sz > + bne 1f > + st\l\()xr\s w15, r1_\sz, [x2] > + cbnz w15, 0b > +1: ret > + .endm > + > + .macro emit_cas, model:req, a, l > + emit_cas_sz 1, \model, uxtb, b, \a, \l > + emit_cas_sz 2, \model, uxth, h, \a, \l > + emit_cas_sz 4, \model, mov , , \a, \l > + emit_cas_sz 8, \model, mov , , \a, \l > + > + fn_start __aarch64_cas16\model > + mov x16, x0 > + mov x17, x1 > +0: ld\a\()xp x0, x1, [x4] > + cmp x0, x16 > + ccmp x1, x17, #0, eq > + bne 1f > + st\l\()xp w15, x16, x17, [x4] > + cbnz w15, 0b > +1: ret > + .endm > + > + .macro emit_model, model:req, a, l > + emit_ld ldadd, add, \model, \a, \l > + emit_ld ldclr, bic, \model, \a, \l > + emit_ld ldeor, eor, \model, \a, \l > + emit_ld ldset, orr, \model, \a, \l > + emit_ld swp, mov, \model, \a, \l > + emit_cas \model, \a, \l > + .endm > + > + reg_alias w, 1 > + reg_alias w, 2 > + reg_alias w, 4 > + reg_alias x, 8 > + > + emit_model _relax > + emit_model _acq, a > + emit_model _rel,, l > + emit_model _acq_rel, a, l > -- > 2.17.1 >