From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by mx.groups.io with SMTP id smtpd.web10.10907.1589975021103919269 for ; Wed, 20 May 2020 04:43:41 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=z1gUv6Ln; spf=pass (domain: nuviainc.com, ip: 209.85.221.67, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f67.google.com with SMTP id k13so2828879wrx.3 for ; Wed, 20 May 2020 04:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=wHDEriIer8fNkc81p1lQGnSEmOke1uTJR89QhDdorNo=; b=z1gUv6LncGaXwTs4q7X6QVPjnY1rNKUX1VAFU9BZf1Zm95x3+Lq8vYAbAtY4kJQeqR Q1UIp3ISWL6d/uzn5sUsxEA2s4pQ8u/58vY6CFQ+Hy3IyHmXhw/g15xeVHmI4XhZV5tk sekwuZ86qlLsHNhIiXkcyQ+5nNrWZwkDexhHVcQoqPNocBEC6iOdOA5TyGUoGvqUdcce 45PA4fns+/gSWEAFZuzOsZOLeEYTzwKzOm+oQWoO8S3Uxf0RThTD1a6lpLpCqlB7PhgU UDaSpGauTYyjMEPZhRRhZBMxE8/1BzxL7/LDZSEqM/iokXkdb70W/wmEkU1P31MLEbet lOPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=wHDEriIer8fNkc81p1lQGnSEmOke1uTJR89QhDdorNo=; b=L2qBajW/v/IhszeTxuxBwuY51WXtI/Ra4HtlCLSVCxZUEXRRFceaYhO/f1wPxa2qkW vVCQweWpV2VgRbgbAh0Wf/M0KAXOaoEcUzaSMik+kaiW8onPI/fvhmqpXZPjUrwOJPvx MIDWgK7+tnknThqBSN7l8PIZ6PiSPuWLV6TfQz4HqnTCNuYOTH8Gb9msPSAiVr48hsu5 1AlZS+ZAH7m+hBcRkILjoMqJ4qyp3gGIi3otoKyLAw4G4oKpaiRkxBTQNntmZXf2GHl4 jVIqJCmVp7zZAVpqA/smqCtoX8zDbQjNLX2Fxrg0yFC4r43EFT0uOTmOXipsdARK5d6K RxAg== X-Gm-Message-State: AOAM530P9eGJIgIEmloXLIHUlAAJutHsAsvi6Kb/f4B0noh1ecizexZl MEWGH1yVzM1vqSEXiTh8A+Kk4o0zb24Re1pfl5TNCErPyxJEUpgb7LTslp7Yl8fLEGqrD+SVm+U ze98nWYQNxNAfi1hVnE2hQWjJbtjVHzlgovcKnY2HvNF0U2LwTQUIP2ePhCI8//EdeQ== X-Google-Smtp-Source: ABdhPJzJh96RxTZxPbBRaOop460k+ywKVXB7eKGTSSlEvfidhWYiB1kbDYSmz/NPJSTQ4b5oXEdDfg== X-Received: by 2002:adf:f601:: with SMTP id t1mr4037414wrp.207.1589975019406; Wed, 20 May 2020 04:43:39 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id v11sm2648358wrv.53.2020.05.20.04.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 04:43:38 -0700 (PDT) Date: Wed, 20 May 2020 12:43:36 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, daniel.schaefer@hpe.com Cc: Abner Chang , Gilbert Chen , Michael D Kinney Subject: Re: [edk2-devel] [PATCH v2 0/3] New RISC-V Patches Message-ID: <20200520114336.GK1923@vanye> References: <20200515133937.29909-1-daniel.schaefer@hpe.com> MIME-Version: 1.0 In-Reply-To: <20200515133937.29909-1-daniel.schaefer@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, May 15, 2020 at 15:39:34 +0200, Daniel Schaefer wrote: > In this updated version I addressed Leif's comments and made the following > changes: > > - Refactor sbi_call* to SbiCall* (EDKII style) > - Use OpenSBI constants if possible > - Include Base.h in OpensbiTypes.h > - Only use __builtin_expect with Clang and GCC (not MSVC) > > I'm sorry, I hadn't explained the new branches properly. > Previously we had all code going to EDK2 via the RISC-V-V2 branch. > > Now we're only making the least amount of necessary changes in edk2 and > everything else in edk2-platforms. > Those changes to edk2 can be grouped into different categories: > > - Patches for RISC-V EDK2 CI enablement > - Patches for edk2 modules other than RISC-V ones, to allow building them with the RISC-V toolchain > - Other RISC-V enablement like PE/COFF relocation > > Those have all been reviewed and merged to edk2 master. > > Previously we had two packages just for RISC-V on our edk2 branch: > RiscVPkg and RiscVPlatformPkg > They are now under > Platform/RISC-V/PlatformPkg and Silicon/RISC-V/ProcessorPkg > in edk2-platforms. Understood. I took my eye off the ball there for a while, but I'm a bit confused as to why RiscVPkg isn't going into EDK2. That is very counterintuitive. And clearly it will need revisiting if we are to add first-class CI checks like those we do with OvmfPkg/ArmVirtPkg. > You, Leif, have previously reviewed those. In addition to this old code, which > was moved, we need some more patches to allow running PEI in S-Mode and > building in edk2-platforms. That's what this patch series is about. I *did* have some outstanding comments specifically with regards to large amounts of code duplication between the SMBIOS implementation of some closely related RISC-V platforms. That now needs to be revisited. > In the previous version of this patchseries I forgot to attach the biggest new > commit, which adds RiscVEdk2SbiLib. It wraps the ecall interface for calling > SBI in a C API and lets PEI and DXE call SBI interfaces. Because we need more > M-Mode capabilities in PEI and DXE than SBI gives us, we register another SBI > extension, that gives us access to the mscratch register. Without looking at it yet, it sounds like that may resolve the only remaining major issue I had with RiscVPkg. > I hope now it makes more sense. It is more clear, as per above I am not sure it makes more sense :) Thanks! Best Regards, Leif > - Daniel > > Cc: Abner Chang > Cc: Gilbert Chen > Cc: Michael D Kinney > Cc: Leif Lindholm > > Abner Chang (1): > ProcessorPkg/Library: Add RiscVOpensbiLib > > Daniel Schaefer (2): > ProcessorPkg/RiscVOpensbLib: Add opensbi submodule > ProcessorPkg/Library: Add RiscVEdk2SbiLib > > Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf | 28 + > Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 60 ++ > Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h | 72 ++ > Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h | 631 ++++++++++++++++ > Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h | 73 ++ > Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 789 ++++++++++++++++++++ > .gitmodules | 3 + > Readme.md | 36 + > Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi | 1 + > 9 files changed, 1693 insertions(+) > create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf > create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf > create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h > create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h > create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h > create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c > create mode 100644 .gitmodules > create mode 160000 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi > > -- > 2.26.1 > > > >