From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.groups.io with SMTP id smtpd.web11.10645.1590145137907596907 for ; Fri, 22 May 2020 03:58:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=MRAEh/zV; spf=pass (domain: nuviainc.com, ip: 209.85.221.68, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f68.google.com with SMTP id y17so1337950wrn.11 for ; Fri, 22 May 2020 03:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=7jrShw7LsGkQyfrosX8IBELEQreZ6kNLpJX7MNL5PFg=; b=MRAEh/zVsLderNuSZHamCN9KQGICDGRKLoaz7rjMSshx50QIqkLsW/0jBn/gsTDd8D E2ap/9WfcLFUNeQOPHlYhRvWcedilRBFqw5TSOobN0hikEvwG/Ra+L03E4Cus2es3hF+ EshZ74XdMqZ3D7EjcENRJORwm6ul4GPo884Vt6yutPXSX/o7JzEKpw1Yd55FDfyfrv33 F6xiF/GE0gaBXrKi7SRAGxhcP7pd4qXZURu9vFSnAqXu4CENv+8S/pVAiyoAZecCjCEX 7kFEm3VnfTD8ywThMv9YFDJcrxkV1TFlrdKTvjoF0PGeyZ7lM234rooCovl//IVuaKFw qX+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=7jrShw7LsGkQyfrosX8IBELEQreZ6kNLpJX7MNL5PFg=; b=bzeFZyopro1i4hzL5eNTG9N13G0htG6j0OA+caIzZ09k+zhCDj/UNoIbCJZGOmIzV4 tiM4l2xwHUTQmqFLb5ZS7fUG7d1iMtuYfn2wZVx8CSVJsYQL+s86dGMvwTKWUErC29sF o9Q+i16vI13xCtcs4mOjz2xQFSV40vhbJPq46+/7Zz0YjkbbzcISLJxHbpwHnvw6JpHG sZxbXFN03lUp84Br6fCD8q/JuNp0Ilxa0SuieuthuwbXtcFiWX1uNz4WLiNSOJ/e/FBS KPDwGk0hIrO26ipF6aWULd89lWymijtXMQz+83XqWSPOrPnePtZkwVtLqlLg6d3U+VEC CZgQ== X-Gm-Message-State: AOAM532wG/7jRhZRulmX3RxoWxWjvSXXPWFp/xzfdPZAfwhqGfJIl2F2 u2sCyQS5w+RizWpBcDzukS5FPQ== X-Google-Smtp-Source: ABdhPJx4legjgrVeRIjnSiSEwkJoSSXi7j4T0FUljaNSjd2aZIwVha9OKEWonjHMN69PHeAZSdeZQA== X-Received: by 2002:a05:6000:12c2:: with SMTP id l2mr2821920wrx.133.1590145136511; Fri, 22 May 2020 03:58:56 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id d15sm201156wrq.30.2020.05.22.03.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2020 03:58:56 -0700 (PDT) Date: Fri, 22 May 2020 11:58:53 +0100 From: "Leif Lindholm" To: Ard Biesheuvel Cc: Wasim Khan , devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, vabhav.sharma@nxp.com, V.Sethi@nxp.com, jon@solid-run.com, Wasim Khan Subject: Re: [PATCH edk2-platforms 00/16] Add PCIe Support Message-ID: <20200522105853.GZ1923@vanye> References: <1590102139-16588-1-git-send-email-wasim.khan@oss.nxp.com> <8e8d0ede-17e6-bbb1-2b3a-ea420933c62b@arm.com> MIME-Version: 1.0 In-Reply-To: <8e8d0ede-17e6-bbb1-2b3a-ea420933c62b@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, May 22, 2020 at 11:46:07 +0200, Ard Biesheuvel wrote: > On 5/22/20 1:02 AM, Wasim Khan wrote: > > From: Wasim Khan > > > > Add PCIe Support for NXP Layerscape SoC which supports > > different PCIe controllers. > > Use generic PCIe drivers and wire up PciHostBridgeLib, > > PciSegmentLib and PciCpuIo2Dxe driver for controller > > specific implementation. > > > > Thanks. This is looking good. Please take a look at the feedback, and give > others some time to respond as well. > > In the meantime, I think we can simply merge #14 and #16 right away (unless > Leif has any objections) (Looking at those two out of order.) 16, sure. 14 - is there any reason to do so before there is PCI to connect network devices through? / Leif > > > Wasim Khan (16): > > Silicon/NXP/NxpQoriqLs.dec: Add PCIe related PCDs. > > Silicon/NXP: LS1043A: Define PCIe related PCDs > > Silicon/NXP: Implement PciHostBridgeLib support > > Silicon/NXP: PciHostBridgeLib: CFG Shift feature support for PCIeLS > > Ctrl > > Silicon/NXP: PciHostBridgeLib: Setup PCIe LsGen4 Controller and ATU > > Windows > > Silicon/NXP: PciHostBridgeLib: add Workaround for A-011451 > > Silicon/NXP: PciHostBridgeLib: Dump Layerscale Gen4 ATU windows > > Silicon/NXP: PciHostBridgeLib: Dump Layerscale iATU windows > > Silicon/NXP: Implement PciSegmentLib for PCIe Layerscape Controller > > Silicon/NXP: PciSegmentLib: Add ECAM config support for PCIe LS > > Controller > > Silicon/NXP: PciSegmentLib: Add support PCIe LsGen4 Controller > > Silicon/NXP: PciSegmentLib: LsGen4Ctrl: Add Workaround for A-011264 > > Silicon/NXP/Drivers: Implement PciCpuIo2Dxe Driver > > Platform/NXP: LS1043aRdbPkg: Enable NetworkPkg > > Platform/NXP: LS1043aRdbPkg: Enable PCIE support > > Platform/NXP: LS1043aRdbPkg : Increase fv image size > > > > Silicon/NXP/NxpQoriqLs.dec | 13 + > > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 8 + > > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 20 + > > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 20 +- > > Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 40 + > > .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 45 ++ > > .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 36 + > > Silicon/NXP/Include/Pcie.h | 231 ++++++ > > Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 628 +++++++++++++++ > > .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 842 +++++++++++++++++++++ > > Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 699 +++++++++++++++++ > > 11 files changed, 2579 insertions(+), 3 deletions(-) > > create mode 100755 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf > > create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > > create mode 100755 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf > > create mode 100755 Silicon/NXP/Include/Pcie.h > > create mode 100755 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c > > create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > > create mode 100755 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c > > >