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From: "Leif Lindholm" <leif@nuviainc.com>
To: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Cc: ard.biesheuvel@arm.com, graeme.gregory@linaro.org,
	devel@edk2.groups.io,
	Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Subject: Re: [PATCH V4] SbsaQemu: EFI implementation for SbsaQemu platform
Date: Sat, 23 May 2020 23:18:57 +0100	[thread overview]
Message-ID: <20200523221857.GH1923@vanye> (raw)
In-Reply-To: <20200522130037.91575-1-tanmay.jagdale@linaro.org>

On Fri, May 22, 2020 at 18:30:37 +0530, Tanmay Jagdale wrote:
> From: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
> 
> Linaro LDCG group is coordinating work for adding SBSA compliant
> virtual platform for QEMU. This patch adds initial support for this
> platform with nondiscoverable AHCI, VGA and single DRAM window over
> 32bit address space.
> 
> We are using FDF to compose EFI flash images with TF-A images.
> Flash0 (secure) is used by BL1 and FIP (BL2 + BL31).
> Flash1 contains EFI code and EFI variables.
> 
> Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> This patch adds initial support for Sbsa QEMU model. There will be
> following patches which will add support for ACPI tables.

With the tweaks as acked by Graeme in
https://edk2.groups.io/g/devel/message/60183
:
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Pushed as 7a4035e9efd8.
Thanks!

> Changes in V4:
>  - Fixed the serial console output issue
>  - Added support to read memory from FDT passed by QEMU
> 
> Changes in V3:
>  - Made more changes in the Readme.md file
>  - Updated the fip.bin and bl1.bin image location the FDF file
> 
> Changes in V2:
>  - Fixed capitalization in the Readme.md file
> 
>  Maintainers.txt                               |  14 +
>  Platform/Qemu/SbsaQemu/Readme.md              | 132 ++++
>  Platform/Qemu/SbsaQemu/SbsaQemu.dsc           | 677 ++++++++++++++++++
>  Platform/Qemu/SbsaQemu/SbsaQemu.fdf           | 303 ++++++++
>  Readme.md                                     |   3 +
>  .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c |  55 ++
>  .../SbsaQemuPlatformDxe.inf                   |  41 ++
>  .../Qemu/Library/SbsaQemuLib/SbsaQemuHelper.S |  55 ++
>  .../Qemu/Library/SbsaQemuLib/SbsaQemuLib.c    | 139 ++++
>  .../Qemu/Library/SbsaQemuLib/SbsaQemuLib.inf  |  51 ++
>  .../Qemu/Library/SbsaQemuLib/SbsaQemuMem.c    | 145 ++++
>  .../SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c |  40 ++
>  .../SbsaQemuNorFlashLib.inf                   |  29 +
>  .../SbsaQemuPciHostBridgeLib.c                | 215 ++++++
>  .../SbsaQemuPciHostBridgeLib.inf              |  47 ++
>  Silicon/Qemu/SbsaQemuPkg.dec                  |  40 ++
>  16 files changed, 1986 insertions(+)
>  create mode 100644 Platform/Qemu/SbsaQemu/Readme.md
>  create mode 100644 Platform/Qemu/SbsaQemu/SbsaQemu.dsc
>  create mode 100644 Platform/Qemu/SbsaQemu/SbsaQemu.fdf
>  create mode 100644 Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
>  create mode 100644 Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
>  create mode 100644 Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuHelper.S
>  create mode 100644 Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.c
>  create mode 100644 Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.inf
>  create mode 100644 Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuMem.c
>  create mode 100644 Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c
>  create mode 100644 Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf
>  create mode 100644 Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
>  create mode 100644 Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf
>  create mode 100644 Silicon/Qemu/SbsaQemuPkg.dec
> 
> diff --git a/Maintainers.txt b/Maintainers.txt
> index b08ce31066..f9e2ca54f4 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -264,3 +264,17 @@ F: Silicon/NXP/Library/Pcf8563RealTimeClockLib/
>  F: Silicon/Socionext/
>  M: Ard Biesheuvel <ard.biesheuvel@arm.com>
>  M: Leif Lindholm <leif@nuviainc.com>
> +
> +Silicon/Qemu
> +M: Ard Biesheuvel <ard.biesheuvel@arm.com>
> +M: Leif Lindholm <leif@nuviainc.com>
> +M: Graeme Gregory <graeme.gregory@linaro.org>
> +R: Radoslaw Biernacki <rad@semihalf.com>
> +R: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> +
> +Platform/Qemu/SbsaQemu
> +M: Ard Biesheuvel <ard.biesheuvel@arm.com>
> +M: Leif Lindholm <leif@nuviainc.com>
> +M: Graeme Gregory <graeme.gregory@linaro.org>
> +R: Radoslaw Biernacki <rad@semihalf.com>
> +R: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> diff --git a/Platform/Qemu/SbsaQemu/Readme.md b/Platform/Qemu/SbsaQemu/Readme.md
> new file mode 100644
> index 0000000000..c7b59f3972
> --- /dev/null
> +++ b/Platform/Qemu/SbsaQemu/Readme.md
> @@ -0,0 +1,132 @@
> +# Overview
> +
> +This directory holds the UEFI implementation for Sbsa-ref machine which is
> +a fully SW emulated SBSA machine (ARM64). It aims to emulate the real HW as
> +close as possible. It's purpose is to enable new feature development when
> +HW for those features are not yet present on the market. It allows poking
> +the HW to do all kinds of things (including errors) which are beyond control
> +on real HW. It also allows easy simulations and debugging of FW-to-HW
> +interactions.
> +
> +Keep in mind that all of the above is possible as this machine is fully
> +emulated in SW. Sbsa-ref machine does not use any HW acceleration of your
> +platform, even if you run it on ARM64 platform. The EL3 (and ARM TrustZone)
> +is also emulated in SW.
> +
> +# How to build (Linux Environment)
> +
> +## Prerequisites
> +
> +Build process for Sbsa-ref uses FDF file for flash image composition. This is
> +different to what some might expect as you need to first build the TF-A before
> +building EDK2.
> +Flash0 (secure) is used by BL1 and FIP (BL2 + BL31).
> +Flash1 contains EFI code and EFI variables.
> +
> +## Obtaining source code
> +
> +Create a directory $WORKSPACE that would hold source code of the components.
> +
> +  1. [qemu](https://github.com/qemu/qemu.git)
> +  2. [edk2](https://github.com/tianocore/edk2)
> +  3. [edk2-platforms](https://github.com/tianocore/edk2-platforms)
> +  4. [edk2-non-osi](https://github.com/tianocore/edk2-non-osi)
> +  5. [tf-a](https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git)
> +
> +## Manual building
> +
> +1. Compile QEMU
> +
> +  Sbsa-ref machine support was added to QEMU in version v4.1.0
> +  If your distribution package provides an earlier version then you need to
> +  compile QEMU from the source. Below is a short set of instructions on how
> +  to compile without referring to QEMU docs.
> +
> +  Set $INSTALL_PATH to /usr/local, ~/local or any of your preferred location.
> +
> +  ```
> +  cd $WORKSPACE/qemu
> +  mkdir -p build-native
> +  cd build-native
> +  ../configure --target-list=aarch64-softmmu --prefix=$INSTALL_PATH
> +  make install
> +  ```
> +
> +  QEMU should be installed now in $INSTALL_PATH
> +
> +2. Compile TF-A
> +
> +  This step is only needed if users want to compile a custom ATF binary.
> +  Else, the edk2-non-osi directory contains prebuilt bl1.bin and fip.bin
> +  binaries which will be automatically used in the build process.
> +
> +  As noted before, for Sbsa-ref machine we use FDF to compose two flash images.
> +  Those flash images need BL1, BL2 and BL31 from TF-A in form of two files
> +  `bl1.bin` and `fip.bin`. Follow the instructions below to get those artifacts.
> +
> +  ```
> +  cd $WORKSPACE/atf
> +  make PLAT=sbsa all fip
> +  ```
> +  Then copy `bl1.bin` and `fip.bin` to the the edk2-non-osi directory:
> +
> +  ```
> +  cp build/sbsa/release/bl1.bin $WORKSPACE/edk2-non-osi/Platform/Qemu/Sbsa/
> +  cp build/sbsa/release/fip.bin $WORKSPACE/edk2-non-osi/Platform/Qemu/Sbsa/
> +  ```
> +
> +3. Compile UEFI for QEMU Sbsa platform
> +
> +  Detailed build instructions can be found on the following link:
> +  https://github.com/tianocore/edk2-platforms
> +
> +  Following is a short description to build for the Sbsa platform.
> +
> +  Compilation of BaseTools and preparation:
> +
> +  ```
> +  cd $WORKSPACE
> +  export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms:$WORKSPACE/edk2-non-osi
> +  make -C edk2/BaseTools
> +  . edk2/edksetup.sh
> +  ```
> +
> +  Now compile UEFI for Sbsa QEMU:
> +
> +  ```
> +  cd $WORKSPACE
> +  build -b RELEASE -a AARCH64 -t GCC5 -p edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> +  ```
> +  Copy SBSA_FLASH0.fd and SBSA_FLASH0.fd to top $WORKSPACE directory.
> +  Then extend the file size to match the machine flash size.
> +  ```
> +  cp Build/SbsaQemu/RELEASE_GCC5/FV/SBSA_FLASH[01].fd .
> +  truncate -s 256M SBSA_FLASH[01].fd
> +  ```
> +
> +# Running
> +
> +  The resulting SBSA_FLASH0.fd file will contain Secure flash0 image (TF-A code).
> +  The SBSA_FLASH1.fd will contain Non-secure UEFI code and UEFI variables.
> +
> +  You will boot to the UEFI console with following QEMU command line:
> +  ```
> +  $INSTALL_PATH/qemu-system-aarch64 -m 1024 -M sbsa-ref -pflash SBSA_FLASH0.fd -pflash SBSA_FLASH1.fd -serial stdio
> +  ```
> +  You can add XHCI controller with keyboard and mouse by:
> +  ```
> +  -device qemu-xhci -device usb-mouse -device usb-kbd
> +  ```
> +  You can add the hard drive to platform AHCI controller by `hda` parameter:
> +  ```
> +  -hda disk1.img
> +  ```
> +  For TEE and other secure development you might get use of secure serial which would require following commands. First create `secure_serial` fifo and read it from separate terminal (open new terminal emulator window for it):
> +  ```
> +  mkfifo secure_serial
> +  tail -f secure_serial
> +  ```
> +  Then on first console:
> +  ```
> +  qemu-system-aarch64 -m 1024 -M sbsa-ref -pflash SBSA_FLASH0.fd -pflash SBSA_FLASH1.fd -serial stdio -hda disk1.img -serial file:secure_serial
> +  ```
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> new file mode 100644
> index 0000000000..379b8ece77
> --- /dev/null
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> @@ -0,0 +1,677 @@
> +#
> +#  Copyright (c) 2019, Linaro Limited. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> +  PLATFORM_NAME                  = SbsaQemu
> +  PLATFORM_GUID                  = feb0325c-b93d-4e47-8844-b832adeb9e0c
> +  PLATFORM_VERSION               = 0.1
> +  DSC_SPECIFICATION              = 0x00010005
> +  OUTPUT_DIRECTORY               = Build/SbsaQemu
> +  SUPPORTED_ARCHITECTURES        = AARCH64
> +  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
> +  SKUID_IDENTIFIER               = DEFAULT
> +  FLASH_DEFINITION               = Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> +
> +  #
> +  # Defines for default states.  These can be changed on the command line.
> +  # -D FLAG=VALUE
> +  #
> +
> +  DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F
> +
> +#
> +# Network definition
> +#
> +DEFINE NETWORK_SNP_ENABLE             = FALSE
> +DEFINE NETWORK_IP6_ENABLE             = FALSE
> +DEFINE NETWORK_TLS_ENABLE             = FALSE
> +DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
> +
> +################################################################################
> +#
> +# Library Class section - list of all Library Classes needed by this Platform.
> +#
> +################################################################################
> +[LibraryClasses.common]
> +!if $(TARGET) == RELEASE
> +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +!else
> +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> +!endif
> +  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> +
> +  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> +  SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
> +  BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf
> +  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> +  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> +  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> +  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> +  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> +  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
> +  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> +  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> +
> +  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> +  HobLib|ArmVirtPkg/Library/ArmVirtDxeHobLib/ArmVirtDxeHobLib.inf
> +  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> +  DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
> +  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> +  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> +  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> +  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> +  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> +  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> +  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> +  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> +
> +  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> +  OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
> +
> +  #
> +  # Ramdisk Requirements
> +  #
> +  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> +
> +  # Allow dynamic PCDs
> +  #
> +  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> +  # use the accelerated BaseMemoryLibOptDxe by default, overrides for SEC/PEI below
> +  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
> +
> +  #
> +  # It is not possible to prevent the ARM compiler from inserting calls to intrinsic functions.
> +  # This library provides the instrinsic functions such a compiler may generate calls to.
> +  #
> +  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +
> +  # Add support for GCC stack protector
> +  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> +
> +  # ARM Architectural Libraries
> +  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
> +  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
> +  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
> +  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
> +  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> +  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
> +  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> +  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
> +  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf
> +
> +  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> +  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
> +  ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> +
> +  # ARM PL031 RTC Driver
> +  RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
> +  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
> +  # ARM PL011 UART Driver
> +  PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
> +
> +  # Debug Support
> +  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
> +  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> +  DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
> +
> +  # PCI Libraries
> +  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
> +  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> +  PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf
> +  PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.inf
> +  PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf
> +
> +  # USB Libraries
> +  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +
> +  #
> +  # CryptoPkg libraries needed by multiple firmware features
> +  #
> +  IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> +  OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> +  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> +
> +  #
> +  # Secure Boot dependencies
> +  #
> +  TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
> +  AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
> +
> +  # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree
> +  PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
> +
> +  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> +  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> +
> +  ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
> +
> +  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> +  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> +
> +  ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
> +
> +  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> +  NorFlashPlatformLib|Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf
> +
> +  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> +  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> +  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> +  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
> +  PciHostBridgeLib|Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf
> +
> +  FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
> +
> +  # Serial driver
> +  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
> +  PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf
> +
> +[LibraryClasses.common.SEC]
> +  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +
> +  DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
> +  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> +  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> +  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> +  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> +
> +[LibraryClasses.common.PEI_CORE]
> +  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> +  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> +  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> +  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> +  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> +  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
> +  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> +  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> +
> +  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> +
> +[LibraryClasses.common.PEIM]
> +  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> +  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> +  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> +  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> +  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> +  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
> +  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> +  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
> +  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> +
> +  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> +
> +  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> +  ArmPlatformLib|Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.inf
> +
> +[LibraryClasses.common.DXE_CORE]
> +  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> +  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> +  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> +  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> +  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
> +
> +[LibraryClasses.common.DXE_DRIVER]
> +  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> +  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> +
> +  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
> +
> +[LibraryClasses.common.UEFI_APPLICATION]
> +  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> +  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +
> +[LibraryClasses.common.UEFI_DRIVER]
> +  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> +  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> +
> +  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
> +
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> +  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +!if $(TARGET) != RELEASE
> +  DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
> +!endif
> +
> +  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> +
> +###################################################################################################
> +# BuildOptions Section - Define the module specific tool chain flags that should be used as
> +#                        the default flags for a module. These flags are appended to any
> +#                        standard flags that are defined by the build process.
> +###################################################################################################
> +
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> +  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
> +
> +[BuildOptions]
> +  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag.common]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
> +
> +  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
> +  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
> +
> +  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
> +
> +  gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE
> +  gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|TRUE
> +
> +  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
> +  #  It could be set FALSE to save size.
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
> +
> +[PcdsFixedAtBuild.common]
> +  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> +  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
> +  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> +  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> +  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> +  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> +
> +  # DEBUG_ASSERT_ENABLED       0x01
> +  # DEBUG_PRINT_ENABLED        0x02
> +  # DEBUG_CODE_ENABLED         0x04
> +  # CLEAR_MEMORY_ENABLED       0x08
> +  # ASSERT_BREAKPOINT_ENABLED  0x10
> +  # ASSERT_DEADLOOP_ENABLED    0x20
> +!if $(TARGET) == RELEASE
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
> +!else
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
> +!endif
> +
> +  #  DEBUG_INIT      0x00000001  // Initialization
> +  #  DEBUG_WARN      0x00000002  // Warnings
> +  #  DEBUG_LOAD      0x00000004  // Load events
> +  #  DEBUG_FS        0x00000008  // EFI File system
> +  #  DEBUG_POOL      0x00000010  // Alloc & Free (pool)
> +  #  DEBUG_PAGE      0x00000020  // Alloc & Free (page)
> +  #  DEBUG_INFO      0x00000040  // Informational debug messages
> +  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE/SMM Dispatchers
> +  #  DEBUG_VARIABLE  0x00000100  // Variable
> +  #  DEBUG_BM        0x00000400  // Boot Manager
> +  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
> +  #  DEBUG_NET       0x00004000  // SNP Driver
> +  #  DEBUG_UNDI      0x00010000  // UNDI Driver
> +  #  DEBUG_LOADFILE  0x00020000  // LoadFile
> +  #  DEBUG_EVENT     0x00080000  // Event messages
> +  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
> +  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
> +  #  DEBUG_VERBOSE   0x00400000  // Detailed debug messages that may
> +  #                              // significantly impact boot performance
> +  #  DEBUG_ERROR     0x80000000  // Error
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL)
> +
> +  #
> +  # Optional feature to help prevent EFI memory map fragments
> +  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> +  # Values are in EFI Pages (4K). DXE Core will make sure that
> +  # at least this much of each type of memory can be allocated
> +  # from a single memory range. This way you only end up with
> +  # maximum of two fragements for each type in the memory map
> +  # (the memory used, and the free memory that was prereserved
> +  # but not used).
> +  #
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
> +
> +  # Override the default values from SecurityPkg to ensure images
> +  # from all sources are verified in secure boot
> +  gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
> +  gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
> +  gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
> +
> +  #
> +  # Enable strict image permissions for all images. (This applies
> +  # only to images that were built with >= 4 KB section alignment.)
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3
> +
> +  #
> +  # Enable NX memory protection for all non-code regions, including OEM and OS
> +  # reserved ones, with the exception of LoaderData regions, of which OS loaders
> +  # (i.e., GRUB) may assume that its contents are executable.
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1
> +
> +  #
> +  # Enable the non-executable DXE stack. (This gets set up by DxeIpl)
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
> +
> +  gArmPlatformTokenSpaceGuid.PcdCoreCount|1
> +  gArmTokenSpaceGuid.PcdVFPEnabled|1
> +
> +  # System Memory Base -- fixed
> +  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10000000000
> +
> +  # Space for 32 stacks
> +  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x1000007c000
> +  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
> +
> +  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
> +  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
> +
> +  #
> +  # ARM General Interrupt Controller
> +  #
> +  gArmTokenSpaceGuid.PcdGicDistributorBase|0x40060000
> +  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x40080000
> +
> +  ## Default Terminal Type
> +  ## 0-PCANSI, 1-VT100, 2-VT00+, 3-UTF8, 4-TTYTERM
> +  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> +
> +  #
> +  # ARM Virtual Architectural Timer -- fetch frequency from QEMU (TCG) or KVM
> +  #
> +  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
> +
> +  gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> +
> +  #
> +  # The maximum physical I/O addressability of the processor, set with
> +  # BuildCpuHob().
> +  #
> +  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
> +
> +  # Initial Device Tree Location
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000
> +
> +  # Non discoverable devices (AHCI,EHCI)
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase|0x60100000
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize|0x00010000
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0x60110000
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x00010000
> +
> +  # PL011 - Serial Terminal
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x60000000
> +
> +  # Timer IRQs
> +  # PPI #13
> +  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29
> +  # PPI #14
> +  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30
> +  # PPI #11
> +  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27
> +  # PPI #10
> +  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26
> +
> +  ## PL031 RealTimeClock
> +  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x60010000
> +
> +  # Clearing BIT0 in this PCD prevents installing a 32-bit SMBIOS entry point,
> +  # if the entry point version is >= 3.0. AARCH64 OSes cannot assume the
> +  # presence of the 32-bit entry point anyway (because many AARCH64 systems
> +  # don't have 32-bit addressable physical RAM), and the additional allocations
> +  # below 4 GB needlessly fragment the memory map. So expose the 64-bit entry
> +  # point only, for entry point versions >= 3.0.
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
> +
> +  #
> +  # PLDA PCI Root Complex
> +  #
> +  # ECAM size == 0x10000000
> +  gArmTokenSpaceGuid.PcdPciBusMin|0
> +  gArmTokenSpaceGuid.PcdPciBusMax|255
> +  gArmTokenSpaceGuid.PcdPciIoBase|0x0
> +  gArmTokenSpaceGuid.PcdPciIoSize|0x00010000
> +  gArmTokenSpaceGuid.PcdPciMmio32Base|0x80000000
> +  gArmTokenSpaceGuid.PcdPciMmio32Size|0x70000000
> +  gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
> +  gArmTokenSpaceGuid.PcdPciMmio64Size|0xFF00000000
> +
> +  # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this
> +  # PCD and PcdPciDisableBusEnumeration have not been assigned yet
> +  # TODO: PcdPciExpressBaseAddress set to max_uint64
> +  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xf0000000
> +  gArmTokenSpaceGuid.PcdPciIoTranslation|0x7fff0000
> +  gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
> +  gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
> +  ## If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI
> +  #  enumeration to complete before installing ACPI tables.
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
> +
> +[PcdsDynamicDefault.common]
> +  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
> +
> +
> +  # System Memory Size -- 128 MB initially, actual size will be fetched from DT
> +  # TODO as no DT will be used we should pass this by some other method
> +  gArmTokenSpaceGuid.PcdSystemMemorySize|0x08000000
> +
> +  #
> +  # Set video resolution for boot options
> +  # PlatformDxe can set the former at runtime.
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> +  # Set video resolution for text setup.
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
> +
> +  #
> +  # SMBIOS entry point version
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +
> +[Components.common]
> +  #
> +  # Ramdisk support
> +  #
> +  MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
> +
> +  #
> +  # UEFI application (Shell Embedded Boot Loader)
> +  #
> +  ShellPkg/Application/Shell/Shell.inf {
> +    <LibraryClasses>
> +      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> +      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> +      NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
> +!endif
> +      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> +      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> +      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> +      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> +
> +    <PcdsFixedAtBuild>
> +      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
> +      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
> +  }
> +
> +  #
> +  # PEI Phase modules
> +  #
> +  ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> +  MdeModulePkg/Core/Pei/PeiMain.inf
> +  MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> +    <LibraryClasses>
> +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  }
> +  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> +  ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> +  ArmPkg/Drivers/CpuPei/CpuPei.inf
> +
> +
> +  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> +    <LibraryClasses>
> +      NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> +  }
> +
> +  #
> +  # DXE
> +  #
> +  MdeModulePkg/Core/Dxe/DxeMain.inf {
> +    <LibraryClasses>
> +      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
> +      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> +  }
> +  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> +    <LibraryClasses>
> +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  }
> +
> +  #
> +  # Architectural Protocols
> +  #
> +  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> +    <LibraryClasses>
> +      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> +      # don't use unaligned CopyMem () on the UEFI varstore NOR flash region
> +      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +  }
> +  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
> +    <LibraryClasses>
> +      NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
> +  }
> +  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
> +  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> +  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> +  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> +
> +  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> +  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> +  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> +  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> +  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> +  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> +  ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
> +  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> +
> +  #
> +  # FAT filesystem + GPT/MBR partitioning
> +  #
> +  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> +  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +  FatPkg/EnhancedFatDxe/Fat.inf
> +  MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
> +
> +  #
> +  # Bds
> +  #
> +  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {
> +    <LibraryClasses>
> +      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  }
> +  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> +  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> +  MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
> +  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  MdeModulePkg/Logo/LogoDxe.inf
> +  MdeModulePkg/Application/UiApp/UiApp.inf {
> +    <LibraryClasses>
> +      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> +      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> +      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> +  }
> +
> +  #
> +  # Networking stack
> +  #
> +!include NetworkPkg/Network.dsc.inc
> +
> +  # NonDiscoverableDevices
> +  Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
> +  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
> +
> +  # IDE/AHCI Support
> +  OvmfPkg/SataControllerDxe/SataControllerDxe.inf
> +  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +
> +  #
> +  # SCSI Bus and Disk Driver
> +  #
> +  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> +  #
> +  # PCI support
> +  #
> +  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
> +  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> +  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> +  #
> +  # Video support (VGA)
> +  #
> +  OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
> +
> +  #
> +  # USB Support
> +  #
> +  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> +  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> +  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> new file mode 100644
> index 0000000000..2d8a30bded
> --- /dev/null
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> @@ -0,0 +1,303 @@
> +#
> +#  Copyright (c) 2019, Linaro Limited. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# FD Section for FLASH0
> +#
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into  the Flash Device Image.  Each FD section
> +# defines one flash "device" image.  A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash"  image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.SBSA_FLASH0]
> +BaseAddress   = 0x00000000
> +Size          = 0x00200000
> +ErasePolarity = 1
> +BlockSize     = 0x00001000
> +NumBlocks     = 0x200
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +## Place for Trusted Firmware
> +# flash0 is secure so we put here the BL1
> +0x00000000|0x00008000
> +FILE = Platform/Qemu/Sbsa/bl1.bin
> +
> +# and FIP (BL2 + BL31)
> +0x00008000|0x00020000
> +FILE = Platform/Qemu/Sbsa/fip.bin
> +
> +################################################################################
> +#
> +# FD Section for FLASH1
> +#
> +################################################################################
> +
> +[FD.SBSA_FLASH1]
> +BaseAddress   = 0x10000000|gArmTokenSpaceGuid.PcdFdBaseAddress
> +Size          = 0x002C0000|gArmTokenSpaceGuid.PcdFdSize
> +ErasePolarity = 1
> +BlockSize     = 0x00001000
> +NumBlocks     = 0x2C0
> +
> +## Place for EFI (BL33)
> +# This offset (if any as it is 0x0 currently) + BaseAddress (0x10000000) must be set in PRELOADED_BL33_BASE at ATF
> +0x00000000|0x00200000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +## Place for Variables. They share flash1 with EFI
> +# Must be aligned to Flash Block size 0x40000
> +0x00200000|0x00040000
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> +  ## This is the EFI_FIRMWARE_VOLUME_HEADER
> +  # ZeroVector []
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
> +  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
> +  #     { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> +  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> +  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> +  # FvLength: 0xC0000
> +  0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  # Signature "_FVH"       # Attributes
> +  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
> +  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> +  0x48, 0x00, 0x28, 0x09, 0x00, 0x00, 0x00, 0x02,
> +  # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
> +  0x3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00,
> +  # Blockmap[1]: End
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  ## This is the VARIABLE_STORE_HEADER
> +  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
> +  # Signature: gEfiAuthenticatedVariableGuid =
> +  #   { 0xaaf32c78, 0x947b, 0x439a,
> +  #     { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> +  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> +  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> +  # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> +  #         0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
> +  # This can speed up the Variable Dispatch a bit.
> +  0xB8, 0xFF, 0x03, 0x00,
> +  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> +  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +0x00240000|0x00040000
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> +  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid         =
> +  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> +  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> +  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
> +  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> +  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
> +  # WriteQueueSize: UINT64
> +  0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +0x00280000|0x00040000
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> +
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file.  This section also defines order the components and modules are positioned
> +# within the image.  The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid         = 706c8e7f-306e-4dbc-a4ca-c8615d0d1b96
> +BlockSize          = 0x40
> +NumBlocks          = 0         # This FV gets compressed so make it just big enough
> +FvAlignment        = 16        # FV alignment and FV attributes setting.
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +  INF MdeModulePkg/Core/Dxe/DxeMain.inf
> +  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> +  #
> +  # PI DXE Drivers producing Architectural Protocols (EFI Services)
> +  #
> +  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> +  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> +  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> +  INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
> +  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> +  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> +  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> +  #
> +  # Multiple Console IO support
> +  #
> +  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> +  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> +  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> +  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> +  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> +  INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
> +  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> +
> +  #
> +  # FAT filesystem + GPT/MBR partitioning + UDF filesystem
> +  #
> +  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> +  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +  INF FatPkg/EnhancedFatDxe/Fat.inf
> +  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +  INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
> +
> +  #
> +  # UEFI application (Shell Embedded Boot Loader)
> +  #
> +  INF ShellPkg/Application/Shell/Shell.inf
> +
> +  #
> +  # Bds
> +  #
> +  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> +  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> +  INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
> +  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +  #
> +  # Networking stack
> +  #
> +!include NetworkPkg/Network.fdf.inc
> +
> +  #
> +  # SCSI Bus and Disk Driver
> +  #
> +  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> +  #
> +  # PCI support
> +  #
> +  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
> +  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> +  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> +  #
> +  # USB Support
> +  #
> +  INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> +  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> +  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> +  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> +  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> +  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> +  #
> +  # TianoCore logo (splash screen)
> +  #
> +  INF MdeModulePkg/Logo/LogoDxe.inf
> +
> +  #
> +  # Ramdisk support
> +  #
> +  INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> +  INF MdeModulePkg/Core/Pei/PeiMain.inf
> +  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> +  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> +  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
> +  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> +  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +
> +  # IDE/AHCI Support
> +  INF OvmfPkg/SataControllerDxe/SataControllerDxe.inf
> +  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> +  # NonDiscoverableDevices
> +  INF Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
> +  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
> +
> +  #VGA
> +  INF OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
> +
> +  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> +    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> +      SECTION FV_IMAGE = FVMAIN
> +    }
> +  }
> +
> +!include ArmVirtPkg/ArmVirtRules.fdf.inc
> diff --git a/Readme.md b/Readme.md
> index 8f9522659d..ea9492240a 100644
> --- a/Readme.md
> +++ b/Readme.md
> @@ -257,6 +257,9 @@ For more information, see the
>  ## NXP
>  * [LS1043aRdb](Platform/NXP/LS1043aRdbPkg)
>  
> +## Qemu
> +* [SBSA](Platform/Qemu/SbsaQemu)
> +
>  # Maintainers
>  
>  See [Maintainers.txt](Maintainers.txt).
> diff --git a/Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c b/Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
> new file mode 100644
> index 0000000000..c707dbcdad
> --- /dev/null
> +++ b/Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
> @@ -0,0 +1,55 @@
> +/** @file
> +*  FDT client protocol driver for qemu,mach-virt-ahci DT node
> +*
> +*  Copyright (c) 2019, Linaro Ltd. All rights reserved.
> +*
> +*  SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/NonDiscoverableDeviceRegistrationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +
> +#include <Protocol/FdtClient.h>
> +
> +EFI_STATUS
> +EFIAPI
> +InitializeSbsaQemuPlatformDxe (
> +  IN EFI_HANDLE           ImageHandle,
> +  IN EFI_SYSTEM_TABLE     *SystemTable
> +  )
> +{
> +  EFI_STATUS                     Status;
> +  UINTN                          Size;
> +  VOID*                          Base;
> +
> +  DEBUG ((DEBUG_INFO, "%a: InitializeSbsaQemuPlatformDxe called\n", __FUNCTION__));
> +
> +  Base = (VOID*)(UINTN)PcdGet64 (PcdPlatformAhciBase);
> +  ASSERT (Base != NULL);
> +  Size = (UINTN)PcdGet32 (PcdPlatformAhciSize);
> +  ASSERT (Size != 0);
> +
> +  DEBUG ((DEBUG_INFO, "%a: Got platform AHCI %llx %u\n",
> +          __FUNCTION__, Base, Size));
> +
> +  Status = RegisterNonDiscoverableMmioDevice (
> +                   NonDiscoverableDeviceTypeAhci,
> +                   NonDiscoverableDeviceDmaTypeCoherent,
> +                   NULL,
> +                   NULL,
> +                   1,
> +                   Base, Size);
> +
> +  if (EFI_ERROR(Status)) {
> +    DEBUG ((DEBUG_ERROR, "%a: NonDiscoverable: Cannot install AHCI device @%p (Staus == %r)\n",
> +            __FUNCTION__, Base, Status));
> +    return Status;
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf b/Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
> new file mode 100644
> index 0000000000..12503ab8b4
> --- /dev/null
> +++ b/Silicon/Qemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
> @@ -0,0 +1,41 @@
> +## @file
> +#  This driver effectuates SbsaQemu platform configuration settings
> +#
> +#  Copyright (c) 2019, Linaro Ltd. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001c
> +  BASE_NAME                      = SbsaQemuPlatformDxe
> +  FILE_GUID                      = 6c592dc9-76c8-474f-93b2-bf1e8f15ae34
> +  MODULE_TYPE                    = DXE_DRIVER
> +  VERSION_STRING                 = 1.0
> +
> +  ENTRY_POINT                    = InitializeSbsaQemuPlatformDxe
> +
> +[Sources]
> +  SbsaQemuPlatformDxe.c
> +
> +[Packages]
> +  ArmVirtPkg/ArmVirtPkg.dec
> +  EmbeddedPkg/EmbeddedPkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +  Silicon/Qemu/SbsaQemuPkg.dec
> +
> +[LibraryClasses]
> +  PcdLib
> +  DebugLib
> +  NonDiscoverableDeviceRegistrationLib
> +  UefiDriverEntryPoint
> +
> +[Pcd]
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize
> +
> +[Depex]
> +  TRUE
> +
> diff --git a/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuHelper.S b/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuHelper.S
> new file mode 100644
> index 0000000000..1087556aa5
> --- /dev/null
> +++ b/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuHelper.S
> @@ -0,0 +1,55 @@
> +#
> +#  Copyright (c) 2019, Linaro Limited. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> +  ret
> +
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +//  IN UINTN MpId
> +//  );
> +// With this function: CorePos = (ClusterId * 4) + CoreId
> +ASM_FUNC(ArmPlatformGetCorePosition)
> +  and   x1, x0, #ARM_CORE_MASK
> +  and   x0, x0, #ARM_CLUSTER_MASK
> +  add   x0, x1, x0, LSR #6
> +  ret
> +
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +//  VOID
> +//  );
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> +  MOV32  (w0, FixedPcdGet32 (PcdArmPrimaryCore))
> +  ret
> +
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +//  IN UINTN MpId
> +//  );
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> +  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
> +  and   x0, x0, x1
> +  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCore))
> +  cmp   w0, w1
> +  mov   x0, #1
> +  mov   x1, #0
> +  csel  x0, x0, x1, eq
> +  ret
> +
> +//
> +// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the
> +// physical address space support on this CPU:
> +// 0 == 32 bits, 1 == 36 bits, etc etc
> +// 6 and 7 are reserved
> +//
> +.LPARanges:
> +  .byte 32, 36, 40, 42, 44, 48, -1, -1
> +
> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> diff --git a/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.c b/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.c
> new file mode 100644
> index 0000000000..ac6cc07a7f
> --- /dev/null
> +++ b/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.c
> @@ -0,0 +1,139 @@
> +/** @file
> +*
> +*  Copyright (c) 2019, Linaro Limited. All rights reserved.
> +*
> +*  SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/ArmLib.h>
> +#include <Library/ArmPlatformLib.h>
> +
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +
> +ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
> +  {
> +    // Cluster 0, Core 0
> +    0x0, 0x0,
> +
> +    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (UINT64)0xFFFFFFFF
> +  },
> +  {
> +    // Cluster 0, Core 1
> +    0x0, 0x1,
> +
> +    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (UINT64)0xFFFFFFFF
> +  },
> +  {
> +    // Cluster 0, Core 2
> +    0x0, 0x2,
> +
> +    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (UINT64)0xFFFFFFFF
> +  },
> +  {
> +    // Cluster 0, Core 3
> +    0x0, 0x3,
> +
> +    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (UINT64)0xFFFFFFFF
> +  }
> +};
> +
> +// This function should be better located into TimerLib implementation
> +RETURN_STATUS
> +EFIAPI
> +TimerConstructor (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Return the current Boot Mode
> +
> +  This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> +  VOID
> +  )
> +{
> +  return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> +  Initialize controllers that must setup in the normal world
> +
> +  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
> +  in the PEI phase.
> +
> +**/
> +RETURN_STATUS
> +ArmPlatformInitialize (
> +  IN  UINTN                     MpId
> +  )
> +{
> +  if (!ArmPlatformIsPrimaryCore (MpId)) {
> +    return RETURN_SUCCESS;
> +  }
> +
> +  return RETURN_SUCCESS;
> +}
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> +  OUT UINTN                   *CoreCount,
> +  OUT ARM_CORE_INFO           **ArmCoreTable
> +  )
> +{
> +  if (ArmIsMpCore()) {
> +    *CoreCount    = ARRAY_SIZE(mArmPlatformNullMpCoreInfoTable);
> +    *ArmCoreTable = mArmPlatformNullMpCoreInfoTable;
> +    return EFI_SUCCESS;
> +  } else {
> +    return EFI_UNSUPPORTED;
> +  }
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +
> +EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
> +  {
> +    EFI_PEI_PPI_DESCRIPTOR_PPI,
> +    &gArmMpCoreInfoPpiGuid,
> +    &mMpCoreInfoPpi
> +  }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> +  OUT UINTN                   *PpiListSize,
> +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
> +  )
> +{
> +  if (ArmIsMpCore()) {
> +    *PpiListSize = sizeof (gPlatformPpiTable);
> +    *PpiList = gPlatformPpiTable;
> +  } else {
> +    *PpiListSize = 0;
> +    *PpiList = NULL;
> +  }
> +}
> diff --git a/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.inf b/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.inf
> new file mode 100644
> index 0000000000..505b81a0a2
> --- /dev/null
> +++ b/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuLib.inf
> @@ -0,0 +1,51 @@
> +#/* @file
> +#
> +#  Copyright (c) 2019, Linaro Limited. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#*/
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001c
> +  BASE_NAME                      = SbsaQemuLib
> +  FILE_GUID                      = 6454006f-4236-46e2-9be4-4bba8d4b29fb
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = ArmPlatformLib
> +  CONSTRUCTOR                    = SbsaQemuLibConstructor
> +
> +[Sources]
> +  SbsaQemuMem.c
> +  SbsaQemuLib.c
> +  SbsaQemuHelper.S
> +
> +[Packages]
> +  ArmPkg/ArmPkg.dec
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +  EmbeddedPkg/EmbeddedPkg.dec
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  Silicon/Qemu/SbsaQemuPkg.dec
> +
> +[LibraryClasses]
> +  ArmLib
> +  BaseMemoryLib
> +  DebugLib
> +  FdtLib
> +  MemoryAllocationLib
> +  PcdLib
> +
> +[Pcd]
> +  gArmTokenSpaceGuid.PcdSystemMemoryBase
> +  gArmTokenSpaceGuid.PcdSystemMemorySize
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdFdBaseAddress
> +  gArmTokenSpaceGuid.PcdFdSize
> +  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> +  gArmTokenSpaceGuid.PcdArmPrimaryCore
> +
> +[Ppis]
> +  gArmMpCoreInfoPpiGuid
> diff --git a/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuMem.c b/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuMem.c
> new file mode 100644
> index 0000000000..2abf4764b8
> --- /dev/null
> +++ b/Silicon/Qemu/Library/SbsaQemuLib/SbsaQemuMem.c
> @@ -0,0 +1,145 @@
> +/** @file
> +
> +  Copyright (c) 2019, Linaro Limited. All rights reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/ArmLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <libfdt.h>
> +
> +// Number of Virtual Memory Map Descriptors
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          4
> +
> +RETURN_STATUS
> +EFIAPI
> +SbsaQemuLibConstructor (
> +  VOID
> +  )
> +{
> +  VOID          *DeviceTreeBase;
> +  INT32         Node, Prev;
> +  UINT64        NewBase, CurBase;
> +  UINT64        NewSize, CurSize;
> +  CONST CHAR8   *Type;
> +  INT32         Len;
> +  CONST UINT64  *RegProp;
> +  RETURN_STATUS PcdStatus;
> +
> +  NewBase = 0;
> +  NewSize = 0;
> +
> +  DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress);
> +  ASSERT (DeviceTreeBase != NULL);
> +
> +  // Make sure we have a valid device tree blob
> +  ASSERT (fdt_check_header (DeviceTreeBase) == 0);
> +
> +  // Look for the lowest memory node
> +  for (Prev = 0;; Prev = Node) {
> +    Node = fdt_next_node (DeviceTreeBase, Prev, NULL);
> +    if (Node < 0) {
> +      break;
> +    }
> +
> +    // Check for memory node
> +    Type = fdt_getprop (DeviceTreeBase, Node, "device_type", &Len);
> +    if (Type && AsciiStrnCmp (Type, "memory", Len) == 0) {
> +      // Get the 'reg' property of this node. For now, we will assume
> +      // two 8 byte quantities for base and size, respectively.
> +      RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);
> +      if (RegProp != 0 && Len == (2 * sizeof (UINT64))) {
> +
> +        CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));
> +        CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));
> +
> +        DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n",
> +          __FUNCTION__, CurBase, CurBase + CurSize - 1));
> +
> +        if (NewBase > CurBase || NewBase == 0) {
> +          NewBase = CurBase;
> +          NewSize = CurSize;
> +        }
> +      } else {
> +        DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n",
> +          __FUNCTION__));
> +      }
> +    }
> +  }
> +
> +  // Make sure the start of DRAM matches our expectation
> +  ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase);
> +  PcdStatus = PcdSet64S (PcdSystemMemorySize, NewSize);
> +  ASSERT_RETURN_ERROR (PcdStatus);
> +
> +  return RETURN_SUCCESS;
> +}
> +
> +/**
> +  Return the Virtual Memory Map of your platform
> +
> +  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU
> +  on your platform.
> +
> +  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR
> +                                    describing a Physical-to-Virtual Memory
> +                                    mapping. This array must be ended by a
> +                                    zero-filled entry. The allocated memory
> +                                    will not be freed.
> +
> +**/
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> +  OUT ARM_MEMORY_REGION_DESCRIPTOR   **VirtualMemoryMap
> +  )
> +{
> +  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
> +
> +  ASSERT (VirtualMemoryMap != NULL);
> +
> +  VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> +                                     MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> +  if (VirtualMemoryTable == NULL) {
> +    DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
> +    return;
> +  }
> +
> +  // System DRAM
> +  VirtualMemoryTable[0].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
> +  VirtualMemoryTable[0].VirtualBase  = VirtualMemoryTable[0].PhysicalBase;
> +  VirtualMemoryTable[0].Length       = PcdGet64 (PcdSystemMemorySize);
> +  VirtualMemoryTable[0].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> +  DEBUG ((DEBUG_INFO, "%a: Dumping System DRAM Memory Map:\n"
> +          "\tPhysicalBase: 0x%lX\n"
> +          "\tVirtualBase: 0x%lX\n"
> +          "\tLength: 0x%lX\n",
> +          __FUNCTION__,
> +          VirtualMemoryTable[0].PhysicalBase,
> +          VirtualMemoryTable[0].VirtualBase,
> +          VirtualMemoryTable[0].Length));
> +
> +  // Peripheral space before DRAM
> +  VirtualMemoryTable[1].PhysicalBase = 0x0;
> +  VirtualMemoryTable[1].VirtualBase  = 0x0;
> +  VirtualMemoryTable[1].Length       = VirtualMemoryTable[0].PhysicalBase;
> +  VirtualMemoryTable[1].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> +  // Remap the FD region as normal executable memory
> +  VirtualMemoryTable[2].PhysicalBase = PcdGet64 (PcdFdBaseAddress);
> +  VirtualMemoryTable[2].VirtualBase  = VirtualMemoryTable[2].PhysicalBase;
> +  VirtualMemoryTable[2].Length       = FixedPcdGet32 (PcdFdSize);
> +  VirtualMemoryTable[2].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> +  // End of Table
> +  ZeroMem (&VirtualMemoryTable[3], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));
> +
> +  *VirtualMemoryMap = VirtualMemoryTable;
> +}
> diff --git a/Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c b/Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c
> new file mode 100644
> index 0000000000..eea4dab580
> --- /dev/null
> +++ b/Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c
> @@ -0,0 +1,40 @@
> +/** @file
> +
> + Copyright (c) 2019, Linaro Ltd. All rights reserved
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> + **/
> +
> +#include <Base.h>
> +#include <PiDxe.h>
> +#include <Library/NorFlashPlatformLib.h>
> +
> +#define QEMU_NOR_BLOCK_SIZE    SIZE_256KB
> +
> +EFI_STATUS
> +NorFlashPlatformInitialization (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +NOR_FLASH_DESCRIPTION mNorFlashDevice =
> +{
> + FixedPcdGet64(PcdFdBaseAddress),
> + FixedPcdGet64(PcdFdBaseAddress),
> + FixedPcdGet32(PcdFdSize),
> + QEMU_NOR_BLOCK_SIZE
> +};
> +
> +EFI_STATUS
> +NorFlashPlatformGetDevices (
> +  OUT NOR_FLASH_DESCRIPTION   **NorFlashDescriptions,
> +  OUT UINT32                  *Count
> +  )
> +{
> +  *NorFlashDescriptions = &mNorFlashDevice;
> +  *Count = 1;
> +  return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf b/Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf
> new file mode 100644
> index 0000000000..e984c6497a
> --- /dev/null
> +++ b/Silicon/Qemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf
> @@ -0,0 +1,29 @@
> +#/** @file
> +#
> +#  Component description file for SbsaNorFlashQemuLib module
> +#
> +#  Copyright (c) 2019, Linaro Ltd. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001c
> +  BASE_NAME                      = SbsaNorFlashQemuLib
> +  FILE_GUID                      = c53d904d-de50-40f1-a148-a2ece48303d8
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = NorFlashPlatformLib
> +
> +[Sources.common]
> +  SbsaQemuNorFlashLib.c
> +
> +[Packages]
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +  ArmPkg/ArmPkg.dec
> +  MdePkg/MdePkg.dec
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdFdBaseAddress
> +  gArmTokenSpaceGuid.PcdFdSize
> diff --git a/Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c b/Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
> new file mode 100644
> index 0000000000..ceef76214a
> --- /dev/null
> +++ b/Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
> @@ -0,0 +1,215 @@
> +/** @file
> +  PCI Host Bridge Library instance for pci-ecam-generic DT nodes
> +
> +  Copyright (c) 2019, Linaro Ltd. All rights reserved
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include <PiDxe.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +
> +#pragma pack(1)
> +typedef struct {
> +  ACPI_HID_DEVICE_PATH     AcpiDevicePath;
> +  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
> +  {
> +    {
> +      ACPI_DEVICE_PATH,
> +      ACPI_DP,
> +      {
> +        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
> +        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
> +      }
> +    },
> +    EISA_PNP_ID(0x0A03),
> +    0
> +  },
> +
> +  {
> +    END_DEVICE_PATH_TYPE,
> +    END_ENTIRE_DEVICE_PATH_SUBTYPE,
> +    {
> +      END_DEVICE_PATH_LENGTH,
> +      0
> +    }
> +  }
> +};
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> +  L"Mem", L"I/O", L"Bus"
> +};
> +
> +STATIC PCI_ROOT_BRIDGE mRootBridge = {
> +  /* UINT32 Segment; Segment number */
> +  0,
> +
> +  /* UINT64 Supports; Supported attributes */
> +  EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
> +  EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16,
> +
> +  /* UINT64 Attributes; Initial attributes */
> +  EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
> +  EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16,
> +
> +  /* BOOLEAN DmaAbove4G; DMA above 4GB memory */
> +  TRUE,
> +
> +  /* BOOLEAN NoExtendedConfigSpace; When FALSE, the root bridge supports
> +     Extended (4096-byte) Configuration Space.  When TRUE, the root bridge
> +     supports 256-byte Configuration Space only. */
> +  FALSE,
> +
> +  /* BOOLEAN ResourceAssigned; Resource assignment status of the root bridge.
> +     Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned */
> +  FALSE,
> +
> +  /* UINT64 AllocationAttributes; Allocation attributes. */
> +  EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
> +  EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */
> +
> +  {
> +     /* PCI_ROOT_BRIDGE_APERTURE Bus; Bus aperture which can be used by the
> +      * root bridge. */
> +     FixedPcdGet32 (PcdPciBusMin),
> +     FixedPcdGet32 (PcdPciBusMax)
> +  },
> +
> +  /* PCI_ROOT_BRIDGE_APERTURE Io; IO aperture which can be used by the root
> +     bridge */
> +  {
> +     FixedPcdGet64 (PcdPciIoBase),
> +     FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
> +  },
> +
> +  /* PCI_ROOT_BRIDGE_APERTURE Mem; MMIO aperture below 4GB which can be used by
> +     the root bridge
> +     (gArmTokenSpaceGuid.PcdPciMmio32Translation as 0x0) */
> +  {
> +    FixedPcdGet32 (PcdPciMmio32Base),
> +    FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1,
> +  },
> +
> +  /* PCI_ROOT_BRIDGE_APERTURE MemAbove4G; MMIO aperture above 4GB which can be
> +     used by the root bridge.
> +     (gArmTokenSpaceGuid.PcdPciMmio64Translation as 0x0) */
> +  {
> +    FixedPcdGet64 (PcdPciMmio64Base),
> +    FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
> +  },
> +
> +  /* PCI_ROOT_BRIDGE_APERTURE PMem; Prefetchable MMIO aperture below 4GB which
> +     can be used by the root bridge.
> +     In our case, there are no separate ranges for prefetchable and
> +     non-prefetchable BARs */
> +  { MAX_UINT64, 0 },
> +
> +  /* PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; Prefetchable MMIO aperture above 4GB
> +     which can be used by the root bridge. */
> +  { MAX_UINT64, 0 },
> +  /* EFI_DEVICE_PATH_PROTOCOL *DevicePath; Device path. */
> +  (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath,
> +};
> +
> +/**
> +  Return all the root bridge instances in an array.
> +
> +  @param Count  Return the count of root bridge instances.
> +
> +  @return All the root bridge instances in an array.
> +          The array should be passed into PciHostBridgeFreeRootBridges()
> +          when it's not used.
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> +  UINTN *Count
> +  )
> +{
> +  *Count = 1;
> +  return &mRootBridge;
> +}
> +
> +/**
> +  Free the root bridge instances array returned from
> +  PciHostBridgeGetRootBridges().
> +
> +  @param Bridges The root bridge instances array.
> +  @param Count   The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> +  PCI_ROOT_BRIDGE *Bridges,
> +  UINTN           Count
> +  )
> +{
> +  ASSERT (Count == 1);
> +}
> +
> +/**
> +  Inform the platform that the resource conflict happens.
> +
> +  @param HostBridgeHandle Handle of the Host Bridge.
> +  @param Configuration    Pointer to PCI I/O and PCI memory resource
> +                          descriptors. The Configuration contains the resources
> +                          for all the root bridges. The resource for each root
> +                          bridge is terminated with END descriptor and an
> +                          additional END is appended indicating the end of the
> +                          entire resources. The resource descriptor field
> +                          values follow the description in
> +                          EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> +                          .SubmitResources().
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> +  EFI_HANDLE                        HostBridgeHandle,
> +  VOID                              *Configuration
> +  )
> +{
> +  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> +  UINTN                             RootBridgeIndex;
> +  DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> +  RootBridgeIndex = 0;
> +  Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> +  while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> +    DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> +    for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> +      ASSERT (Descriptor->ResType <
> +               ARRAY_SIZE(mPciHostBridgeLibAcpiAddressSpaceTypeStr));
> +      DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> +              mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> +              Descriptor->AddrLen, Descriptor->AddrRangeMax
> +              ));
> +      if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> +        DEBUG ((DEBUG_ERROR, "     Granularity/SpecificFlag = %ld / %02x%s\n",
> +                Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> +                ((Descriptor->SpecificFlag &
> +                  EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> +                  ) != 0) ? L" (Prefetchable)" : L""
> +                ));
> +      }
> +    }
> +    //
> +    // Skip the END descriptor for root bridge
> +    //
> +    ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> +    Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> +                   (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> +                   );
> +  }
> +}
> diff --git a/Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf b/Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf
> new file mode 100644
> index 0000000000..f3c2472809
> --- /dev/null
> +++ b/Silicon/Qemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf
> @@ -0,0 +1,47 @@
> +## @file
> +#  PCI Host Bridge Library instance for pci-ecam-generic DT nodes
> +#
> +#  Copyright (c) 2019, Linaro Ltd. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001c
> +  BASE_NAME                      = SbsaQemuPciHostBridgeLib
> +  FILE_GUID                      = 151dbef1-332d-4a8f-963e-b8f6bebb891d
> +  MODULE_TYPE                    = DXE_DRIVER
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = PciHostBridgeLib
> +
> +#
> +# The following information is for reference only and not required by the build
> +# tools.
> +#
> +#  VALID_ARCHITECTURES           = AARCH64
> +#
> +
> +[Sources]
> +  SbsaQemuPciHostBridgeLib.c
> +
> +[Packages]
> +  ArmPkg/ArmPkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> +  DebugLib
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdPciBusMin
> +  gArmTokenSpaceGuid.PcdPciBusMax
> +  gArmTokenSpaceGuid.PcdPciIoBase
> +  gArmTokenSpaceGuid.PcdPciIoSize
> +  gArmTokenSpaceGuid.PcdPciMmio32Base
> +  gArmTokenSpaceGuid.PcdPciMmio32Size
> +  gArmTokenSpaceGuid.PcdPciMmio64Base
> +  gArmTokenSpaceGuid.PcdPciMmio64Size
> +
> +[Depex]
> +  TRUE
> diff --git a/Silicon/Qemu/SbsaQemuPkg.dec b/Silicon/Qemu/SbsaQemuPkg.dec
> new file mode 100644
> index 0000000000..a5aae5a9ab
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemuPkg.dec
> @@ -0,0 +1,40 @@
> +#/** @file
> +#
> +#  Copyright (c) 2019, Linaro Limited. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> +  DEC_SPECIFICATION              = 0x0001001B
> +  PACKAGE_NAME                   = SbsaQemuPkg
> +  PACKAGE_GUID                   = 8db32c5a-2821-43e2-b4ac-bc148e2b0b05
> +  PACKAGE_VERSION                = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +#                   Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +#[Includes.common]
> +#  Include                        # Root include for the package
> +
> +[LibraryClasses]
> +  ArmPlatformLib|Include/Library/ArmPlatformLib.h
> +
> +[Guids.common]
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid   = { 0xaab3bea9, 0xa8e8, 0x4e76, { 0xb5, 0x3a, 0x35, 0x22, 0x11, 0xce, 0xf7, 0xf7 } }
> +
> +[PcdsFixedAtBuild.common]
> +
> +  # Non discoverable devices Pcds
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase|0|UINT64|0x00000001
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize|0x10000|UINT32|0x00000002
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x00000003
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT32|0x00000004
> +  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000|UINT64|0x00000005
> -- 
> 2.26.2
> 

      reply	other threads:[~2020-05-23 22:19 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-22 13:00 [PATCH V4] SbsaQemu: EFI implementation for SbsaQemu platform Tanmay Jagdale
2020-05-23 22:18 ` Leif Lindholm [this message]

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