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Add the Chassis3V2 package. Signed-off-by: Pankaj Bansal --- Notes: V2: - No change Silicon/NXP/Chassis3V2/Chassis3V2.dec | 22 ++++++ Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 +++ Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf | 33 +++++++++ Silicon/NXP/Chassis3V2/Include/Chassis.h | 26 +++++++ Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c | 71 ++++++++++++= ++++++++ 5 files changed, 162 insertions(+) diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec b/Silicon/NXP/Chassis3V2= /Chassis3V2.dec new file mode 100644 index 000000000000..f7269e6bf6de --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec @@ -0,0 +1,22 @@ +# @file +# NXP Layerscape processor package. +# +# Copyright 2017, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEC_SPECIFICATION =3D 1.27 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc b/Silicon/NXP/Chassi= s3V2/Chassis3V2.dsc.inc new file mode 100644 index 000000000000..b9f388a59f2a --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc @@ -0,0 +1,10 @@ +# @file +# +# Copyright 2018-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[LibraryClasses.common] + ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf b/Sil= icon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf new file mode 100644 index 000000000000..75b68cc4ca2d --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf @@ -0,0 +1,33 @@ +# @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION =3D 1.27 + BASE_NAME =3D Chassis3V2Lib + FILE_GUID =3D fae0d077-5fc2-494f-b8e1-c51a3023ee3e + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ChassisLib + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/Chassis3V2/Chassis3V2.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + IoAccessLib + IoLib + PcdLib + SerialPortLib + +[Sources.common] + ChassisLib.c + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h b/Silicon/NXP/Chassis= 3V2/Include/Chassis.h new file mode 100644 index 000000000000..0fd70132d897 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h @@ -0,0 +1,26 @@ +/** @file + + Copyright 2018-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef CHASSIS_H__ +#define CHASSIS_H__ + +#include + +#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000 + +/** + The Device Configuration Unit provides general purpose configuration and + status for the device. These registers only support 32-bit accesses. +**/ +#pragma pack(1) +typedef struct { + UINT8 Reserved0[0x100 - 0x0]; + UINT32 RcwSr[32]; // Reset Control Word Status Register +} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG; +#pragma pack() + +#endif // CHASSIS_H__ diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c b/Silic= on/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c new file mode 100644 index 000000000000..30f8f945b233 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c @@ -0,0 +1,71 @@ +/** @file + Chassis specific functions common to all SOCs based on a specific Chessi= s + + Copyright 2018-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Read Dcfg register + + @param Address The MMIO register to read. + + @return The value read. +**/ +UINT32 +EFIAPI +DcfgRead32 ( + IN UINTN Address + ) +{ + MMIO_OPERATIONS *DcfgOps; + + DcfgOps =3D GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian)); + + return DcfgOps->Read32 (Address); +} + +/** + Write Dcfg register + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. +**/ +UINT32 +EFIAPI +DcfgWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + MMIO_OPERATIONS *DcfgOps; + + DcfgOps =3D GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian)); + + return DcfgOps->Write32 (Address, Value); +} + +/** + Function to initialize Chassis Specific functions + **/ +VOID +ChassisInit ( + VOID + ) +{ + // + // Early init serial Port to get board information. + // + SerialPortInitialize (); +} --=20 2.17.1