From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web12.6510.1591241275730400375 for ; Wed, 03 Jun 2020 20:27:57 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ray.ni@intel.com) IronPort-SDR: Ar+CMiC9m9Omb4PlKm1Zaa1WdwgxMC0T7Vl0WWF52wa+8V2ih3KCYp4S1ExMv+uIfV4BdEMkWW /bwwxo/pcIzQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2020 20:27:57 -0700 IronPort-SDR: oyob/uocw2/p1ZSDl3W1CU4CsEg/rJJWvk5TiYgTb02A/LNl2QuuPO7HR2aHu+ZNYPS6m1qp7H QADnBSvA3lUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,470,1583222400"; d="scan'208";a="471280229" Received: from ray-dev.ccr.corp.intel.com ([10.239.158.43]) by fmsmga006.fm.intel.com with ESMTP; 03 Jun 2020 20:27:56 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Maurice Ma , Guo Dong , Benjamin You Subject: [PATCH V2 2/2] UefiPayloadPkg/Pci: Use the PCIE Base Addr stored in AcpiBoardInfo HOB Date: Thu, 4 Jun 2020 11:27:10 +0800 Message-Id: <20200604032710.970-3-ray.ni@intel.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200604032710.970-1-ray.ni@intel.com> References: <20200604032710.970-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Today's UefiPayloadPkg always uses 0xE0000000 as the PCIE base address and ignores the value set in AcpiBoardInfo HOB created by the boot loader. This makes the payload binary cannot work in environment where the PCIE base address set by boot loader doesn't equal to 0xE0000000. The patch enhances UefiPayloadPkg so that the PCIE base address set by boot loader in the AcpiBoardInfo HOB is used. Signed-off-by: Ray Ni Cc: Maurice Ma Cc: Guo Dong Cc: Benjamin You --- .../PciSegmentInfoLibAcpiBoardInfo.c | 59 +++++++++++++++++++ .../PciSegmentInfoLibAcpiBoardInfo.inf | 36 +++++++++++ UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 16 +---- 3 files changed, 98 insertions(+), 13 deletions(-) create mode 100644 UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/P= ciSegmentInfoLibAcpiBoardInfo.c create mode 100644 UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/P= ciSegmentInfoLibAcpiBoardInfo.inf diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegme= ntInfoLibAcpiBoardInfo.c b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoar= dInfo/PciSegmentInfoLibAcpiBoardInfo.c new file mode 100644 index 0000000000..d37c91cc9f --- /dev/null +++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoL= ibAcpiBoardInfo.c @@ -0,0 +1,59 @@ +/** @file=0D + PCI Segment Information Library that returns one segment whose=0D + segment base address is retrieved from AcpiBoardInfo HOB.=0D +=0D + Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +STATIC PCI_SEGMENT_INFO mPciSegment0 =3D {=0D + 0, // Segment number=0D + 0, // To be fixed later=0D + 0, // Start bus number=0D + 255 // End bus number=0D +};=0D +=0D +/**=0D + Return an array of PCI_SEGMENT_INFO holding the segment information.=0D +=0D + Note: The returned array/buffer is owned by callee.=0D +=0D + @param Count Return the count of segments.=0D +=0D + @retval A callee owned array holding the segment information.=0D +**/=0D +PCI_SEGMENT_INFO *=0D +EFIAPI=0D +GetPciSegmentInfo (=0D + UINTN *Count=0D + )=0D +{=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + ACPI_BOARD_INFO *AcpiBoardInfo;=0D +=0D + ASSERT (Count !=3D NULL);=0D + if (Count =3D=3D NULL) {=0D + return NULL;=0D + }=0D +=0D + if (mPciSegment0.BaseAddress =3D=3D 0) {=0D + //=0D + // Find the acpi board information guid hob=0D + //=0D + GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);=0D + ASSERT (GuidHob !=3D NULL);=0D +=0D + AcpiBoardInfo =3D (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (GuidHob);=0D + mPciSegment0.BaseAddress =3D AcpiBoardInfo->PcieBaseAddress;=0D + }=0D + *Count =3D 1;=0D + return &mPciSegment0;=0D +}=0D diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegme= ntInfoLibAcpiBoardInfo.inf b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBo= ardInfo/PciSegmentInfoLibAcpiBoardInfo.inf new file mode 100644 index 0000000000..ec4dbaaa55 --- /dev/null +++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoL= ibAcpiBoardInfo.inf @@ -0,0 +1,36 @@ +## @file=0D +# PCI Segment Information Library that returns one segment whose=0D +# segment base address is retrieved from AcpiBoardInfo HOB.=0D +#=0D +# Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PciSegmentInfoLibAcpiBoardInfo=0D + FILE_GUID =3D 0EA82AA2-6C36-4FD5-BC90-FFA3ECB5E0CE= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PciSegmentInfoLib | DXE_DRIVER=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D +#=0D +=0D +[Sources]=0D + PciSegmentInfoLibAcpiBoardInfo.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + UefiPayloadPkg/UefiPayloadPkg.dec=0D +=0D +[LibraryClasses]=0D + PcdLib=0D + HobLib=0D + DebugLib=0D diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/Uefi= PayloadPkgIa32X64.dsc index 0736cd9954..62d680eb79 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc @@ -3,7 +3,7 @@ #=0D # Provides drivers and definitions to create uefi payload for bootloaders.= =0D #=0D -# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D @@ -38,11 +38,6 @@ [Defines] #=0D DEFINE MAX_LOGICAL_PROCESSORS =3D 64=0D =0D - #=0D - # PCI options=0D - #=0D - DEFINE PCIE_BASE =3D 0xE0000000=0D -=0D #=0D # Serial port set up=0D #=0D @@ -122,14 +117,10 @@ [LibraryClasses] PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf=0D IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D -!if $(PCIE_BASE) =3D=3D 0=0D PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D -!else=0D - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf=0D - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf=0D -!endif=0D - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf=0D + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibS= egmentInfo.inf=0D + PciSegmentInfoLib|UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/= PciSegmentInfoLibAcpiBoardInfo.inf=0D PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf=0D @@ -288,7 +279,6 @@ [PcdsFixedAtBuild] gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE=0D gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 }=0D =0D - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)=0D =0D !if $(SOURCE_DEBUG_ENABLE)=0D gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2=0D --=20 2.26.2.windows.1