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Fri, 05 Jun 2020 05:38:13 -0700 (PDT) Date: Fri, 5 Jun 2020 13:38:11 +0100 From: "Leif Lindholm" To: Wasim Khan Cc: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, Wasim Khan Subject: Re: [PATCH edk2-platforms 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers Message-ID: <20200605123811.GF28566@vanye> References: <1591039658-18541-1-git-send-email-wasim.khan@oss.nxp.com> <1591039658-18541-4-git-send-email-wasim.khan@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <1591039658-18541-4-git-send-email-wasim.khan@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jun 02, 2020 at 00:57:38 +0530, Wasim Khan wrote: > From: Wasim Khan > > Based on the serdes protocol value in reset configuration > word (RCW), different PCIe controllers are enabled. > Get serdes protocol map and initialize only enabled PCIe > controllers. > > Signed-off-by: Wasim Khan > --- > Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + > Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++++++++++- > 2 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > index aa5a9dec7c34..6003da708698 100644 > --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -28,6 +28,7 @@ [LibraryClasses] > IoAccessLib > MemoryAllocationLib > PcdLib > + SocLib > > [FeaturePcd] > gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > index 549f4fa133fb..323afc2015ae 100644 > --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -719,6 +720,32 @@ PcieSetupCntrl ( > } > > /** > + This function checks whether PCIe is enabled or not > + depending upon SoC serdes protocol map > + > + @param PcieNum PCIe number. > + > + @return The PCIe number enabled in map. > + @return FALSE PCIe number is disabled in map. > + > +**/ > +STATIC > +BOOLEAN > +IsPcieNumEnabled( > + IN UINTN PcieNum > + ) > +{ > + UINT64 SerDesProtocolMap; > + > + SerDesProtocolMap = 0x0; There is nothing magical about hexadecimal zero. 0 is sufficient. > + > + // Reading serdes protocol map > + GetSerdesProtocolMaps (&SerDesProtocolMap); > + > + return (SerDesProtocolMap & (0x1u << (PcieNum))) != 0 ; BIT0, or simply 1. No space before ;. / Leif > +} > + > +/** > Return all the root bridge instances in an array. > > @param Count Return the count of root bridge instances. > @@ -750,13 +777,19 @@ PciHostBridgeGetRootBridges ( > PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); > Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); > > + // Check is the PCIe controller is enabled > + if (IsPcieNumEnabled (Idx + 1) == 0) { > + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Regs[Idx])); > + continue; > + } > + > // Check PCIe Link > LinkUp = PcieLinkUp(Regs[Idx], Idx); > > if (!LinkUp) { > continue; > } > - DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1)); > + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx + 1, Regs[Idx])); > // Set up PCIe Controller and ATU windows > PcieSetupCntrl (Regs[Idx], > PciPhyCfg0Addr[Idx], > -- > 2.7.4 >