From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.groups.io with SMTP id smtpd.web12.11606.1591365633646877259 for ; Fri, 05 Jun 2020 07:00:34 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=BehK9aze; spf=pass (domain: nuviainc.com, ip: 209.85.128.66, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f66.google.com with SMTP id q25so9257713wmj.0 for ; Fri, 05 Jun 2020 07:00:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=EzhBw5Vj2xF4vrtk+50Xj8Nn6FGhJ5zPWjuSgfhPgos=; b=BehK9azeHj24PtHJtwPCnbcec3KwBEkRJ9lHTaFQ+ORpyG8S6vfCAabEWsaccVXjvJ o6D+5QOSmjiNxvLC7PuMgSIs801iSlm7dDfags6flJun9GZaItjU2ZoMed5fP3RkF1Ab GSzeZFIkbaQFt2aZLaH6S/RbxW+NKfBSKTuN3APwSeCmdOEtzYVSKzNW7yXbXfinDiaJ TKbG6t+V178Sv2460RlGSWPfGyziJPsy0/nbnCcWzAvZudH5q+gCRgEOMnw1Q4DV6NdP epssNunPJ5jMdnSaM4Q9uv00R6sLoWqgP/CnITYF06KFffYAVz9oFPhul4acXOqGk5JA oj+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=EzhBw5Vj2xF4vrtk+50Xj8Nn6FGhJ5zPWjuSgfhPgos=; b=kVY21KygMN+oLJfbh7A/nNapQqlqBqwKOQfKyXHm8kQbXGm7YOstYWcCm6ZEt9OeA5 YVSXj89T3kAJBaM0jpDCo3LU3OzGSUe460a3Gc6qdS1sATqhBFKpiZfV9URXuJSffpKO DMFfUhCEGPdn5fu+OdSJQCchTU/bUZvoYBffhik9G8HKSxocKfYAtCyk5W7RQogt7g1Q 5VXsLiZveBKvX2JlrkM2ufDP2v3wA22N4TPeMKjiZfucwOPiZx0CeN84h04QmJZGQ3wQ vSpIuL6rmo+LNRcQGGvAMOzgfvaKQuJTyOgtbIlnxrL4o4RQDzhye1yAAcQLfVkIgf/K rEnQ== X-Gm-Message-State: AOAM532zteKeRsUW3Qr+ha5MgvIO5TIbc8GEwGV3Xj6zICbAZFDrqXcg vmLVi/zfsc8OkVuT2sT8JXyjbw== X-Google-Smtp-Source: ABdhPJx7bTm9qYIFF0nhOc5fBHwU/5Wwg4LtMrDJiGwJdASN+tsKROYnL40gzYzq9XgNm/OT4JguZg== X-Received: by 2002:a1c:2643:: with SMTP id m64mr2812639wmm.158.1591365632243; Fri, 05 Jun 2020 07:00:32 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id x186sm11349882wmg.8.2020.06.05.07.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jun 2020 07:00:30 -0700 (PDT) Date: Fri, 5 Jun 2020 15:00:28 +0100 From: "Leif Lindholm" To: Pankaj Bansal Cc: Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Augustine Philips , Ard Biesheuvel , Arokia Samy , Kuldip Dwivedi Subject: Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation Message-ID: <20200605140028.GH28566@vanye> References: <20200602132503.27154-1-pankaj.bansal@oss.nxp.com> <20200602132503.27154-2-pankaj.bansal@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <20200602132503.27154-2-pankaj.bansal@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote: > From: Pankaj Bansal > > for LS1043A SOC the DCFG registers are read in big endian format. > However current Platofmr PLL calculation is being done assuing the Platform? assuming > little endian format. > > Fix the Platform PLL calculation OK, now I'm confused. DCFG is read using the DcfgRead32 function, which is supposed to handle the endianness issue. Ls1043a builds with gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE which means GetMmioOperations() returns the byte-swapping versions. Please clarify. / Leif > Signed-off-by: Pankaj Bansal > --- > Silicon/NXP/LS1043A/Include/Soc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h > index 97a77d3f5da6..afcd9da34cda 100644 > --- a/Silicon/NXP/LS1043A/Include/Soc.h > +++ b/Silicon/NXP/LS1043A/Include/Soc.h > @@ -48,7 +48,7 @@ > /** > Reset Control Word (RCW) Bits > **/ > -#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 > +#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 > > typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG; > > -- > 2.17.1 >