From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by mx.groups.io with SMTP id smtpd.web11.31073.1591626149263569725 for ; Mon, 08 Jun 2020 07:22:29 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=F9SapZLM; spf=pass (domain: nuviainc.com, ip: 209.85.221.66, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f66.google.com with SMTP id y17so17590522wrn.11 for ; Mon, 08 Jun 2020 07:22:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=PK1mhuByrWnHkSlBY3ytt2x1iKnNaBXvs4vcZckoSjA=; b=F9SapZLMhKt2U2e3rqA34VdFEoiZNVOfLESHdhn0CUhyur4l2E/OIoZl4LnkH56/kP rQwNMMEdQAL1koxHOxF35Yuk++ZbyfMChCvAzI+2Vqx2zQzD0CdwkmV/DShU3QTZ8Csh NhDJa0HTTYl4phkjluCF+UOKHv4Fqha3CG6KLMPJlZxuDDTh4sjVma3f3lLYestf5f1A 9Zw5nJF636vTm2MRE+UQauaO8UoqG5sc8FRhcCnNnlz3y/8fdeppPz5EwhabJJdZHfUI 9iAOUtQySiWgze7HnuboFfV296u+jKrEWDcaul2X2BXAYOmZ8wu2oz4mif5ZMx8/8nxj 3TXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=PK1mhuByrWnHkSlBY3ytt2x1iKnNaBXvs4vcZckoSjA=; b=tBYKp+Tgqg8Hm2rNcye4wSjDd1BdfNHOY8mhGsw15VxphyU7CdlFtIJZgQtBkD3tMv EOTKp5VLWgd1uR1b21gqEH0P4mDmOVNk21sgPPnu3+87yd4DK8/RFRoAcmBOLLfnRyJR Bb1m8ZBHYMWMLE4Su+v2aJ+JxEc9vu8kuxFZ5+IUCIu6Zqatmzov9BnpSbHhIuqRwRL8 5S1Iv1JUtvXnu/GoGYVYq6e20/6tgTSObkIk1SrTp0U3jNqVsGjWFofeLPQeut1CECGg 53UqaOl4qfXihlM1XYrTux6QPMI+MVgTBgcdoKo9qeV7STlT/CjFP0zQYLFGqvwNhGpf hRKw== X-Gm-Message-State: AOAM532qducul5XNGdF5KH4TzeTXfI2F6sE+veH7QLaQCv6GLce7zSNa taDVXcGIiZf1TiqEm+Xcxlj0Og== X-Google-Smtp-Source: ABdhPJxlrNxdSGsbwITEtYi+uYKmbI/w/9RaYv8THvLugJefY9cBYAYBgIYZhKdpiK2YgEoV7wt2oA== X-Received: by 2002:adf:9286:: with SMTP id 6mr24110206wrn.361.1591626147814; Mon, 08 Jun 2020 07:22:27 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id u7sm23853872wrm.23.2020.06.08.07.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 07:22:27 -0700 (PDT) Date: Mon, 8 Jun 2020 15:22:25 +0100 From: "Leif Lindholm" To: "Pankaj Bansal (OSS)" Cc: Meenakshi Aggarwal , Michael D Kinney , "devel@edk2.groups.io" , Varun Sethi , Samer El-Haj-Mahmoud , Augustine Philips , Ard Biesheuvel , Arokia Samy , kuldip dwivedi Subject: Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation Message-ID: <20200608142224.GN28566@vanye> References: <20200602132503.27154-1-pankaj.bansal@oss.nxp.com> <20200602132503.27154-2-pankaj.bansal@oss.nxp.com> <20200605140028.GH28566@vanye> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Jun 05, 2020 at 17:18:54 +0000, Pankaj Bansal (OSS) wrote: > > On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote: > > > From: Pankaj Bansal > > > > > > for LS1043A SOC the DCFG registers are read in big endian format. > > > However current Platofmr PLL calculation is being done assuing the > > > > Platform? assuming > > yes. typo mistake. > > > > > > little endian format. > > > > > > Fix the Platform PLL calculation > > > > OK, now I'm confused. > > DCFG is read using the DcfgRead32 function, which is supposed to > > handle the endianness issue. > > > > Ls1043a builds with > > gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE > > which means GetMmioOperations() returns the byte-swapping versions. > > > > Please clarify. > > OK. so this might be little confusing, so bear with me. > The reset configuration word (RCW) is 512 bits (1024 bits in LS2088 > / LS2160) long and contains all necessary configuration information > for the chip. RCW data is read from external memory (Nor flash or > SD/eMMC card or I2c eeprom) and written to the RCW status registers > (RCWSR) contained in the Device Configuration and Pin Control module > (DCSR), after which the device is configured as specified in the > RCW. > > The PreBoot Loader (PBL) fetches RCW data from the source memory > device and writes it to the RCW status registers. > Now the PBL fetches the data from flash in little endian format and > writes it to the DCSR registers in little endian format always. > This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088). This PBL is a ROM executing before the EDK2 code? > Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we > read the RCWSR registers in big endian fashion. > This causes the bit position to be reversed. I'm still not following. We've set up this elaborate Rube Goldberg machine to be able to *not* have to carry separate header files for devices with individual components with registers that may be big- or little-endian depending on which SoC/version they are in. And now we have an implementation that states that its DcfgRead operations need to happan as big-endian. And the *only* time the Dcfg registers are accessed, we immediately need to change the header file to treat it as little-endian? What is the situation where Dcfg accesses *need* to be big-endian? Regards, Leif > In SOCs where DCSR space is little endian (LS2088 / LX2160), we read > the RCWSR registers in little endian fashion. > That is why the bit position is correct. > > > > > / > > Leif > > > > > Signed-off-by: Pankaj Bansal > > > --- > > > Silicon/NXP/LS1043A/Include/Soc.h | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h > > b/Silicon/NXP/LS1043A/Include/Soc.h > > > index 97a77d3f5da6..afcd9da34cda 100644 > > > --- a/Silicon/NXP/LS1043A/Include/Soc.h > > > +++ b/Silicon/NXP/LS1043A/Include/Soc.h > > > @@ -48,7 +48,7 @@ > > > /** > > > Reset Control Word (RCW) Bits > > > **/ > > > -#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 > > > +#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 > > > > > > typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG > > LS1043A_DEVICE_CONFIG; > > > > > > -- > > > 2.17.1 > > >