From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.groups.io with SMTP id smtpd.web10.32629.1591630356803196135 for ; Mon, 08 Jun 2020 08:32:37 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=xgx96TK/; spf=pass (domain: nuviainc.com, ip: 209.85.221.68, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f68.google.com with SMTP id y17so17862995wrn.11 for ; Mon, 08 Jun 2020 08:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=XWFAz54YewaupahrhMteoPjF13StRwflKQLj+cbkFXI=; b=xgx96TK/zttq6hEPSEDgpN7yNbMI+EogGygMjUVKbX9oQYtK7jmT34I3P4Nr/9UUS4 j4juDzfNglREp51BqJRw9Kn6GQvEgVnYuy7qy4Iw5sZyWnvOjY7nxa9TRhA1avm728t/ ZHAZEa89B5bY7xD9DsTd4IJcDZjr9zmvZtoPXTbFpjEtLC64U7EAUtCGpHaF+K7K2QQW DRVmJwPkSneYLoEvuX2sknHIUOvn4vQvnpAQUBF5WEn32rMviNHLaIf1ilz4qgBXan2g A4YJQPeSLs0sSCxzYhPT0n+7P0JLknmEkKi+RU9HAuZ9/v4R6nysxTWFLCa7s9U/vla3 MeXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=XWFAz54YewaupahrhMteoPjF13StRwflKQLj+cbkFXI=; b=e1lhlE1yNTt0hGYP+ORqLW8tGzNYVqrSyYVCDKztyyRlrQvSwu9RyyDW9+A9WmouCn Loh/jFToywkeDR+SAOCtC+FYYXHWHjRzejKfuCr5UVCLa3w9tlO0FMyw4bzBSODHREpr 6MmVxUoCRHRnD1sUQHQAl6bl2UHyNa5wNLqnyRCdItLAoocE5AR34S4acIFFwTH9rKQJ V/3b80TMIDyj9Dog1XLeeD55gzQwz/kYwjtvNCpaL5xleHiUwaBBmubMlY+x0dfGjPRN P5uL/nXkLgd5ajTChtsSUOVi29hQQ55jVc+WUCrPVzdweWsbVAGO1t4HvdzJXoPVFOjK 8Elg== X-Gm-Message-State: AOAM530V69Y6cXfQgHaoCkq9VW7ldaAVv3VM69dZ6jugCyudEyRNqEyc f5y7LebPNSdi8eLc9cbIhvaSVw== X-Google-Smtp-Source: ABdhPJyPd8uCQ/0aLOo7J0pM1xqDg1g1VXxv+HQ5hl5RCeO+CdyEkFiW9AF/wA2JELE4OTvHNDh20A== X-Received: by 2002:a05:6000:4c:: with SMTP id k12mr23734113wrx.215.1591630355451; Mon, 08 Jun 2020 08:32:35 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id y17sm108068wrn.12.2020.06.08.08.32.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 08:32:34 -0700 (PDT) Date: Mon, 8 Jun 2020 16:32:32 +0100 From: "Leif Lindholm" To: Wasim Khan Cc: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, Wasim Khan Subject: Re: [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers Message-ID: <20200608153232.GR28566@vanye> References: <1591535750-15743-1-git-send-email-wasim.khan@oss.nxp.com> <1591535750-15743-4-git-send-email-wasim.khan@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <1591535750-15743-4-git-send-email-wasim.khan@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Jun 07, 2020 at 18:45:50 +0530, Wasim Khan wrote: > From: Wasim Khan > > Based on the serdes protocol value in reset configuration > word (RCW), different PCIe controllers are enabled. > Get SerDes protocol map and initialize only enabled PCIe > controllers. > > Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm For simplicity, could you send a full v3 out please? Regards, Leif > --- > > Notes: > Changes in V2: > - Addressed review comments for structure, variable and function names > - Using BIT0 instead of 0x1u > > Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + > Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++++++++++- > 2 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > index aa5a9dec7c34..6003da708698 100644 > --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -28,6 +28,7 @@ [LibraryClasses] > IoAccessLib > MemoryAllocationLib > PcdLib > + SocLib > > [FeaturePcd] > gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > index e5309a4f4248..8bbbaaa6e24d 100644 > --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -721,6 +722,32 @@ PcieSetupCntrl ( > } > > /** > + This function checks whether PCIe is enabled or not > + depending upon SoC serdes protocol map > + > + @param PcieNum PCIe number. > + > + @return The PCIe number enabled in map. > + @return FALSE PCIe number is disabled in map. > + > +**/ > +STATIC > +BOOLEAN > +IsPcieNumEnabled( > + IN UINTN PcieNum > + ) > +{ > + UINT64 SerDesProtocolMap; > + > + SerDesProtocolMap = 0; > + > + // Reading serdes protocol map > + GetSerDesProtocolMap (&SerDesProtocolMap); > + > + return (SerDesProtocolMap & (BIT0 << (PcieNum))) != 0; > +} > + > +/** > Return all the root bridge instances in an array. > > @param Count Return the count of root bridge instances. > @@ -752,13 +779,19 @@ PciHostBridgeGetRootBridges ( > PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); > Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); > > + // Check is the PCIe controller is enabled > + if (IsPcieNumEnabled (Idx + 1) == 0) { > + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Regs[Idx])); > + continue; > + } > + > // Check PCIe Link > LinkUp = PcieLinkUp(Regs[Idx], Idx); > > if (!LinkUp) { > continue; > } > - DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1)); > + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx + 1, Regs[Idx])); > // Set up PCIe Controller and ATU windows > PcieSetupCntrl (Regs[Idx], > PciPhyCfg0Addr[Idx], > -- > 2.7.4 >