[PATCH edk2-platforms 0/5] Add LS1046AFRWY Platform

[PATCH edk2-platforms 0/5] Add LS1046AFRWY Platform

[Pankaj Bansal]

From: Pankaj Bansal <pankaj.bansal@nxp.com>

The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.

The LS1046A SOC is based on Layerscape Chassis2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

Pankaj Bansal (5):
  Silicon/NXP/LS1043A: Fix the Platform PLL calculation
  Silicon/NXP: Add LS1046A Soc package
  Platform/NXP/LS1046AFRWY: Add ArmPlatformLib
  Platform/NXP: Add LS1046AFRWY Platform
  Platform/NXP/LS1046aFrwyPkg: Add VarStore

 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec     |  23 +++
 Silicon/NXP/LS1046A/LS1046A.dec               |  13 ++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc           |  42 +++++
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc     |  46 +++++
 .../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf     | 169 ++++++++++++++++++
 .../Library/ArmPlatformLib/ArmPlatformLib.inf |  42 +++++
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  27 +++
 Silicon/NXP/LS1043A/Include/Soc.h             |   2 +-
 Silicon/NXP/LS1046A/Include/Soc.h             |  36 ++++
 .../Library/ArmPlatformLib/ArmPlatformLib.c   | 147 +++++++++++++++
 .../ArmPlatformLib/ArmPlatformLibMem.c        |  76 ++++++++
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   |  78 ++++++++
 .../AArch64/ArmPlatformHelper.S               |  45 +++++
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc  |  91 ++++++++++
 14 files changed, 836 insertions(+), 1 deletion(-)
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
 create mode 100644 Silicon/NXP/LS1046A/Include/Soc.h
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
 create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
 create mode 100644 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc

-- 
2.17.1

[PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

[Pankaj Bansal]

From: Pankaj Bansal <pankaj.bansal@nxp.com>

for LS1043A SOC the DCFG registers are read in big endian format.
However current Platofmr PLL calculation is being done assuing the
little endian format.

Fix the Platform PLL calculation

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
 Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index 97a77d3f5da6..afcd9da34cda 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -48,7 +48,7 @@
 /**
   Reset Control Word (RCW) Bits
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
 
 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
 
-- 
2.17.1

[PATCH edk2-platforms 2/5] Silicon/NXP: Add LS1046A Soc package

[Pankaj Bansal]

From: Pankaj Bansal <pankaj.bansal@nxp.com>

LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.

Co-authored-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Co-authored-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
 Silicon/NXP/LS1046A/LS1046A.dec               | 13 ++++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc           | 42 +++++++++++
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 27 +++++++
 Silicon/NXP/LS1046A/Include/Soc.h             | 36 +++++++++
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   | 78 ++++++++++++++++++++
 5 files changed, 196 insertions(+)

diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index 000000000000..deb473b549c2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,13 @@
+# LS1046A.dec
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x0001001B
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index 000000000000..dbe7f408fce9
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,42 @@
+#  LS1046A.dsc
+#  LS1046A Soc package.
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
+
+[PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+[PcdsFeatureFlag]
+  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+##
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
new file mode 100644
index 000000000000..01ed0f6592d2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+#  @file
+#
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = SocLib
+  FILE_GUID                      = ddd5f950-8816-4d38-8f98-f42b07333f78
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SocLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
+  Silicon/NXP/LS1046A/LS1046A.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ChassisLib
+  DebugLib
+
+[Sources.common]
+  SocLib.c
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
new file mode 100644
index 000000000000..6ff8db927865
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -0,0 +1,36 @@
+/** @file
+
+  Copyright 2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include <Chassis.h>
+
+/**
+  Soc Memory Map
+**/
+#define LS1046A_DRAM0_PHYS_ADDRESS   (BASE_2GB)
+#define LS1046A_DRAM0_SIZE           (SIZE_2GB)
+#define LS1046A_DRAM1_PHYS_ADDRESS   (BASE_32GB + BASE_2GB)
+#define LS1046A_DRAM1_SIZE           (SIZE_32GB - SIZE_2GB) // 30 GB
+
+#define LS1046A_CCSR_PHYS_ADDRESS    (BASE_16MB)
+#define LS1046A_CCSR_SIZE            (SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LS1046A_QSPI0_PHYS_ADDRESS   (BASE_1GB)
+#define LS1046A_QSPI0_SIZE           (SIZE_512MB)
+
+#define LS1046A_DCFG_ADDRESS         NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+  Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+
+#endif // SOC_H__
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
new file mode 100644
index 000000000000..3b15aee6ecae
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -0,0 +1,78 @@
+/** @Soc.c
+  SoC specific Library containg functions to initialize various SoC components
+
+  Copyright 2017-2020 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SocLib.h>
+#include <Soc.h>
+
+/**
+  Return the input clock frequency to an IP Module.
+  This function reads the RCW bits and calculates the  PLL multiplier/divider
+  values to be applied to various IP modules.
+  If a module is disabled or doesn't exist on platform, then return zero.
+
+  @param[in]  BaseClock  Base clock to which PLL multiplier/divider values is
+                         to be applied.
+  @param[in]  ClockType  Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+                         is to be retrieved.
+  @param[in]  Args       Variable argument list which is parsed based on
+                         ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+                         the second argument will be interpreted as controller
+                         number. e.g. if there are four i2c controllers in SOC,
+                         then this value can be 0, 1, 2, 3
+                         e.g. if ClockType is NXP_CORE_CLOCK, then second
+                         argument is interpreted as cluster number and third
+                         argument is interpreted as core number (within the
+                         cluster)
+
+  @return                Actual Clock Frequency. Return value 0 should be
+                         interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+  IN  UINT64        BaseClock,
+  IN  NXP_IP_CLOCK  ClockType,
+  IN  VA_LIST       Args
+  )
+{
+  LS1046A_DEVICE_CONFIG  *Dcfg;
+  UINT32                 RcwSr;
+  UINT64                 ReturnValue;
+
+  ReturnValue = 0;
+  Dcfg = (LS1046A_DEVICE_CONFIG  *)LS1046A_DCFG_ADDRESS;
+
+  switch (ClockType) {
+  case NXP_UART_CLOCK:
+  case NXP_I2C_CLOCK:
+    RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+    ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+    ReturnValue >>= 1; // 1/2 Platform Clock
+    break;
+  default:
+    break;
+  }
+
+  return ReturnValue;
+}
+
+/**
+  Function to initialize SoC specific constructs
+ **/
+VOID
+SocInit (
+  VOID
+  )
+{
+  ChassisInit ();
+
+  return;
+}
-- 
2.17.1

[PATCH edk2-platforms 3/5] Platform/NXP/LS1046AFRWY: Add ArmPlatformLib

[Pankaj Bansal]

From: Pankaj Bansal <pankaj.bansal@nxp.com>

Add ArmPlatformLib for LS1046AFRWY platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf          | 38 ++++++++
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c            | 96 ++++++++++++++++++++
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c         | 28 ++++++
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S | 45 +++++++++
 4 files changed, 207 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index 000000000000..e6b6fb4d7e88
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,38 @@
+#/* @file
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = PlatformLib
+  FILE_GUID                      = c61c8a13-36a0-46f4-a3bc-7bab5a55db81
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  ArmPlatformLibMem.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index 000000000000..f59e7aa556a3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,96 @@
+/** @file
+*
+*  Copyright 2019-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (UINT64)0xFFFFFFFF
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  //TODO: Implement me
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  if (ArmIsMpCore()) {
+    *CoreCount    = sizeof(mLS1046aMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+    *ArmCoreTable = mLS1046aMpCoreInfoTable;
+    return EFI_SUCCESS;
+  } else {
+    return EFI_UNSUPPORTED;
+  }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  if (ArmIsMpCore()) {
+    *PpiListSize = sizeof(gPlatformPpiTable);
+    *PpiList = gPlatformPpiTable;
+  } else {
+    *PpiListSize = 0;
+    *PpiList = NULL;
+  }
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
new file mode 100644
index 000000000000..24d949369b98
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -0,0 +1,28 @@
+/** @file
+*
+*  Copyright 2019-2020 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ASSERT(0);
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 000000000000..b7c6dbdc2e61
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,45 @@
+//
+//  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #6
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32  (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+  cmp   w0, w1
+  mov   x0, #1
+  mov   x1, #0
+  csel  x0, x0, x1, eq
+  ret
-- 
2.17.1

[PATCH edk2-platforms 4/5] Platform/NXP: Add LS1046AFRWY Platform

[Pankaj Bansal]

From: Pankaj Bansal <pankaj.bansal@nxp.com>

LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.

Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Co-authored-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec                         |  23 +++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc                         |  46 ++++++
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf                         | 168 ++++++++++++++++++++
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf  |   4 +
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c    |  53 +++++-
 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c |  50 +++++-
 6 files changed, 342 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
new file mode 100644
index 000000000000..a693d8262444
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
@@ -0,0 +1,23 @@
+#  LS1046aFrwyPkg.dec
+#  LS1046a board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  PACKAGE_NAME                   = LS1046aFrwyPkg
+  PACKAGE_GUID                   = 3547d88c-62c2-4fb2-a11b-80245f80928f
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
new file mode 100644
index 000000000000..2e7d7da6db3a
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -0,0 +1,46 @@
+#  LS1046aFrwyPkg.dsc
+#
+#  LS1046AFRWY Board package.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME                  = LS1046aFrwyPkg
+  PLATFORM_GUID                  = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
+  OUTPUT_DIRECTORY               = Build/LS1046aFrwyPkg
+  FLASH_DEFINITION               = Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+  ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+  RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # Architectural Protocols
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <PcdsFixedAtBuild>
+    gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+  }
+
+ ##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
new file mode 100644
index 000000000000..8da5b57cb49e
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -0,0 +1,168 @@
+#  LS1046aFrwyPkg.fdf
+#
+#  FLASH layout file for LS1046a board.
+#
+#  Copyright 2019-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1046AFRWY_EFI]
+BaseAddress   = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress  #The base address of the FLASH Device.
+Size          = 0x00140000|gArmTokenSpaceGuid.PcdFdSize         #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize     = 0x1000
+NumBlocks     = 0x140
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00140000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid         = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize          = 0x1
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF MdeModulePkg/Universal/Metronome/Metronome.inf
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index e6b6fb4d7e88..8a3e4f0efa74 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -18,10 +18,14 @@
   ArmPlatformPkg/ArmPlatformPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
+  Silicon/NXP/Chassis2/Chassis2.dec
+  Silicon/NXP/LS1046A/LS1046A.dec
+  Silicon/NXP/NxpQoriqLs.dec
 
 [LibraryClasses]
   ArmLib
   DebugLib
+  SocLib
 
 [Sources.common]
   ArmPlatformLib.c
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index f59e7aa556a3..e1f20da09337 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -8,8 +8,10 @@
 
 #include <Library/ArmLib.h>
 #include <Library/ArmPlatformLib.h>
+#include <Library/SocLib.h>
 
 #include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/NxpPlatformGetClock.h>
 
 ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
   {
@@ -38,6 +40,54 @@ ArmPlatformGetBootMode (
   return BOOT_WITH_FULL_CONFIGURATION;
 }
 
+/**
+  Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+  @param[in]  ClockType  Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+                         is to be retrieved.
+  @param[in]  ...        Variable argument list which is parsed based on
+                         ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+                         the second argument will be interpreted as controller
+                         number.
+                         if ClockType is NXP_CORE_CLOCK, then second argument
+                         is interpreted as cluster number and third argument is
+                         interpreted as core number (within the cluster)
+
+  @return                Actual Clock Frequency. Return value 0 should be
+                         interpreted as clock not being provided to IP.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+  IN  UINT32  ClockType,
+  ...
+  )
+{
+  UINT64      Clock;
+  VA_LIST     Args;
+
+  Clock = 0;
+
+  VA_START (Args, ClockType);
+
+  switch (ClockType) {
+  case NXP_SYSTEM_CLOCK:
+    Clock = 100 * 1000 * 1000; // 100 MHz
+    break;
+  case NXP_I2C_CLOCK:
+  case NXP_UART_CLOCK:
+    Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+    Clock = SocGetClock (Clock, ClockType, Args);
+    break;
+  default:
+    break;
+  }
+
+  VA_END (Args);
+
+  return Clock;
+}
+
 /**
   Initialize controllers that must setup in the normal world
 
@@ -50,7 +100,7 @@ ArmPlatformInitialize (
   IN  UINTN                     MpId
   )
 {
-  //TODO: Implement me
+  SocInit ();
 
   return EFI_SUCCESS;
 }
@@ -71,6 +121,7 @@ PrePeiCoreGetMpCoreInfo (
 }
 
 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi = { NxpPlatformGetClock };
 
 EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
   {
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
index 24d949369b98..c770c234546d 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -7,7 +7,13 @@
 **/
 
 #include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
 #include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Soc.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          5
+
 
 /**
   Return the Virtual Memory Map of your platform
@@ -24,5 +30,47 @@ ArmPlatformGetVirtualMemoryMap (
   IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
   )
 {
-  ASSERT(0);
+  UINTN                            Index;
+  ARM_MEMORY_REGION_DESCRIPTOR     *VirtualMemoryTable;
+
+  Index = 0;
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+                                     MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  if (VirtualMemoryTable == NULL) {
+    DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
+    return;
+  }
+
+  VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1046A_DRAM0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1046A_DRAM0_SIZE;
+  VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+  VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM1_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1046A_DRAM1_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1046A_DRAM1_SIZE;
+  VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+  // CCSR Space
+  VirtualMemoryTable[Index].PhysicalBase = LS1046A_CCSR_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1046A_CCSR_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1046A_CCSR_SIZE;
+  VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // QSPI
+  VirtualMemoryTable[Index].PhysicalBase = LS1046A_QSPI0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].VirtualBase  = LS1046A_QSPI0_PHYS_ADDRESS;
+  VirtualMemoryTable[Index].Length       = LS1046A_QSPI0_SIZE;
+  VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // End of Table
+  ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));
+
+  ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  *VirtualMemoryMap = VirtualMemoryTable;
 }
-- 
2.17.1

[PATCH edk2-platforms 5/5] Platform/NXP/LS1046aFrwyPkg: Add VarStore

[Pankaj Bansal]

From: Pankaj Bansal <pankaj.bansal@nxp.com>

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf |  1 +
 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc   | 91 ++++++++++++++++++++
 2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 8da5b57cb49e..24af547729c7 100644
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -48,6 +48,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 ################################################################################
 #
 # FV Section
diff --git a/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
new file mode 100644
index 000000000000..727705feaea1
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2020 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1046aFrwyNv_EFI]
+BaseAddress   = 0x40500000  #The base address of the FLASH device
+Size          = 0x000C0000  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize     = 0x1000
+NumBlocks     = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE                = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE                = 0x00040000
+DEFINE FTW_WORKING_BASE                        = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE                        = 0x00040000
+DEFINE FTW_SPARE_BASE                          = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE                          = 0x00040000
+
+#############################################################################
+# LS1046AFRWY NVRAM Area
+# LS1046AFRWY NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  #     { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: Flash Size : 0x4000000
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"       # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  #     { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  #         0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid         =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
-- 
2.17.1

Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

[Leif Lindholm]

On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
> 
> for LS1043A SOC the DCFG registers are read in big endian format.
> However current Platofmr PLL calculation is being done assuing the

                  Platform?                              assuming

> little endian format.
> 
> Fix the Platform PLL calculation

OK, now I'm confused.
DCFG is read using the DcfgRead32 function, which is supposed to
handle the endianness issue.

Ls1043a builds with
  gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
which means GetMmioOperations() returns the byte-swapping versions.

Please clarify.

/
    Leif

> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
>  Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
> index 97a77d3f5da6..afcd9da34cda 100644
> --- a/Silicon/NXP/LS1043A/Include/Soc.h
> +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> @@ -48,7 +48,7 @@
>  /**
>    Reset Control Word (RCW) Bits
>  **/
> -#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
> +#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
>  
>  typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
>  
> -- 
> 2.17.1
> 

Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

[Pankaj Bansal]

> On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > for LS1043A SOC the DCFG registers are read in big endian format.
> > However current Platofmr PLL calculation is being done assuing the
> 
>                   Platform?                              assuming

yes. typo mistake.

> 
> > little endian format.
> >
> > Fix the Platform PLL calculation
> 
> OK, now I'm confused.
> DCFG is read using the DcfgRead32 function, which is supposed to
> handle the endianness issue.
> 
> Ls1043a builds with
>   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> which means GetMmioOperations() returns the byte-swapping versions.
> 
> Please clarify.

OK. so this might be little confusing, so bear with me.
The reset configuration word (RCW) is 512 bits (1024 bits in LS2088 / LS2160) long and contains all necessary configuration information for
the chip. RCW data is read from external memory (Nor flash or SD/eMMC card or I2c eeprom)  and written to the RCW status registers
(RCWSR) contained in the Device Configuration and Pin Control module (DCSR), after which the device is configured as specified in the RCW.

The PreBoot Loader (PBL) fetches RCW data from the source memory device and writes it to the RCW status registers.
Now the PBL fetches the data from flash in little endian format and writes it to the DCSR registers in little endian format always.
This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).

Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we read the RCWSR registers in big endian fashion.
This causes the bit position to be reversed.

In SOCs where DCSR space is little endian (LS2088 / LX2160), we read the RCWSR registers in little endian fashion.
That is why the bit position is correct.

> 
> /
>     Leif
> 
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> >  Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> b/Silicon/NXP/LS1043A/Include/Soc.h
> > index 97a77d3f5da6..afcd9da34cda 100644
> > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> > @@ -48,7 +48,7 @@
> >  /**
> >    Reset Control Word (RCW) Bits
> >  **/
> > -#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
> > +#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
> >
> >  typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG
> LS1043A_DEVICE_CONFIG;
> >
> > --
> > 2.17.1
> >

Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

[Leif Lindholm]

On Fri, Jun 05, 2020 at 17:18:54 +0000, Pankaj Bansal (OSS) wrote:
> > On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > >
> > > for LS1043A SOC the DCFG registers are read in big endian format.
> > > However current Platofmr PLL calculation is being done assuing the
> > 
> >                   Platform?                              assuming
> 
> yes. typo mistake.
> 
> > 
> > > little endian format.
> > >
> > > Fix the Platform PLL calculation
> > 
> > OK, now I'm confused.
> > DCFG is read using the DcfgRead32 function, which is supposed to
> > handle the endianness issue.
> > 
> > Ls1043a builds with
> >   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> > which means GetMmioOperations() returns the byte-swapping versions.
> > 
> > Please clarify.
> 
> OK. so this might be little confusing, so bear with me.
> The reset configuration word (RCW) is 512 bits (1024 bits in LS2088
> / LS2160) long and contains all necessary configuration information
> for the chip. RCW data is read from external memory (Nor flash or
> SD/eMMC card or I2c eeprom) and written to the RCW status registers
> (RCWSR) contained in the Device Configuration and Pin Control module
> (DCSR), after which the device is configured as specified in the
> RCW.
> 
> The PreBoot Loader (PBL) fetches RCW data from the source memory
> device and writes it to the RCW status registers.
> Now the PBL fetches the data from flash in little endian format and
> writes it to the DCSR registers in little endian format always.
> This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).

This PBL is a ROM executing before the EDK2 code?

> Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we
> read the RCWSR registers in big endian fashion.
> This causes the bit position to be reversed.

I'm still not following.

We've set up this elaborate Rube Goldberg machine to be able to *not*
have to carry separate header files for devices with individual
components with registers that may be big- or little-endian depending
on which SoC/version they are in.

And now we have an implementation that states that its DcfgRead
operations need to happan as big-endian. And the *only* time the Dcfg
registers are accessed, we immediately need to change the header file
to treat it as little-endian?

What is the situation where Dcfg accesses *need* to be big-endian?

Regards,

Leif

> In SOCs where DCSR space is little endian (LS2088 / LX2160), we read
> the RCWSR registers in little endian fashion.
> That is why the bit position is correct.
> 
> > 
> > /
> >     Leif
> > 
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > ---
> > >  Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> > b/Silicon/NXP/LS1043A/Include/Soc.h
> > > index 97a77d3f5da6..afcd9da34cda 100644
> > > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > > +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> > > @@ -48,7 +48,7 @@
> > >  /**
> > >    Reset Control Word (RCW) Bits
> > >  **/
> > > -#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
> > > +#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
> > >
> > >  typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG
> > LS1043A_DEVICE_CONFIG;
> > >
> > > --
> > > 2.17.1
> > >

Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

[Pankaj Bansal]

> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Monday, June 8, 2020 7:52 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Augustine Philips <Augustine.Philips@arm.com>; Ard
> Biesheuvel <ard.biesheuvel@linaro.org>; Arokia Samy
> <arokia.samy@puresoftware.com>; kuldip dwivedi
> <kuldip.dwivedi@puresoftware.com>
> Subject: Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform
> PLL calculation
> 
> On Fri, Jun 05, 2020 at 17:18:54 +0000, Pankaj Bansal (OSS) wrote:
> > > On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> > > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > >
> > > > for LS1043A SOC the DCFG registers are read in big endian format.
> > > > However current Platofmr PLL calculation is being done assuing the
> > >
> > >                   Platform?                              assuming
> >
> > yes. typo mistake.
> >
> > >
> > > > little endian format.
> > > >
> > > > Fix the Platform PLL calculation
> > >
> > > OK, now I'm confused.
> > > DCFG is read using the DcfgRead32 function, which is supposed to
> > > handle the endianness issue.
> > >
> > > Ls1043a builds with
> > >   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> > > which means GetMmioOperations() returns the byte-swapping versions.
> > >
> > > Please clarify.
> >
> > OK. so this might be little confusing, so bear with me.
> > The reset configuration word (RCW) is 512 bits (1024 bits in LS2088
> > / LS2160) long and contains all necessary configuration information
> > for the chip. RCW data is read from external memory (Nor flash or
> > SD/eMMC card or I2c eeprom) and written to the RCW status registers
> > (RCWSR) contained in the Device Configuration and Pin Control module
> > (DCSR), after which the device is configured as specified in the
> > RCW.
> >
> > The PreBoot Loader (PBL) fetches RCW data from the source memory
> > device and writes it to the RCW status registers.
> > Now the PBL fetches the data from flash in little endian format and
> > writes it to the DCSR registers in little endian format always.
> > This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).
> 
> This PBL is a ROM executing before the EDK2 code?

Yes

> 
> > Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we
> > read the RCWSR registers in big endian fashion.
> > This causes the bit position to be reversed.
> 
> I'm still not following.
> 
> We've set up this elaborate Rube Goldberg machine to be able to *not*
> have to carry separate header files for devices with individual
> components with registers that may be big- or little-endian depending
> on which SoC/version they are in.
> 
> And now we have an implementation that states that its DcfgRead
> operations need to happan as big-endian. And the *only* time the Dcfg
> registers are accessed, we immediately need to change the header file
> to treat it as little-endian?

The RCW Status registers are a special case and a subset of DCFG address space.
The whole DCFG address space is big endian itself, and should be read as such.

if it makes more sense, then I can swap the RCW status registers after being read from DCFG space.
And I can put the explanation I wrote above in the code where I swap RCW SR registers ?

> 
> What is the situation where Dcfg accesses *need* to be big-endian?

Apart from RCWSR registers the DCFG space contains following registers as well, which we need to access in boot firmware:

- SVR (SOC Version Register)
- to retrieve Core and Cluster Information (which I plan to send shortly)
- To set the ICID of DMA connected devices like USB, SATA, SD/EMMC
- to retrieve the clock frequency of serial flash controller (qspi/flexspi)

> 
> Regards,
> 
> Leif
> 
> > In SOCs where DCSR space is little endian (LS2088 / LX2160), we read
> > the RCWSR registers in little endian fashion.
> > That is why the bit position is correct.
> >
> > >
> > > /
> > >     Leif
> > >
> > > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > > ---
> > > >  Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> > > b/Silicon/NXP/LS1043A/Include/Soc.h
> > > > index 97a77d3f5da6..afcd9da34cda 100644
> > > > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > > > +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> > > > @@ -48,7 +48,7 @@
> > > >  /**
> > > >    Reset Control Word (RCW) Bits
> > > >  **/
> > > > -#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
> > > > +#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
> > > >
> > > >  typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG
> > > LS1043A_DEVICE_CONFIG;
> > > >
> > > > --
> > > > 2.17.1
> > > >

Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

[Leif Lindholm]

Hi Pankaj,

Apologies for delay in responding, this message got lost from my inbox.
On a sidenote, I think this has something to do with the email
moderation. Could you possibly subscribe the @oss.nxp.com address to
the list? You can set it not to deliver email, under
https://edk2.groups.io/g/devel/editsub, but I can't whitelist
addresses that are not subscribed.

On Mon, Jun 08, 2020 at 19:56:35 +0000, Pankaj Bansal (OSS) wrote:
> > > > OK, now I'm confused.
> > > > DCFG is read using the DcfgRead32 function, which is supposed to
> > > > handle the endianness issue.
> > > >
> > > > Ls1043a builds with
> > > >   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> > > > which means GetMmioOperations() returns the byte-swapping versions.
> > > >
> > > > Please clarify.
> > >
> > > OK. so this might be little confusing, so bear with me.
> > > The reset configuration word (RCW) is 512 bits (1024 bits in LS2088
> > > / LS2160) long and contains all necessary configuration information
> > > for the chip. RCW data is read from external memory (Nor flash or
> > > SD/eMMC card or I2c eeprom) and written to the RCW status registers
> > > (RCWSR) contained in the Device Configuration and Pin Control module
> > > (DCSR), after which the device is configured as specified in the
> > > RCW.
> > >
> > > The PreBoot Loader (PBL) fetches RCW data from the source memory
> > > device and writes it to the RCW status registers.
> > > Now the PBL fetches the data from flash in little endian format and
> > > writes it to the DCSR registers in little endian format always.
> > > This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).
> > 
> > This PBL is a ROM executing before the EDK2 code?
> 
> Yes
> 
> > 
> > > Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we
> > > read the RCWSR registers in big endian fashion.
> > > This causes the bit position to be reversed.
> > 
> > I'm still not following.
> > 
> > We've set up this elaborate Rube Goldberg machine to be able to *not*
> > have to carry separate header files for devices with individual
> > components with registers that may be big- or little-endian depending
> > on which SoC/version they are in.
> > 
> > And now we have an implementation that states that its DcfgRead
> > operations need to happan as big-endian. And the *only* time the Dcfg
> > registers are accessed, we immediately need to change the header file
> > to treat it as little-endian?
> 
> The RCW Status registers are a special case and a subset of DCFG
> address space. The whole DCFG address space is big endian itself,
> and should be read as such.

So the RCW status registers are in effect just temporary storage for
data, as opposed to having any effect on the hw? Whereas other parts
of DCFG *do* affect (and reflect) hw, and are big-endian?

If so, ok, I understand. And I think your platform designers owe me
(and you, if so inclined) a beer.

> if it makes more sense, then I can swap the RCW status registers
> after being read from DCFG space.
> And I can put the explanation I wrote above in the code where I swap
> RCW SR registers ?

Yes, I think manually swapping the words make more sense. This is a
*weird* thing - it helps to call it out explicitly rather than try to
make it look normal.

Please do that, and drop the .h change, and I'm happy with that.

> > What is the situation where Dcfg accesses *need* to be big-endian?
> 
> Apart from RCWSR registers the DCFG space contains following
> registers as well, which we need to access in boot firmware:
> 
> - SVR (SOC Version Register)
> - to retrieve Core and Cluster Information (which I plan to send shortly)
> - To set the ICID of DMA connected devices like USB, SATA, SD/EMMC
> - to retrieve the clock frequency of serial flash controller (qspi/flexspi)

Understood - thanks!

/
    Leif

Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform PLL calculation

[Pankaj Bansal]

Hi Leif,

Sorry for late reply.
Actually I had asked the design team to check this point.
I am waiting for their reply.
I will add comments in code based on their reply and send new version.

Regards,
Pankaj Bansal

> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Friday, June 12, 2020 8:41 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Augustine Philips <Augustine.Philips@arm.com>; Ard
> Biesheuvel <ard.biesheuvel@linaro.org>; Arokia Samy
> <arokia.samy@puresoftware.com>; kuldip dwivedi
> <kuldip.dwivedi@puresoftware.com>
> Subject: Re: [PATCH edk2-platforms 1/5] Silicon/NXP/LS1043A: Fix the Platform
> PLL calculation
> 
> Hi Pankaj,
> 
> Apologies for delay in responding, this message got lost from my inbox.
> On a sidenote, I think this has something to do with the email
> moderation. Could you possibly subscribe the @oss.nxp.com address to
> the list? You can set it not to deliver email, under
> https://edk2.groups.io/g/devel/editsub, but I can't whitelist
> addresses that are not subscribed.
> 
> On Mon, Jun 08, 2020 at 19:56:35 +0000, Pankaj Bansal (OSS) wrote:
> > > > > OK, now I'm confused.
> > > > > DCFG is read using the DcfgRead32 function, which is supposed to
> > > > > handle the endianness issue.
> > > > >
> > > > > Ls1043a builds with
> > > > >   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> > > > > which means GetMmioOperations() returns the byte-swapping versions.
> > > > >
> > > > > Please clarify.
> > > >
> > > > OK. so this might be little confusing, so bear with me.
> > > > The reset configuration word (RCW) is 512 bits (1024 bits in LS2088
> > > > / LS2160) long and contains all necessary configuration information
> > > > for the chip. RCW data is read from external memory (Nor flash or
> > > > SD/eMMC card or I2c eeprom) and written to the RCW status registers
> > > > (RCWSR) contained in the Device Configuration and Pin Control module
> > > > (DCSR), after which the device is configured as specified in the
> > > > RCW.
> > > >
> > > > The PreBoot Loader (PBL) fetches RCW data from the source memory
> > > > device and writes it to the RCW status registers.
> > > > Now the PBL fetches the data from flash in little endian format and
> > > > writes it to the DCSR registers in little endian format always.
> > > > This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).
> > >
> > > This PBL is a ROM executing before the EDK2 code?
> >
> > Yes
> >
> > >
> > > > Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we
> > > > read the RCWSR registers in big endian fashion.
> > > > This causes the bit position to be reversed.
> > >
> > > I'm still not following.
> > >
> > > We've set up this elaborate Rube Goldberg machine to be able to *not*
> > > have to carry separate header files for devices with individual
> > > components with registers that may be big- or little-endian depending
> > > on which SoC/version they are in.
> > >
> > > And now we have an implementation that states that its DcfgRead
> > > operations need to happan as big-endian. And the *only* time the Dcfg
> > > registers are accessed, we immediately need to change the header file
> > > to treat it as little-endian?
> >
> > The RCW Status registers are a special case and a subset of DCFG
> > address space. The whole DCFG address space is big endian itself,
> > and should be read as such.
> 
> So the RCW status registers are in effect just temporary storage for
> data, as opposed to having any effect on the hw? Whereas other parts
> of DCFG *do* affect (and reflect) hw, and are big-endian?
> 
> If so, ok, I understand. And I think your platform designers owe me
> (and you, if so inclined) a beer.
> 
> > if it makes more sense, then I can swap the RCW status registers
> > after being read from DCFG space.
> > And I can put the explanation I wrote above in the code where I swap
> > RCW SR registers ?
> 
> Yes, I think manually swapping the words make more sense. This is a
> *weird* thing - it helps to call it out explicitly rather than try to
> make it look normal.
> 
> Please do that, and drop the .h change, and I'm happy with that.
> 
> > > What is the situation where Dcfg accesses *need* to be big-endian?
> >
> > Apart from RCWSR registers the DCFG space contains following
> > registers as well, which we need to access in boot firmware:
> >
> > - SVR (SOC Version Register)
> > - to retrieve Core and Cluster Information (which I plan to send shortly)
> > - To set the ICID of DMA connected devices like USB, SATA, SD/EMMC
> > - to retrieve the clock frequency of serial flash controller (qspi/flexspi)
> 
> Understood - thanks!
> 
> /
>     Leif