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Tue, 16 Jun 2020 08:19:51 -0700 (PDT) Date: Tue, 16 Jun 2020 16:19:49 +0100 From: "Leif Lindholm" To: Wasim Khan Cc: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, Wasim Khan Subject: Re: [PATCH edk2-platforms 1/1] Silicon/NXP: LX2160A: Add SerDes Support Message-ID: <20200616151949.GG6739@vanye> References: <1591736934-7745-1-git-send-email-wasim.khan@oss.nxp.com> <1591736934-7745-2-git-send-email-wasim.khan@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <1591736934-7745-2-git-send-email-wasim.khan@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jun 10, 2020 at 02:38:54 +0530, Wasim Khan wrote: > From: Wasim Khan > > Based on SerDes protocol value in reset configuration word (RCW) > different IP blocks gets enabled in HW. > Add SoC specific SerDes configuration for LX2160A, which can be > used by different IPs to know the enabled interfaces and perform > the required initialization. > > Signed-off-by: Wasim Khan > --- > Silicon/NXP/LX2160A/LX2160A.dsc.inc | 2 + > Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf | 6 + > Silicon/NXP/LX2160A/Include/SocSerDes.h | 74 +++++++ > Silicon/NXP/LX2160A/Library/SocLib/SerDes.c | 211 ++++++++++++++++++++ > 4 files changed, 293 insertions(+) > > diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/LX2160A/LX2160A.dsc.inc > index af22b4dd973c..fe8ed402fc4e 100644 > --- a/Silicon/NXP/LX2160A/LX2160A.dsc.inc > +++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc > @@ -15,6 +15,7 @@ [LibraryClasses.common] > PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf > SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf > PL011UartClockLib|Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf > + SerDesHelperLib|Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf > > ################################################################################ > # > @@ -32,6 +33,7 @@ [PcdsFixedAtBuild.common] > gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A0000 > gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2390000 > gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|91 > + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes|0x8 > > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C0000 > diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf > index 421072b88019..54bcb82e6877 100644 > --- a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf > +++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf > @@ -22,6 +22,12 @@ [Packages] > [LibraryClasses] > ChassisLib > DebugLib > + PcdLib > + SerDesHelperLib > > [Sources.common] > + SerDes.c > SocLib.c > + > +[FixedPcd] > + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes > diff --git a/Silicon/NXP/LX2160A/Include/SocSerDes.h b/Silicon/NXP/LX2160A/Include/SocSerDes.h > new file mode 100644 > index 000000000000..02000622d89a > --- /dev/null > +++ b/Silicon/NXP/LX2160A/Include/SocSerDes.h > @@ -0,0 +1,74 @@ > +/** SocSerDes.h > + SoC Specific header file for SerDes > + > + Copyright 2017-2020 NXP > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef SOC_SERDES_H > +#define SOC_SERDES_H > + > +typedef enum { > + NONE = 0, > + PCIE1, > + PCIE2, > + PCIE3, > + PCIE4, > + PCIE5, > + PCIE6, > + SATA1, > + SATA2, > + SATA3, > + SATA4, > + XFI1, > + XFI2, > + XFI3, > + XFI4, > + XFI5, > + XFI6, > + XFI7, > + XFI8, > + XFI9, > + XFI10, > + XFI11, > + XFI12, > + XFI13, > + XFI14, > + SGMII1, > + SGMII2, > + SGMII3, > + SGMII4, > + SGMII5, > + SGMII6, > + SGMII7, > + SGMII8, > + SGMII9, > + SGMII10, > + SGMII11, > + SGMII12, > + SGMII13, > + SGMII14, > + SGMII15, > + SGMII16, > + SGMII17, > + SGMII18, > + GE100_1, > + GE100_2, > + GE50_1, > + GE50_2, > + GE40_1, > + GE40_2, > + GE25_1, > + GE25_2, > + GE25_3, > + GE25_4, > + GE25_5, > + GE25_6, > + GE25_7, > + GE25_8, > + GE25_9, > + GE25_10, > + SERDES_PROTOCOL_COUNT > +} SERDES_PROTOCOL; > +#endif > diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SerDes.c b/Silicon/NXP/LX2160A/Library/SocLib/SerDes.c > new file mode 100644 > index 000000000000..58f2b3df3600 > --- /dev/null > +++ b/Silicon/NXP/LX2160A/Library/SocLib/SerDes.c > @@ -0,0 +1,211 @@ > +/** SerDes.c > + Provides SoC specific SerDes interface > + > + Copyright 2017-2020 NXP > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +// SerDes Protocol Mask and Shift in Reset Configuration Word (RCW) Status Register > +#define SERDES1_PROTOCOL_MASK 0x001f0000 > +#define SERDES1_PROTOCOL_SHIFT 16 > +#define SERDES2_PROTOCOL_MASK 0x03E00000 > +#define SERDES2_PROTOCOL_SHIFT 21 > +#define SERDES3_PROTOCOL_MASK 0x7C000000 > +#define SERDES3_PROTOCOL_SHIFT 26 > + > +SERDES_CONFIG gSerDes1ConfigTable[] = { Are these intended to be directly externally accessed (as opposed to through gSerDesConfig[])? If not, could they be STATIC? (And if so, they should probably have an 'm' (module) prefix rather than a 'g' (global) one. / Leif > + { 1, { PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, > + { 2, { PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, > + { 3, { PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, > + { 4, { SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3 } }, > + { 5, { XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, PCIE1} }, > + { 6, { SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3 } }, > + { 7, { SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, XFI3 } }, > + { 8, { XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, > + { 9, { SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, PCIE1 } }, > + { 10, { XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, > + { 11, { SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, > + { 12, { SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, > + { 13, { GE100_2, GE100_2, GE100_2, GE100_2, GE100_1, GE100_1, GE100_1, GE100_1 } }, > + { 14, { PCIE2, PCIE2, PCIE2, PCIE2, GE100_1, GE100_1, GE100_1, GE100_1 } }, > + { 15, { PCIE2, PCIE2, PCIE2, PCIE2, GE50_2, GE50_2, GE50_1, GE50_1 } }, > + { 16, { PCIE2, PCIE2, PCIE2, PCIE2, GE25_6, GE25_5, GE50_1, GE50_1 } }, > + { 17, { PCIE2, PCIE2, PCIE2, PCIE2, GE25_6, GE25_5, GE25_4, GE25_3 } }, > + { 18, { XFI10, XFI9, XFI8, XFI7, GE25_6, GE25_5, XFI4, XFI3 } }, > + { 19, { GE40_2, GE40_2, GE40_2, GE40_2, GE25_6, GE25_5, XFI4, XFI3 } }, > + { 20, { GE40_2, GE40_2, GE40_2, GE40_2, GE40_1, GE40_1, GE40_1, GE40_1 } }, > + { 21, { GE25_10, GE25_9, PCIE2, PCIE2, GE25_6, GE25_5, GE25_4, GE25_3 } }, > + { 22, { XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, > + {} > +}; > + > +SERDES_CONFIG gSerDes2ConfigTable[] = { > + { 1, { PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, > + { 2, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, > + { 3, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, > + { 4, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, > + { 5, { PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, > + { 6, { PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, XFI14} }, > + { 7, { PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, XFI14} }, > + { 8, { 0, 0, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14} }, > + { 9, { SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, SGMII14 } }, > + { 10, { SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, PCIE4 } }, > + { 11, { PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, SGMII14 } }, > + { 12, { SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, SATA2 } }, > + { 13, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, > + { 14, { PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, SGMII14 } }, > + {} > +}; > + > +SERDES_CONFIG gSerDes3ConfigTable[] = { > + { 2, { PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, > + { 3, { PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, > + {} > +}; > + > +SERDES_CONFIG *gSerDesConfig[] = { > + gSerDes1ConfigTable, > + gSerDes2ConfigTable, > + gSerDes3ConfigTable > +}; > + > +/** > + Probe all SerDes for lane protocol and execute provided callback function. > + > + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol > + @param Arg Pointer to Arguments to be passed to callback function. > + > +**/ > +VOID > +SerDesProbeLanes ( > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > + IN VOID *Arg > + ) > +{ > + UINT32 SerDes1Protocol; > + UINT32 SerDes2Protocol; > + UINT32 SerDes3Protocol; > + LX2160A_DEVICE_CONFIG *DeviceConfig; > + > + DeviceConfig = (LX2160A_DEVICE_CONFIG *)LX2160A_DCFG_ADDRESS; > + SerDes1Protocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[28]) & SERDES1_PROTOCOL_MASK; > + SerDes1Protocol >>= SERDES1_PROTOCOL_SHIFT; > + SerDes2Protocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[28]) & SERDES2_PROTOCOL_MASK; > + SerDes2Protocol >>= SERDES2_PROTOCOL_SHIFT; > + SerDes3Protocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[28]) & SERDES3_PROTOCOL_MASK; > + SerDes3Protocol >>= SERDES3_PROTOCOL_SHIFT; > + > + // SerDes1 > + SerDesInstanceProbeLanes ( > + SERDES_1, > + SerDes1Protocol, > + FixedPcdGet8 (PcdSerDesLanes), > + SERDES_PROTOCOL_COUNT, > + gSerDesConfig[SERDES_1], > + SerDesLaneProbeCallback, > + Arg > + ); > + > + // SerDes2 > + SerDesInstanceProbeLanes ( > + SERDES_2, > + SerDes2Protocol, > + FixedPcdGet8 (PcdSerDesLanes), > + SERDES_PROTOCOL_COUNT, > + gSerDesConfig[SERDES_2], > + SerDesLaneProbeCallback, > + Arg > + ); > + > + // SerDes3 > + SerDesInstanceProbeLanes ( > + SERDES_3, > + SerDes3Protocol, > + FixedPcdGet8 (PcdSerDesLanes), > + SERDES_PROTOCOL_COUNT, > + gSerDesConfig[SERDES_3], > + SerDesLaneProbeCallback, > + Arg > + ); > +} > + > +/** > + Function to return SerDes protocol map for all SerDes available on board. > + > + @param SerDesProtocolMap Pointer to SerDes protocl map. > + > +**/ > +VOID > +GetSerDesProtocolMap ( > + OUT UINT64 *SerDesProtocolMap > + ) > +{ > + UINT32 SerDes1Protocol; > + UINT32 SerDes2Protocol; > + UINT32 SerDes3Protocol; > + LX2160A_DEVICE_CONFIG *DeviceConfig; > + EFI_STATUS Status; > + > + DeviceConfig = (LX2160A_DEVICE_CONFIG *)LX2160A_DCFG_ADDRESS; > + SerDes1Protocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[28]) & SERDES1_PROTOCOL_MASK; > + SerDes1Protocol >>= SERDES1_PROTOCOL_SHIFT; > + SerDes2Protocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[28]) & SERDES2_PROTOCOL_MASK; > + SerDes2Protocol >>= SERDES2_PROTOCOL_SHIFT; > + SerDes3Protocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[28]) & SERDES3_PROTOCOL_MASK; > + SerDes3Protocol >>= SERDES3_PROTOCOL_SHIFT; > + > + *SerDesProtocolMap = 0; > + > + // SerDes1 > + Status = GetSerDesMap ( > + SERDES_1, > + SerDes1Protocol, > + FixedPcdGet8 (PcdSerDesLanes), > + SERDES_PROTOCOL_COUNT, > + gSerDesConfig[SERDES_1], > + SerDesProtocolMap > + ); > + > + if (Status != EFI_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__)); > + *SerDesProtocolMap = 0; > + } > + > + // SerDes2 > + Status = GetSerDesMap ( > + SERDES_2, > + SerDes2Protocol, > + FixedPcdGet8 (PcdSerDesLanes), > + SERDES_PROTOCOL_COUNT, > + gSerDesConfig[SERDES_2], > + SerDesProtocolMap > + ); > + > + if (Status != EFI_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: failed for SerDes2 \n",__FUNCTION__)); > + *SerDesProtocolMap = 0; > + } > + > + // SerDes3 > + Status = GetSerDesMap ( > + SERDES_3, > + SerDes3Protocol, > + FixedPcdGet8 (PcdSerDesLanes), > + SERDES_PROTOCOL_COUNT, > + gSerDesConfig[SERDES_3], > + SerDesProtocolMap > + ); > + > + if (Status != EFI_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: failed for SerDes3 \n",__FUNCTION__)); > + *SerDesProtocolMap = 0; > + } > +} > -- > 2.7.4 >