From: "Ni, Ray" <ray.ni@intel.com>
To: devel@edk2.groups.io
Cc: Maurice Ma <maurice.ma@intel.com>, Guo Dong <guo.dong@intel.com>,
Benjamin You <benjamin.you@intel.com>
Subject: [PATCH V3 2/2] UefiPayloadPkg/Pci: Use the PCIE Base Addr stored in AcpiBoardInfo HOB
Date: Wed, 17 Jun 2020 16:40:58 +0800 [thread overview]
Message-ID: <20200617084058.196-3-ray.ni@intel.com> (raw)
In-Reply-To: <20200617084058.196-1-ray.ni@intel.com>
Today's UefiPayloadPkg always uses 0xE0000000 as the PCIE base address
and ignores the value set in AcpiBoardInfo HOB created by the boot
loader. This makes the payload binary cannot work in environment
where the PCIE base address set by boot loader doesn't equal to
0xE0000000.
The patch enhances UefiPayloadPkg so that the PCIE base address
set by boot loader in the AcpiBoardInfo HOB is used.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
---
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c | 13 +++-
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf | 3 +-
.../PciSegmentInfoLibAcpiBoardInfo.c | 59 +++++++++++++++++++
.../PciSegmentInfoLibAcpiBoardInfo.inf | 36 +++++++++++
UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 10 ++--
UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 11 ++--
6 files changed, 121 insertions(+), 11 deletions(-)
create mode 100644 UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
create mode 100644 UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
index 28dfc8fc55..a3974dcc02 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
@@ -2,7 +2,7 @@
This driver will report some MMIO/IO resources to dxe core, extract smbios and acpi
tables from bootloader.
- Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -101,6 +101,7 @@ BlDxeEntryPoint (
EFI_HOB_GUID_TYPE *GuidHob;
SYSTEM_TABLE_INFO *SystemTableInfo;
EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo;
+ ACPI_BOARD_INFO *AcpiBoardInfo;
Status = EFI_SUCCESS;
//
@@ -153,6 +154,16 @@ BlDxeEntryPoint (
ASSERT_EFI_ERROR (Status);
}
+ //
+ // Set PcdPciExpressBaseAddress by HOB info
+ //
+ GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
+ if (GuidHob != NULL) {
+ AcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
+ Status = PcdSet64S (PcdPciExpressBaseAddress, AcpiBoardInfo->PcieBaseAddress);
+ ASSERT_EFI_ERROR (Status);
+ }
+
return EFI_SUCCESS;
}
diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
index 4c2b4670af..1371d5eb79 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
@@ -3,7 +3,7 @@
#
# Report some MMIO/IO resources to dxe core, extract smbios and acpi tables
#
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -53,6 +53,7 @@ [Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
[Depex]
TRUE
diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
new file mode 100644
index 0000000000..d37c91cc9f
--- /dev/null
+++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
@@ -0,0 +1,59 @@
+/** @file
+ PCI Segment Information Library that returns one segment whose
+ segment base address is retrieved from AcpiBoardInfo HOB.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Guid/AcpiBoardInfoGuid.h>
+
+#include <Library/HobLib.h>
+#include <Library/PciSegmentInfoLib.h>
+#include <Library/DebugLib.h>
+
+STATIC PCI_SEGMENT_INFO mPciSegment0 = {
+ 0, // Segment number
+ 0, // To be fixed later
+ 0, // Start bus number
+ 255 // End bus number
+};
+
+/**
+ Return an array of PCI_SEGMENT_INFO holding the segment information.
+
+ Note: The returned array/buffer is owned by callee.
+
+ @param Count Return the count of segments.
+
+ @retval A callee owned array holding the segment information.
+**/
+PCI_SEGMENT_INFO *
+EFIAPI
+GetPciSegmentInfo (
+ UINTN *Count
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ ACPI_BOARD_INFO *AcpiBoardInfo;
+
+ ASSERT (Count != NULL);
+ if (Count == NULL) {
+ return NULL;
+ }
+
+ if (mPciSegment0.BaseAddress == 0) {
+ //
+ // Find the acpi board information guid hob
+ //
+ GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
+ ASSERT (GuidHob != NULL);
+
+ AcpiBoardInfo = (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (GuidHob);
+ mPciSegment0.BaseAddress = AcpiBoardInfo->PcieBaseAddress;
+ }
+ *Count = 1;
+ return &mPciSegment0;
+}
diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
new file mode 100644
index 0000000000..ec4dbaaa55
--- /dev/null
+++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
@@ -0,0 +1,36 @@
+## @file
+# PCI Segment Information Library that returns one segment whose
+# segment base address is retrieved from AcpiBoardInfo HOB.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PciSegmentInfoLibAcpiBoardInfo
+ FILE_GUID = 0EA82AA2-6C36-4FD5-BC90-FFA3ECB5E0CE
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentInfoLib | DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+[Sources]
+ PciSegmentInfoLibAcpiBoardInfo.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiPayloadPkg/UefiPayloadPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ HobLib
+ DebugLib
diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
index d52945442e..4ce1b8ef1c 100644
--- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
@@ -3,7 +3,7 @@
#
# Provides drivers and definitions to create uefi payload for bootloaders.
#
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -40,7 +40,7 @@ [Defines]
#
# PCI options
#
- DEFINE PCIE_BASE = 0xE0000000
+ DEFINE PCIE_BASE_SUPPORT = TRUE
#
# Serial port set up
@@ -121,14 +121,15 @@ [LibraryClasses]
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-!if $(PCIE_BASE) == 0
+!if $(PCIE_BASE_SUPPORT) == FALSE
PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
!else
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
!endif
- PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
+ PciSegmentInfoLib|UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -357,6 +358,7 @@ [PcdsDynamicDefault]
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0
################################################################################
#
diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
index 0736cd9954..7388543751 100644
--- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
@@ -3,7 +3,7 @@
#
# Provides drivers and definitions to create uefi payload for bootloaders.
#
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -41,7 +41,7 @@ [Defines]
#
# PCI options
#
- DEFINE PCIE_BASE = 0xE0000000
+ DEFINE PCIE_BASE_SUPPORT = TRUE
#
# Serial port set up
@@ -122,14 +122,15 @@ [LibraryClasses]
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-!if $(PCIE_BASE) == 0
+!if $(PCIE_BASE_SUPPORT) == FALSE
PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
!else
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
!endif
- PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
+ PciSegmentInfoLib|UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -288,7 +289,6 @@ [PcdsFixedAtBuild]
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)
!if $(SOURCE_DEBUG_ENABLE)
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
@@ -359,6 +359,7 @@ [PcdsDynamicDefault]
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0
################################################################################
#
--
2.26.2.windows.1
next prev parent reply other threads:[~2020-06-17 8:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 8:40 [PATCH 0/2] UefiPayloadPkg: Use PCIE base address set by boot loader Ni, Ray
2020-06-17 8:40 ` [PATCH V3 1/2] MdePkg/PciSegmentInfoLib: Add missing EFIAPI to GetPciSegmentInfo() Ni, Ray
2020-06-17 15:18 ` Liming Gao
2020-06-17 8:40 ` Ni, Ray [this message]
2020-06-17 20:52 ` [PATCH V3 2/2] UefiPayloadPkg/Pci: Use the PCIE Base Addr stored in AcpiBoardInfo HOB Guo Dong
2020-06-17 21:09 ` Ma, Maurice
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200617084058.196-3-ray.ni@intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox