From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.groups.io with SMTP id smtpd.web11.4005.1592473899748824983 for ; Thu, 18 Jun 2020 02:51:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=u2UAfJI4; spf=pass (domain: nuviainc.com, ip: 209.85.128.65, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f65.google.com with SMTP id j198so6292788wmj.0 for ; Thu, 18 Jun 2020 02:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=EVIRMQcua34HjJBd48MA+bE0KtIaGaR//3dwyI3fawQ=; b=u2UAfJI4cdJo+DPwzI2cSGeX6iw9OjKBX/s6L7Mbp91RwyrHI5pj7QMZO/bLGLzcOL QxemfEyCivyYjeDHdb9lqnN6/x1fOC3PsA8RXuRKQ7znSw8TBD34IG8ukXyyX2GlfelA iedP7yGLOUWowxPe2pzmsFKfK4E4x1R5wf9yFox+7egMi+YO7ipRCWUW2P2Q6JsOdRNj 8wnCsQJUC9KNIIMZ+QH+JPAL2WdtBnklzb7jV4Jb5NMQTVbB8tLWh5+Hks0DDCP+xTUM t2Gt/TjzDYjwN/bPtdbyO7WSu2hQM1V6EPmkNo4XHRlQ7wRlShTEgeOgGoVRrPJT7yL1 VQOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=EVIRMQcua34HjJBd48MA+bE0KtIaGaR//3dwyI3fawQ=; b=qK0r6nkso79eGG1sSClWTx2ocTE0zUGEw+PvE91L4Y4/ozr7IjHRLBSD8+u2GnZXKX GibyhVHJ/lqmCpgyDDsUTSV7yJpiArFo42ZEddCdtJsb+GLeF08aD4ph2uwYPqULdqQ2 ObVEGYqlI5VmPeFti1Z/Tkl6PioT+Uhyv8FGxgitPRYQ+czpG3sjhFSamRnG4ut1R4ys WRg3ln7hKsd9FgG47Uewqv0kzU6bba7YqgVF6IA+n+d5ydjVgKi0vzAJn4uM4t3YA/tZ qZZVhggTmeugS4n2xK7Yt8D3cPckQ0aaTKFfZyDD3Di7rbFvGo9dBxnvB6qnkbBwlMpj oLjQ== X-Gm-Message-State: AOAM532NCET3PtME4iW76SjZBprGTfLEgeKO0hQLO1qsRgw24K4iQhol KEXZqQ8chMWXrh8YFR+Hps8PRw== X-Google-Smtp-Source: ABdhPJz6E/beI5CXHwpXmUSxiyrerqeNb2Cxyk2qj5Ky52OUDeL2i/rc6CJQzP/WB/bYC/iQPBZvuA== X-Received: by 2002:a7b:c0c8:: with SMTP id s8mr3286796wmh.134.1592473898284; Thu, 18 Jun 2020 02:51:38 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id d9sm2821842wre.28.2020.06.18.02.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 02:51:37 -0700 (PDT) Date: Thu, 18 Jun 2020 10:51:35 +0100 From: "Leif Lindholm" To: Wasim Khan Cc: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, Wasim Khan Subject: Re: [PATCH edk2-platforms 1/7] Platform/NXP: LX2160aRdbPkg: Add PCIe space in VirtualMemoryMap Message-ID: <20200618095135.GU6739@vanye> References: <1591741050-11645-1-git-send-email-wasim.khan@oss.nxp.com> <1591741050-11645-2-git-send-email-wasim.khan@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <1591741050-11645-2-git-send-email-wasim.khan@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jun 10, 2020 at 03:47:24 +0530, Wasim Khan wrote: > From: Wasim Khan > > Add PCIe space in VirtualMemoryMap You appear to be adding six spaces to the memory map, not one. I may know why, but most people do not. Please describe in the commit message what the spaces are and why there's six of them. / Leif > Signed-off-by: Wasim Khan > --- > Silicon/NXP/LX2160A/Include/Soc.h | 8 +++++ > Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 38 +++++++++++++++++++- > 2 files changed, 45 insertions(+), 1 deletion(-) > > diff --git a/Silicon/NXP/LX2160A/Include/Soc.h b/Silicon/NXP/LX2160A/Include/Soc.h > index 6c745d580a6d..7e6359485aaf 100644 > --- a/Silicon/NXP/LX2160A/Include/Soc.h > +++ b/Silicon/NXP/LX2160A/Include/Soc.h > @@ -26,6 +26,14 @@ > #define LX2160A_FSPI0_PHYS_ADDRESS (BASE_512MB) > #define LX2160A_FSPI0_SIZE (SIZE_256MB) > > +#define LX2160A_PCI1_PHYS_ADDRESS 0x8000000000 > +#define LX2160A_PCI2_PHYS_ADDRESS 0x8800000000 > +#define LX2160A_PCI3_PHYS_ADDRESS 0x9000000000 > +#define LX2160A_PCI4_PHYS_ADDRESS 0x9800000000 > +#define LX2160A_PCI5_PHYS_ADDRESS 0xa000000000 > +#define LX2160A_PCI6_PHYS_ADDRESS 0xa800000000 > +#define LX2160A_PCI_SIZE SIZE_32GB > + > #define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS > > // SVR > diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c > index 391dab265ad7..c03bc23f4a1d 100644 > --- a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c > +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c > @@ -12,7 +12,7 @@ > #include > #include > > -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 > > /** > Return the Virtual Memory Map of your platform > @@ -71,6 +71,42 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length = LX2160A_FSPI0_SIZE; > VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > + // PCIe1 > + VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI1_PHYS_ADDRESS; > + VirtualMemoryTable[Index].VirtualBase = LX2160A_PCI1_PHYS_ADDRESS; > + VirtualMemoryTable[Index].Length = LX2160A_PCI_SIZE; > + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // PCIe2 > + VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI2_PHYS_ADDRESS; > + VirtualMemoryTable[Index].VirtualBase = LX2160A_PCI2_PHYS_ADDRESS; > + VirtualMemoryTable[Index].Length = LX2160A_PCI_SIZE; > + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // PCIe3 > + VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI3_PHYS_ADDRESS; > + VirtualMemoryTable[Index].VirtualBase = LX2160A_PCI3_PHYS_ADDRESS; > + VirtualMemoryTable[Index].Length = LX2160A_PCI_SIZE; > + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // PCIe4 > + VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI4_PHYS_ADDRESS; > + VirtualMemoryTable[Index].VirtualBase = LX2160A_PCI4_PHYS_ADDRESS; > + VirtualMemoryTable[Index].Length = LX2160A_PCI_SIZE; > + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // PCIe5 > + VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI5_PHYS_ADDRESS; > + VirtualMemoryTable[Index].VirtualBase = LX2160A_PCI5_PHYS_ADDRESS; > + VirtualMemoryTable[Index].Length = LX2160A_PCI_SIZE; > + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // PCIe6 > + VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI6_PHYS_ADDRESS; > + VirtualMemoryTable[Index].VirtualBase = LX2160A_PCI6_PHYS_ADDRESS; > + VirtualMemoryTable[Index].Length = LX2160A_PCI_SIZE; > + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > // End of Table > ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTOR)); > > -- > 2.7.4 >