From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web12.4279.1592474864697084540 for ; Thu, 18 Jun 2020 03:07:45 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=SWQRAxMn; spf=pass (domain: nuviainc.com, ip: 209.85.128.67, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f67.google.com with SMTP id r9so4584644wmh.2 for ; Thu, 18 Jun 2020 03:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ltdxnC/jtNZcmIecsF6xLHdDxzh5+8vN2kCRJo1p2AE=; b=SWQRAxMnEQPN5kuO7Esbw9sFpLyFD+96Y+Zav015vw+vQHHsh5hAGUqguv7OgPUgnU qTSyKGlT8mn0YOPC2dyrq6w2DsCYDJQujrv25Qdy+orVvK9T5q8tbUx0drZdjo7H/pVL kKOcpJhNhp68pXYBulvjlLU+ASYMwddrKsIOgCJ6MeLEZcpuWYEfChYrhbvdXW7Itc3P QQeT1aZtDjQPIbo9D2iPw4CVaAfvmakN5HP2WURpFmLXUJmc7iimlANnCKBzcG7i3cWW PCNz3/TijAvQft+DNDfb208uuH0D/ouBW8x+7U5KK5ihGFJHizmwJS566aZH+ZEsSj1q rCvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ltdxnC/jtNZcmIecsF6xLHdDxzh5+8vN2kCRJo1p2AE=; b=j/Q/uVVUMTBHx2F+8SvPr2J2uS5sop+rshYQe2Sb9j+yvwEbYviZPyaowd9J0mVXQc 8n5k+qNUH6XskY2joB5+6k2KYxc3fNUKCR5iApVWqbn86LOosNE8C/afVqrxEjl+Y6P6 aHlpkDrqdrQpuRF/AGvOWyunpQVrcF0DadUwyT3wrjebXfqNjqm4gUdXp+Cl8Weq40SL ss2bvbUlYrd4oFj0Gvv7dOTqUgHUOyG8pUey+Z2qIf9AQA5fvQoKVaxPbLeXM5dUHnSs leL+K9H4BZM8CpPon/ph0EqkEgyQQBA2HWyOKa5QwDiZdCSzbOJrod+NX1UVw5Zknb6i eNAw== X-Gm-Message-State: AOAM533MMjXfvqqopLpVn23mepdI3eI+zsCtELZR4dt5fGaHzN0Ahrsx KF+niPNNrxqYK4/2M25sAoWTvA== X-Google-Smtp-Source: ABdhPJxOxF7BTs/PFlt/cy/vAsNF/Q8JbPgxy/iEfUbTJnFq+riQLztIxfOUGz5vzHYBra/ivyJtDA== X-Received: by 2002:a7b:c5d5:: with SMTP id n21mr3219976wmk.106.1592474863230; Thu, 18 Jun 2020 03:07:43 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id u12sm2991016wrq.90.2020.06.18.03.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 03:07:42 -0700 (PDT) Date: Thu, 18 Jun 2020 11:07:40 +0100 From: "Leif Lindholm" To: Wasim Khan Cc: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, Wasim Khan Subject: Re: [PATCH edk2-platforms 2/7] Silicon/NXP: LX2160A: Define PCIe related PCDs Message-ID: <20200618100740.GV6739@vanye> References: <1591741050-11645-1-git-send-email-wasim.khan@oss.nxp.com> <1591741050-11645-3-git-send-email-wasim.khan@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <1591741050-11645-3-git-send-email-wasim.khan@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jun 10, 2020 at 03:47:25 +0530, Wasim Khan wrote: > From: Wasim Khan > > Define PCIe related PCDs for LX2160A. > > Signed-off-by: Wasim Khan > --- > Silicon/NXP/LX2160A/LX2160A.dsc.inc | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/LX2160A/LX2160A.dsc.inc > index fe8ed402fc4e..43e361464c8e 100644 > --- a/Silicon/NXP/LX2160A/LX2160A.dsc.inc > +++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc > @@ -38,6 +38,11 @@ [PcdsFixedAtBuild.common] > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C0000 > > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x8000000000 This is already provided by LX2160A_PCI1_PHYS_ADDRESS in Silicon/NXP/LX2160A/Include/Soc.h, and PCI_SEG0_MMIO_MEMBASE would be better described as an alias of that. Unless the NXP PciHostBridgeLib/PciSegmentLib is intended to be shared with SoCs where these base addresses can be different in different platforms. If so, the PHYS_ADDRESSES would be better defined as derivatives of PcdPciExp1BaseAddr. > + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|6 Is this number possible to be different for different platforms based on the same SoC? / Leif > + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000 > + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC > + > [PcdsFeatureFlag] > gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE > > -- > 2.7.4 >