From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by mx.groups.io with SMTP id smtpd.web10.9468.1592492300659322310 for ; Thu, 18 Jun 2020 07:58:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=raqOJF0l; spf=pass (domain: nuviainc.com, ip: 209.85.128.68, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f68.google.com with SMTP id g21so1556568wmg.0 for ; Thu, 18 Jun 2020 07:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=1acZvZQ4uyQ8kKkgmF7bIkVVYuLmUi3f9i2P48SHPh8=; b=raqOJF0l93YmkJ8xfUAyZ91PLCCeO+Q+7WIyqZ365jXjZ1t/xjSnrrDDkZG7/wzStV Ih+6FX2vQsjCtBjbV+R1lfDsEfOCrt/3ndvPGf9YXyQNA9hZU61k+M+G7y/wrs7xb/gS efTLIGXQzJ5oko4V6B5wDWI7+V+tHlfFgDq3G1V4Pv0Wywzw3lztsvqauCZ+/8U4RxQW pyYkrjplyKfvUXOCuvRB08F5OyLy3osevxYzOTGPY2ABplDND22gWAVXzmBt37UthX8B mvDItJ4RhxNdVE4rqDkAzK7eRUu2B1S/DxqHmTgRVhSJxCQ3AOn4s8BTuvJcOa0ovaO5 PHEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=1acZvZQ4uyQ8kKkgmF7bIkVVYuLmUi3f9i2P48SHPh8=; b=NkxP68+pmMBQFvdBrIi7rsbkD6pjXRQqn6ksWwRR+nNaAUei/7UGDzcveUqV25K6tf t/JDo0Nn4s/UFYbmlFm70dyFgmnhiEzwcdvRcotSnj7V1nPE57GkeCYevIzuXUjQG55J MxI2om+fI/FPtlFivNaYfFNK168S/NEt6joI/4J0Uo38GCt+wYCBjzCxN5IMDnK7S6ix YC+UgPpqakP3RjzTvkRVeKk3bVs4bpxGWNdZBHIed2LFeQLZ+7SEO2T1GGcPsQI//nlE hOSgimB1d7xrrR5ihE37MKG1ViP8uofyYTy5DfWOCie41mfCjNxZHd0BiNdZRf0ITMLv JUEA== X-Gm-Message-State: AOAM531y7K6UyI1wqbFo/i2udC0wqwnLOxI0pltFLttDRGAmN+ansQxg +NYUjX9AmZKXfbL139KJ/iRtZw== X-Google-Smtp-Source: ABdhPJyN1t9KP9tik+/Xk4l1sqCJga/rak7RRxH2UvbRIFuhM6asuPsbYAm/fd6O+brrFDCS1/OMow== X-Received: by 2002:a1c:6887:: with SMTP id d129mr2325967wmc.179.1592492299273; Thu, 18 Jun 2020 07:58:19 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id a16sm3848695wrx.8.2020.06.18.07.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 07:58:18 -0700 (PDT) Date: Thu, 18 Jun 2020 15:58:16 +0100 From: "Leif Lindholm" To: "Wasim Khan (OSS)" Cc: "devel@edk2.groups.io" , Meenakshi Aggarwal , Varun Sethi , "ard.biesheuvel@arm.com" Subject: Re: [PATCH edk2-platforms 2/7] Silicon/NXP: LX2160A: Define PCIe related PCDs Message-ID: <20200618145816.GX6739@vanye> References: <1591741050-11645-1-git-send-email-wasim.khan@oss.nxp.com> <1591741050-11645-3-git-send-email-wasim.khan@oss.nxp.com> <20200618100740.GV6739@vanye> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jun 18, 2020 at 10:33:05 +0000, Wasim Khan (OSS) wrote: > > > > -----Original Message----- > > From: Leif Lindholm > > Sent: Thursday, June 18, 2020 3:38 PM > > To: Wasim Khan (OSS) > > Cc: devel@edk2.groups.io; Meenakshi Aggarwal > > ; Varun Sethi ; > > ard.biesheuvel@arm.com; Wasim Khan > > Subject: Re: [PATCH edk2-platforms 2/7] Silicon/NXP: LX2160A: Define PCIe > > related PCDs > > > > On Wed, Jun 10, 2020 at 03:47:25 +0530, Wasim Khan wrote: > > > From: Wasim Khan > > > > > > Define PCIe related PCDs for LX2160A. > > > > > > Signed-off-by: Wasim Khan > > > --- > > > Silicon/NXP/LX2160A/LX2160A.dsc.inc | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc > > > b/Silicon/NXP/LX2160A/LX2160A.dsc.inc > > > index fe8ed402fc4e..43e361464c8e 100644 > > > --- a/Silicon/NXP/LX2160A/LX2160A.dsc.inc > > > +++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc > > > @@ -38,6 +38,11 @@ [PcdsFixedAtBuild.common] > > > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 > > > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C0000 > > > > > > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x8000000000 > > > > This is already provided by LX2160A_PCI1_PHYS_ADDRESS in > > Silicon/NXP/LX2160A/Include/Soc.h, and PCI_SEG0_MMIO_MEMBASE would be > > better described as an alias of that. Unless the NXP > > PciHostBridgeLib/PciSegmentLib is intended to be shared with SoCs where these > > base addresses can be different in different platforms. > > Yes, PciHostBridgeLib/PciSegmentLib are shared with different SoC > with different base address and number of PCIe controllers. Yes. What I meant was whether the base address could change for the SoC depending on which platform it is integrated in? > > If so, the PHYS_ADDRESSES would be better defined as derivatives of > > PcdPciExp1BaseAddr. > > OK, I will use PcdPciExp1BaseAddr and PcdNumPciController for PHYS_ADDRESSES > > > > > > + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|6 > > > > Is this number possible to be different for different platforms based on the same > > SoC? > > This is the total number of PCIe controller on a SoC (for LS1043 its > 3, for LX2160 its 6) > A platform may use few of them based on the RCW (For Ex: > LX2160aRdbPkg has only PEX3 and PEX5 . LX2160aQdsPkg may have all 6 > controller enabled). OK, then the use of the Pcd is definitely the right way to go, but yes, please do as you suggest above to avoid multiple (and potentially conflicting) definitions for the same address. Regards, Leif