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dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=amd.com; Received: from SN1PR12MB2352.namprd12.prod.outlook.com (2603:10b6:802:25::13) by SN1PR12MB2573.namprd12.prod.outlook.com (2603:10b6:802:2b::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22; Thu, 18 Jun 2020 15:23:04 +0000 Received: from SN1PR12MB2352.namprd12.prod.outlook.com ([fe80::156e:ce6d:a148:274e]) by SN1PR12MB2352.namprd12.prod.outlook.com ([fe80::156e:ce6d:a148:274e%7]) with mapi id 15.20.3109.021; Thu, 18 Jun 2020 15:23:04 +0000 From: "Kirkendall, Garrett" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek Subject: [PATCH v2 2/2] UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on AMD Date: Thu, 18 Jun 2020 10:22:45 -0500 Message-Id: <20200618152245.6483-3-Garrett.Kirkendall@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200618152245.6483-1-Garrett.Kirkendall@amd.com> References: <20200618152245.6483-1-Garrett.Kirkendall@amd.com> X-ClientProxiedBy: DM5PR20CA0042.namprd20.prod.outlook.com (2603:10b6:3:13d::28) To SN1PR12MB2352.namprd12.prod.outlook.com (2603:10b6:802:25::13) Return-Path: Garrett.Kirkendall@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from biosdev-01.amd.com (165.204.78.2) by DM5PR20CA0042.namprd20.prod.outlook.com (2603:10b6:3:13d::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22 via Frontend Transport; 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Accessing that register causes and exception on AMD processors. If Execution Disable is supported, but if the processor is an AMD processor, skip manipulating MSR_IA32_MISC_ENABLE[34] XD Disable bit. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Garrett Kirkendall --- Notes: Tested on Intel hardware with Laszlo Ersek's help =20=20=20=20 (1) downloaded two Linux images from provided links. (2) Test using a 32-bit guest on an Intel host (standing in your edk2 t= ree, with the patches applied): =20=20=20=20 $ build -a IA32 -b DEBUG -p OvmfPkg/OvmfPkgIa32.dsc -t GCC5 -D SMM_REQU= IRE =20=20=20=20 $ qemu-system-i386 \ -cpu coreduo,-nx \ -machine q35,smm=3Don,accel=3Dkvm \ -m 4096 \ -smp 4 \ -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ -drive if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild= /OvmfIa32/DEBUG_GCC5/FV/OVMF_CODE.fd \ -drive if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild= /OvmfIa32/DEBUG_GCC5/FV/OVMF_VARS.fd \ -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfedor= a-30-efi-systemd-i686.qcow2 \ -device virtio-scsi-pci,id=3Dscsi0 \ -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 =20=20=20=20 (Once you get a login prompt, feel free to interrupt QEMU with Ctrl-C.) =20=20=20=20 (3) Test using a 64-bit guest on an Intel host: =20=20=20=20 $ build -a IA32 -a X64 -b DEBUG -p OvmfPkg/OvmfPkgIa32X64.dsc -t GCC5 -= D SMM_REQUIRE =20=20=20=20 $ qemu-system-x86_64 \ -cpu host \ -machine q35,smm=3Don,accel=3Dkvm \ -m 4096 \ -smp 4 \ -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ -drive if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild= /Ovmf3264/DEBUG_GCC5/FV/OVMF_CODE.fd \ -drive if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild= /Ovmf3264/DEBUG_GCC5/FV/OVMF_VARS.fd \ -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfedor= a-31-efi-grub2-x86_64.qcow2 \ -device virtio-scsi-pci,id=3Dscsi0 \ -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 =20=20=20=20 Tested on real AMD Hardware UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 3 +++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 9 ++++++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 19 +++++++++++++++++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 20 ++++++++++++++++++-- 4 files changed, 46 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/Pi= SmmCpuDxeSmm/SmmProfileInternal.h index 43f6935cf9dc..993360a8a8c1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -2,6 +2,7 @@ SMM profile internal header file.=0D =0D Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2020, AMD Incorporated. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -13,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D #include =0D =0D #include "SmmProfileArch.h"=0D @@ -99,6 +101,7 @@ extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; extern UINTN gSmiExceptionHandlers[];=0D extern BOOLEAN mXdSupported;=0D X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;=0D +X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;=0D extern UINTN *mPFEntryCount;=0D extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];= =0D extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUN= T];=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index c47b5573e366..d7ed9ab7a770 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -2,7 +2,7 @@ Enable SMM profile.=0D =0D Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
=0D -Copyright (c) 2017, AMD Incorporated. All rights reserved.
=0D +Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -1015,6 +1015,13 @@ CheckFeatureSupported ( mXdSupported =3D FALSE;=0D PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1);=0D }=0D +=0D + if (StandardSignatureIsAuthenticAMD ()) {=0D + //=0D + // AMD processors do not support MSR_IA32_MISC_ENABLE=0D + //=0D + PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1);=0D + }=0D }=0D =0D if (mBtsSupported) {=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index f96de9bdeb43..167f5e14dbd4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ;=0D ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2020, AMD Incorporated. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -59,6 +60,7 @@ global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmbase)=0D extern ASM_PFX(mXdSupported)=0D global ASM_PFX(gPatchXdSupported)=0D +global ASM_PFX(gPatchMsrIa32MiscEnableSupported)=0D extern ASM_PFX(gSmiHandlerIdtr)=0D =0D extern ASM_PFX(mCetSupported)=0D @@ -153,17 +155,30 @@ ASM_PFX(gPatchSmiCr3): ASM_PFX(gPatchXdSupported):=0D cmp al, 0=0D jz @SkipXd=0D +=0D +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit=0D + mov al, strict byte 1 ; source operand may be patched=0D +ASM_PFX(gPatchMsrIa32MiscEnableSupported):=0D + cmp al, 1=0D + jz MsrIa32MiscEnableSupported=0D +=0D +; MSR_IA32_MISC_ENABLE not supported=0D + xor edx, edx=0D + push edx ; don't try to restore the XD Disa= ble bit just before RSM=0D + jmp EnableNxe=0D +=0D ;=0D ; Check XD disable bit=0D ;=0D +MsrIa32MiscEnableSupported:=0D mov ecx, MSR_IA32_MISC_ENABLE=0D rdmsr=0D push edx ; save MSR_IA32_MISC_ENABLE[63-32]= =0D test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]=0D - jz .5=0D + jz EnableNxe=0D and dx, 0xFFFB ; clear XD Disable bit if it is set= =0D wrmsr=0D -.5:=0D +EnableNxe:=0D mov ecx, MSR_EFER=0D rdmsr=0D or ax, MSR_EFER_XD ; enable NXE=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index 8bfba55b5d08..0e154e5db949 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ;=0D ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2020, AMD Incorporated. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -67,6 +68,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase)=0D extern ASM_PFX(mXdSupported)=0D global ASM_PFX(gPatchXdSupported)=0D +global ASM_PFX(gPatchMsrIa32MiscEnableSupported)=0D global ASM_PFX(gPatchSmiStack)=0D global ASM_PFX(gPatchSmiCr3)=0D global ASM_PFX(gPatch5LevelPagingNeeded)=0D @@ -152,18 +154,32 @@ SkipEnable5LevelPaging: ASM_PFX(gPatchXdSupported):=0D cmp al, 0=0D jz @SkipXd=0D +=0D +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit=0D + mov al, strict byte 1 ; source operand may be patched=0D +ASM_PFX(gPatchMsrIa32MiscEnableSupported):=0D + cmp al, 1=0D + jz MsrIa32MiscEnableSupported=0D +=0D +; MSR_IA32_MISC_ENABLE not supported=0D + sub esp, 4=0D + xor rdx, rdx=0D + push rdx ; don't try to restore the XD Disa= ble bit just before RSM=0D + jmp EnableNxe=0D +=0D ;=0D ; Check XD disable bit=0D ;=0D +MsrIa32MiscEnableSupported:=0D mov ecx, MSR_IA32_MISC_ENABLE=0D rdmsr=0D sub esp, 4=0D push rdx ; save MSR_IA32_MISC_ENABLE[63-32]= =0D test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]=0D - jz .0=0D + jz EnableNxe=0D and dx, 0xFFFB ; clear XD Disable bit if it is set= =0D wrmsr=0D -.0:=0D +EnableNxe:=0D mov ecx, MSR_EFER=0D rdmsr=0D or ax, MSR_EFER_XD ; enable NXE=0D --=20 2.27.0