From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.groups.io with SMTP id smtpd.web11.10187.1592494118505929289 for ; Thu, 18 Jun 2020 08:28:38 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=ZwgA1dH/; spf=pass (domain: nuviainc.com, ip: 209.85.128.65, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f65.google.com with SMTP id t194so6107875wmt.4 for ; Thu, 18 Jun 2020 08:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=YC14RWYLPY9CrpaA8kk6fWxSo1RKfbtqghqKi+Sb3u4=; b=ZwgA1dH//jYvauLJNq8ERKDIcoLMqB3AR2VLPVAG+eOeEOIOZbFebk77ab38DlMaOu 6kZw9WDTTVmog/LXddWNQRJT0qSSP7K8V/sro135LSpY9H9bH5HFNpucKHZTBjuKjfus q4uW73s2ZYE8Is2UDzGX90Uvg0hFre8YT/Xhkb3UeQRepqvbVNM4D1cXcbnVe+Q6b0Q/ gM1TkBvLB8+hdC752pC99Elk8YH4bhQeO9KwdxsK1y7Pt2aZ1ABmLC+A92R3HP7dqoqS vutti9krv6klV3pqiVVcIr/BVlcKfUCBvbVdaZTOfFURPttLkYJruOAgnQebqB6lXluU Dv5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=YC14RWYLPY9CrpaA8kk6fWxSo1RKfbtqghqKi+Sb3u4=; b=bIS3FAv9uIdwIh6pKpINhSTsKL1Y5Fpq37D6FRQIS/EeKzRYFLJwNKF1dsgrfWbwFh eWxjgyvCWKWf3xRLLHIVuk3txXGBuKHs9yWQ/erS4zHt+FdKSK8wOdCgQYbMReqWaDKw na8L4ainWGN5KKtcZFeRv0tyA9EdEVSDln0J9vi1kpczRfXW25Of3X2RK2do26fZyUW9 Wul/p5MxwE7f4LbTVa0Kz4tEAJ8mtU/HMKVFJj/IhNNvG4vYSUXh8FGYZMps/r90oUDc 6VjiMSnhrSPcwoS7sa+XxFyaa4fOe1RvfiIHMfPjWzT5K1YTaaIdQpQwVkJNobAHEv93 QYpQ== X-Gm-Message-State: AOAM533IUxCsGDLEcxU3vzS6VqkTJgvL4FEQyWoKgoDbb5qcTPSCsrLw i9rdkEGXG7dthlgWH2X9tJ0ZPg== X-Google-Smtp-Source: ABdhPJy0aaS4FxFW/Ii9eOOWUlXLYjIRLSUNV23gzY100EsiVy2K666aP//CcXt7Go0cQyblWk8VEg== X-Received: by 2002:a1c:790f:: with SMTP id l15mr4531052wme.161.1592494116947; Thu, 18 Jun 2020 08:28:36 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id r12sm4004547wrc.22.2020.06.18.08.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 08:28:36 -0700 (PDT) Date: Thu, 18 Jun 2020 16:28:34 +0100 From: "Leif Lindholm" To: "Wasim Khan (OSS)" Cc: "devel@edk2.groups.io" , Meenakshi Aggarwal , Varun Sethi , "ard.biesheuvel@arm.com" Subject: Re: [PATCH edk2-platforms 2/8] Silicon/NXP: Chassis2: define SVR macros Message-ID: <20200618152834.GA6739@vanye> References: <1591737659-8051-1-git-send-email-wasim.khan@oss.nxp.com> <1591737659-8051-3-git-send-email-wasim.khan@oss.nxp.com> <20200617145408.GQ6739@vanye> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jun 18, 2020 at 09:59:28 +0000, Wasim Khan (OSS) wrote: > > > > -----Original Message----- > > From: Leif Lindholm > > Sent: Wednesday, June 17, 2020 8:24 PM > > To: Wasim Khan (OSS) > > Cc: devel@edk2.groups.io; Meenakshi Aggarwal > > ; Varun Sethi ; > > ard.biesheuvel@arm.com; Wasim Khan > > Subject: Re: [PATCH edk2-platforms 2/8] Silicon/NXP: Chassis2: define SVR > > macros > > > > On Wed, Jun 10, 2020 at 02:50:53 +0530, Wasim Khan wrote: > > > From: Wasim Khan > > > > > > Define macros to retrieve System Version Register(SVR) related > > > information > > > > > > Signed-off-by: Wasim Khan > > > --- > > > Silicon/NXP/Chassis2/Include/Chassis.h | 4 ++++ > > > 1 file changed, 4 insertions(+) > > > > > > diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h > > > b/Silicon/NXP/Chassis2/Include/Chassis.h > > > index e5edd80134a4..7e8bf224884b 100644 > > > --- a/Silicon/NXP/Chassis2/Include/Chassis.h > > > +++ b/Silicon/NXP/Chassis2/Include/Chassis.h > > > @@ -12,6 +12,10 @@ > > > > > > #define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000 > > > > > > +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE) > > > +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) > > > +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf) > > > + > > > /* SMMU Defintions */ > > > #define SMMU_BASE_ADDR 0x09000000 > > > #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) > > > > These macros are identical between Chassis2 and Chassis3V2, and they also look > > like exactly the sort of thing you want identical across different chassis. Is there > > a common header file they can use? > > Thank you Leif for the review. > These MACROS are chassic specific. Upper 24 bits representation is > different in Chassis2 and Chassis3V2 (although not used currently > and masked for SVR calculation but we may need it in future). > SVR representation may further change for future SoC, so we would > like to keep them in chassis specific header file. OK, understood. Yes, this is fine then. For the series: Reviewed-by: Leif Lindholm Pushed as 8dd78ea11a38..14e47144ffc6. / Leif > > > > > > (The set is straightforward, I have no other comments on it.) > > > > / > > Leif > > > > > -- > > > 2.7.4 > > >