From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by mx.groups.io with SMTP id smtpd.web12.10621.1592994358869109624 for ; Wed, 24 Jun 2020 03:25:59 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@9elements.com header.s=google header.b=PQSFVbve; spf=pass (domain: 9elements.com, ip: 209.85.221.65, mailfrom: marcello.bauer@9elements.com) Received: by mail-wr1-f65.google.com with SMTP id j94so1755941wrj.0 for ; Wed, 24 Jun 2020 03:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=9elements.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EITzrJphiXWT9JZ1vo1G8oK+P3gU9TiQ8f+niU+32q0=; b=PQSFVbvezq+ArFBYWgddgQncV6WQgi0+RYMC8DV0senbRRoTl3vMd1duOvwBk8pt2P 96rQN08oCn2ukXvn3EWI0vwpYGdbn6G6u8moFmm931kFrE+xMiItpkdEDgfLFLvdcEZe onZNIQOMDfeoZ2mvEc+dB1U9nhjBPq+rYEuhmtijI/7bVQ82tSjZ8y4nkov6vCfpvQIZ e/PcHvY4xYa8jrlhy5GMQDUB4PpdSNQgPQQeyJv7mtqE4yaaStv1UWaVYFe/6BvFzBe8 uwmN+G92PFLeiH03lNReJneO3p88D5FARb4J833MWJQPfMbjO5PPLKHgyT+VIDp/PHVR X0Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EITzrJphiXWT9JZ1vo1G8oK+P3gU9TiQ8f+niU+32q0=; b=IkYfCTfnKPOtYxNJytw9AXvkoxhePOwYBpMoIRBLWxnXxnhoqlXW3rEsblU4a8VFL9 CWT1UdGbuXwoR5t5DF8ObIQ5Mtt59vtu+2vEmBMAjB0jK1n5x4tUY5kxGjS0ql4oc46z YO0SjPjuNavbK73KcKvfW6R39mGdILRQadF9wpUm8rIFfdkSIrVAC8nqSN5Loc8cEhr5 0etAN1ZA/ENVGvV141dAvPT/ZjFrESnT5wHVewDhRvQYKc4xTKa1W24HpJLU56eyKvpM bWkNtM31s8TLscgIubU6EJFYUwneGPikJ39rYGs1G2e70e9izn99mhSv7UwWvsJ3G0AH W6Ow== X-Gm-Message-State: AOAM530AaB+t3WWBLtvWxuBydMY9ompdUAg01xC7HK9oXrP2NnNaPZnh lPb94CmF8MWCDe37Foo6HxXvdimw74btwA== X-Google-Smtp-Source: ABdhPJzEf5TIwhXkdmYnk7WA+SOvSZJfA8VkEPZWeUJGExDbaTHEaokRk8qwL5HfpoRIZb31avzjhQ== X-Received: by 2002:adf:e908:: with SMTP id f8mr7099578wrm.3.1592994356457; Wed, 24 Jun 2020 03:25:56 -0700 (PDT) Return-Path: Received: from T580.n1ce.space ([2a02:908:e851:d750:6547:7a47:84ac:1330]) by smtp.gmail.com with ESMTPSA id 3sm1771449wmi.45.2020.06.24.03.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jun 2020 03:25:55 -0700 (PDT) From: "Marcello Sylvester Bauer" To: devel@edk2.groups.io Cc: Patrick Rudolph , Christian Walter , Maurice Ma , Nate DeSimone , Star Zeng Subject: [PATCH v1 2/2] UefiPayloadPkg: Runtime MMCONF Date: Wed, 24 Jun 2020 12:25:45 +0200 Message-Id: <20200624102545.21390-3-marcello.bauer@9elements.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200624102545.21390-1-marcello.bauer@9elements.com> References: <20200624102545.21390-1-marcello.bauer@9elements.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Patrick Rudolph * Don't hardcode PCIE_BASE at build time * Support arbitrary platforms with different or even no MMCONF space * Fix buffer overflow accessing MMCONF where less than 256 buses are exposed * Use PciCfg8 for PCI access in PEI, which is only used for debugging Signed-off-by: Patrick Rudolph Signed-off-by: Marcello Sylvester Bauer Cc: Patrick Rudolph Cc: Christian Walter Cc: Maurice Ma Cc: Nate DeSimone Cc: Star Zeng --- UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 1= 6 +- UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 1= 6 +- UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf | 4= 6 + UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf | 4= 2 + UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c | 145= 5 ++++++++++++++++++++ UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c | 130= 2 ++++++++++++++++++ UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni | 1= 7 + UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni | 1= 7 + 8 files changed, 2885 insertions(+), 26 deletions(-) diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc b/UefiPayloadPkg/UefiPay= loadPkgIa32.dsc index c6c47833871b..48b03af6f223 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc @@ -37,11 +37,6 @@ [Defines] #=0D DEFINE MAX_LOGICAL_PROCESSORS =3D 64=0D =0D - #=0D - # PCI options=0D - #=0D - DEFINE PCIE_BASE =3D 0xE0000000=0D -=0D #=0D # Serial port set up=0D #=0D @@ -121,13 +116,9 @@ [LibraryClasses] PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf=0D IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D -!if $(PCIE_BASE) =3D=3D 0=0D - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D -!else=0D - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf=0D - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf=0D -!endif=0D + PciLib|UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.= inf=0D + PciExpressLib|UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib= .inf=0D PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf=0D PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D @@ -216,6 +207,7 @@ [LibraryClasses.IA32.SEC] [LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM]=0D PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf=0D HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf=0D ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf=0D @@ -286,8 +278,6 @@ [PcdsFixedAtBuild] gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE=0D gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 }=0D =0D - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)=0D -=0D !if $(SOURCE_DEBUG_ENABLE)=0D gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2=0D !endif=0D diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/Uefi= PayloadPkgIa32X64.dsc index 5559b1258521..af951ee5aec0 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc @@ -38,11 +38,6 @@ [Defines] #=0D DEFINE MAX_LOGICAL_PROCESSORS =3D 64=0D =0D - #=0D - # PCI options=0D - #=0D - DEFINE PCIE_BASE =3D 0xE0000000=0D -=0D #=0D # Serial port set up=0D #=0D @@ -122,13 +117,9 @@ [LibraryClasses] PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf=0D IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D -!if $(PCIE_BASE) =3D=3D 0=0D - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D -!else=0D - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf=0D - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf=0D -!endif=0D + PciLib|UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.= inf=0D + PciExpressLib|UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib= .inf=0D PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf=0D PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D @@ -217,6 +208,7 @@ [LibraryClasses.IA32.SEC] [LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM]=0D PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf=0D HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf=0D ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf=0D @@ -288,8 +280,6 @@ [PcdsFixedAtBuild] gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE=0D gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 }=0D =0D - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)=0D -=0D !if $(SOURCE_DEBUG_ENABLE)=0D gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2=0D !endif=0D diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf= b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf new file mode 100644 index 000000000000..9f052c0a2e65 --- /dev/null +++ b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf @@ -0,0 +1,46 @@ +## @file=0D +# Instance of PCI Express Library using the 256 MB PCI Express MMIO windo= w.=0D +#=0D +# PCI Express Library that uses the 256 MB PCI Express MMIO window to per= form=0D +# PCI Configuration cycles. Layers on top of an I/O Library instance.=0D +#=0D +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D BasePciExpressLib=0D + MODULE_UNI_FILE =3D BasePciExpressLib.uni=0D + FILE_GUID =3D 287e50f4-a188-4699-b907-3e4080ca5688= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PciExpressLib=0D + CONSTRUCTOR =3D PciExpressLibInitialize=0D +=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D +#=0D +=0D +[Sources]=0D + PciExpressLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + UefiPayloadPkg/UefiPayloadPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + HobLib=0D + IoLib=0D +=0D +[Guids]=0D + gUefiAcpiBoardInfoGuid=0D +=0D +[Pcd]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES=0D +=0D diff --git a/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpre= ss.inf b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.i= nf new file mode 100644 index 000000000000..0858e49a47ae --- /dev/null +++ b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf @@ -0,0 +1,42 @@ +## @file=0D +# Instance of PCI Library based on PCI Express Library.=0D +#=0D +# PCI Library that uses the 256 MB PCI Express MMIO window to perform PCI= =0D +# Configuration cycles. Layers on one PCI Express Library instance.=0D +#=0D +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D BasePciLibPciExpress=0D + MODULE_UNI_FILE =3D BasePciLibPciExpress.uni=0D + FILE_GUID =3D 8987081e-daeb-44a9-8bef-a195b22d9417= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PciLib=0D + CONSTRUCTOR =3D PciLibInitialize=0D +=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[Sources]=0D + PciLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + UefiPayloadPkg/UefiPayloadPkg.dec=0D +=0D +[Guids]=0D + gUefiAcpiBoardInfoGuid=0D +=0D +[LibraryClasses]=0D + PciExpressLib=0D + PciCf8Lib=0D + BaseLib=0D + HobLib=0D diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c b/Uef= iPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c new file mode 100644 index 000000000000..f3b4582d3c47 --- /dev/null +++ b/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c @@ -0,0 +1,1455 @@ +/** @file=0D + Functions in this library instance make use of MMIO functions in IoLib t= o=0D + access memory mapped PCI configuration space.=0D +=0D + All assertions for I/O operations are handled in MMIO functions in the I= oLib=0D + Library.=0D +=0D + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +=0D +STATIC ACPI_BOARD_INFO mBoardInfo;=0D +/**=0D + Assert the validity of a PCI address.=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + Return 0xff on transaction outside of the MMCONF space.=0D +=0D + @param A The address to validate.=0D +=0D +**/=0D +#define ASSERT_INVALID_PCI_ADDRESS(A) \=0D + ASSERT (((A) & ~0xfffffff) =3D=3D 0); \=0D + if ((A) >=3D mBoardInfo.PcieBaseSize) { \=0D + return ~0; \=0D + }=0D +=0D +/**=0D + Registers a PCI device so PCI configuration registers may be accessed af= ter=0D + SetVirtualAddressMap().=0D +=0D + Registers the PCI device specified by Address so all the PCI configurati= on=0D + registers associated with that PCI device may be accessed after SetVirtu= alAddressMap()=0D + is called.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @retval RETURN_SUCCESS The PCI device was registered for runti= me access.=0D + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on=0D + after ExitBootServices().=0D + @retval RETURN_UNSUPPORTED The resources required to access the PC= I device=0D + at runtime could not be mapped.=0D + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to=0D + complete the registration.=0D +=0D +**/=0D +RETURN_STATUS=0D +EFIAPI=0D +PciExpressRegisterForRuntimeAccess (=0D + IN UINTN Address=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return RETURN_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + Performs platform specific initialization required for the CPU to access= =0D + the MMCONF space. This function does not initialize the MMCONF itself.= =0D +=0D + @retval RETURN_SUCCESS The platform specific initialization succee= ded.=0D + @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed.=0D +=0D +**/=0D +RETURN_STATUS=0D +EFIAPI=0D +PciExpressLibInitialize (=0D + VOID=0D + )=0D +{=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D +=0D + //=0D + // Find the acpi board information guid hob=0D + //=0D + GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);=0D + ASSERT (GuidHob !=3D NULL);=0D + if (GuidHob =3D=3D NULL) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + CopyMem (&mBoardInfo, GET_GUID_HOB_DATA (GuidHob), sizeof(mBoardInfo));= =0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Gets the base address of PCI Express.=0D +=0D + This internal functions retrieves PCI Express Base Address via a PCD ent= ry=0D + PcdPciExpressBaseAddress.=0D +=0D + @return The base address of PCI Express.=0D +=0D +**/=0D +VOID*=0D +GetPciExpressBaseAddress (=0D + VOID=0D + )=0D +{=0D + return (VOID*)(UINTN) mBoardInfo.PcieBaseAddress;=0D +}=0D +=0D +/**=0D + Reads an 8-bit PCI configuration register.=0D +=0D + Reads and returns the 8-bit PCI configuration register specified by Addr= ess.=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @return The read value from the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressRead8 (=0D + IN UINTN Address=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);=0D +}=0D +=0D +/**=0D + Writes an 8-bit PCI configuration register.=0D +=0D + Writes the 8-bit PCI configuration register specified by Address with th= e=0D + value specified by Value. Value is returned. This function must guarante= e=0D + that all PCI read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param Value The value to write.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressWrite8 (=0D + IN UINTN Address,=0D + IN UINT8 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value)= ;=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of an 8-bit PCI configuration register with=0D + an 8-bit value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 8-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressOr8 (=0D + IN UINTN Address,=0D + IN UINT8 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D +}=0D +=0D +/**=0D + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit=0D + value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 8-bit PCI configuration register specified by=0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressAnd8 (=0D + IN UINTN Address,=0D + IN UINT8 AndData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData)= ;=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit=0D + value, followed a bitwise OR with another 8-bit value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND between the read result and the value specified by AndData,= =0D + performs a bitwise OR between the result of the AND operation and=0D + the value specified by OrData, and writes the result to the 8-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D + @param OrData The value to OR with the result of the AND operation.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressAndThenOr8 (=0D + IN UINTN Address,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioAndThenOr8 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + AndData,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressBitFieldRead8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldRead8 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit=0D + );=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 8-bit register is returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressBitFieldWrite8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldWrite8 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + Value=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and=0D + writes the result back to the bit field in the 8-bit port.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 8-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized. Extra left bits in OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressBitFieldOr8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldOr8 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise=0D + AND, and writes the result back to the bit field in the 8-bit register.= =0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 8-bit PCI configuration register specified by=0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized. Extra left bits in AndData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressBitFieldAnd8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 AndData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldAnd8 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + AndData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 8-bit port.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 8-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciExpressBitFieldAndThenOr8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldAndThenOr8 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + AndData,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a 16-bit PCI configuration register.=0D +=0D + Reads and returns the 16-bit PCI configuration register specified by Add= ress.=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @return The read value from the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressRead16 (=0D + IN UINTN Address=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);=0D +}=0D +=0D +/**=0D + Writes a 16-bit PCI configuration register.=0D +=0D + Writes the 16-bit PCI configuration register specified by Address with t= he=0D + value specified by Value. Value is returned. This function must guarante= e=0D + that all PCI read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param Value The value to write.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressWrite16 (=0D + IN UINTN Address,=0D + IN UINT16 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value= );=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 16-bit PCI configuration register with=0D + a 16-bit value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 16-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressOr16 (=0D + IN UINTN Address,=0D + IN UINT16 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit=0D + value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 16-bit PCI configuration register specified by= =0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressAnd16 (=0D + IN UINTN Address,=0D + IN UINT16 AndData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData= );=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit=0D + value, followed a bitwise OR with another 16-bit value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData,= =0D + performs a bitwise OR between the result of the AND operation and=0D + the value specified by OrData, and writes the result to the 16-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D + @param OrData The value to OR with the result of the AND operation.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressAndThenOr16 (=0D + IN UINTN Address,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioAndThenOr16 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + AndData,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressBitFieldRead16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldRead16 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit=0D + );=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 16-bit register is returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressBitFieldWrite16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldWrite16 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + Value=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, = and=0D + writes the result back to the bit field in the 16-bit port.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 16-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized. Extra left bits in OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressBitFieldOr16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldOr16 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 16-bit PCI configuration register, performs a bit= wise=0D + AND, and writes the result back to the bit field in the 16-bit register.= =0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 16-bit PCI configuration register specified by= =0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized. Extra left bits in AndData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressBitFieldAnd16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 AndData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldAnd16 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + AndData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 16-bit port.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 16-bit PCI= =0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciExpressBitFieldAndThenOr16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldAndThenOr16 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + AndData,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a 32-bit PCI configuration register.=0D +=0D + Reads and returns the 32-bit PCI configuration register specified by Add= ress.=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @return The read value from the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressRead32 (=0D + IN UINTN Address=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);=0D +}=0D +=0D +/**=0D + Writes a 32-bit PCI configuration register.=0D +=0D + Writes the 32-bit PCI configuration register specified by Address with t= he=0D + value specified by Value. Value is returned. This function must guarante= e=0D + that all PCI read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param Value The value to write.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressWrite32 (=0D + IN UINTN Address,=0D + IN UINT32 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value= );=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 32-bit PCI configuration register with=0D + a 32-bit value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 32-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressOr32 (=0D + IN UINTN Address,=0D + IN UINT32 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit=0D + value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 32-bit PCI configuration register specified by= =0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressAnd32 (=0D + IN UINTN Address,=0D + IN UINT32 AndData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData= );=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit=0D + value, followed a bitwise OR with another 32-bit value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData,= =0D + performs a bitwise OR between the result of the AND operation and=0D + the value specified by OrData, and writes the result to the 32-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D + @param OrData The value to OR with the result of the AND operation.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressAndThenOr32 (=0D + IN UINTN Address,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioAndThenOr32 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + AndData,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressBitFieldRead32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldRead32 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit=0D + );=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 32-bit register is returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressBitFieldWrite32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldWrite32 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + Value=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and=0D + writes the result back to the bit field in the 32-bit port.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 32-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized. Extra left bits in OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressBitFieldOr32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldOr32 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise=0D + AND, and writes the result back to the bit field in the 32-bit register.= =0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 32-bit PCI configuration register specified by= =0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized. Extra left bits in AndData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressBitFieldAnd32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 AndData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldAnd32 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + AndData=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 32-bit port.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 32-bit PCI= =0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciExpressBitFieldAndThenOr32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + )=0D +{=0D + ASSERT_INVALID_PCI_ADDRESS (Address);=0D + return MmioBitFieldAndThenOr32 (=0D + (UINTN) GetPciExpressBaseAddress () + Address,=0D + StartBit,=0D + EndBit,=0D + AndData,=0D + OrData=0D + );=0D +}=0D +=0D +/**=0D + Reads a range of PCI configuration registers into a caller supplied buff= er.=0D +=0D + Reads the range of PCI configuration registers specified by StartAddress= and=0D + Size into the buffer specified by Buffer. This function only allows the = PCI=0D + configuration registers from a single PCI function to be read. Size is=0D + returned. When possible 32-bit PCI configuration read cycles are used to= read=0D + from StartAdress to StartAddress + Size. Due to alignment restrictions, = 8-bit=0D + and 16-bit PCI configuration read cycles may be used at the beginning an= d the=0D + end of the range.=0D +=0D + If StartAddress > 0x0FFFFFFF, then ASSERT().=0D + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D + If Size > 0 and Buffer is NULL, then ASSERT().=0D +=0D + @param StartAddress The starting address that encodes the PCI Bus, Dev= ice,=0D + Function and Register.=0D + @param Size The size in bytes of the transfer.=0D + @param Buffer The pointer to a buffer receiving the data read.=0D +=0D + @return Size read data from StartAddress.=0D +=0D +**/=0D +UINTN=0D +EFIAPI=0D +PciExpressReadBuffer (=0D + IN UINTN StartAddress,=0D + IN UINTN Size,=0D + OUT VOID *Buffer=0D + )=0D +{=0D + UINTN ReturnValue;=0D +=0D + ASSERT_INVALID_PCI_ADDRESS (StartAddress);=0D + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D +=0D + if (Size =3D=3D 0) {=0D + return Size;=0D + }=0D +=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + //=0D + // Save Size for return=0D + //=0D + ReturnValue =3D Size;=0D +=0D + if ((StartAddress & 1) !=3D 0) {=0D + //=0D + // Read a byte if StartAddress is byte aligned=0D + //=0D + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress);=0D + StartAddress +=3D sizeof (UINT8);=0D + Size -=3D sizeof (UINT8);=0D + Buffer =3D (UINT8*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) {=0D + //=0D + // Read a word if StartAddress is word aligned=0D + //=0D + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartA= ddress));=0D +=0D + StartAddress +=3D sizeof (UINT16);=0D + Size -=3D sizeof (UINT16);=0D + Buffer =3D (UINT16*)Buffer + 1;=0D + }=0D +=0D + while (Size >=3D sizeof (UINT32)) {=0D + //=0D + // Read as many double words as possible=0D + //=0D + WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartA= ddress));=0D +=0D + StartAddress +=3D sizeof (UINT32);=0D + Size -=3D sizeof (UINT32);=0D + Buffer =3D (UINT32*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT16)) {=0D + //=0D + // Read the last remaining word if exist=0D + //=0D + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartA= ddress));=0D + StartAddress +=3D sizeof (UINT16);=0D + Size -=3D sizeof (UINT16);=0D + Buffer =3D (UINT16*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT8)) {=0D + //=0D + // Read the last remaining byte if exist=0D + //=0D + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress);=0D + }=0D +=0D + return ReturnValue;=0D +}=0D +=0D +/**=0D + Copies the data in a caller supplied buffer to a specified range of PCI= =0D + configuration space.=0D +=0D + Writes the range of PCI configuration registers specified by StartAddres= s and=0D + Size from the buffer specified by Buffer. This function only allows the = PCI=0D + configuration registers from a single PCI function to be written. Size i= s=0D + returned. When possible 32-bit PCI configuration write cycles are used t= o=0D + write from StartAdress to StartAddress + Size. Due to alignment restrict= ions,=0D + 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning=0D + and the end of the range.=0D +=0D + If StartAddress > 0x0FFFFFFF, then ASSERT().=0D + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D + If Size > 0 and Buffer is NULL, then ASSERT().=0D +=0D + @param StartAddress The starting address that encodes the PCI Bus, Dev= ice,=0D + Function and Register.=0D + @param Size The size in bytes of the transfer.=0D + @param Buffer The pointer to a buffer containing the data to wri= te.=0D +=0D + @return Size written to StartAddress.=0D +=0D +**/=0D +UINTN=0D +EFIAPI=0D +PciExpressWriteBuffer (=0D + IN UINTN StartAddress,=0D + IN UINTN Size,=0D + IN VOID *Buffer=0D + )=0D +{=0D + UINTN ReturnValue;=0D +=0D + ASSERT_INVALID_PCI_ADDRESS (StartAddress);=0D + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D +=0D + if (Size =3D=3D 0) {=0D + return 0;=0D + }=0D +=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + //=0D + // Save Size for return=0D + //=0D + ReturnValue =3D Size;=0D +=0D + if ((StartAddress & 1) !=3D 0) {=0D + //=0D + // Write a byte if StartAddress is byte aligned=0D + //=0D + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);=0D + StartAddress +=3D sizeof (UINT8);=0D + Size -=3D sizeof (UINT8);=0D + Buffer =3D (UINT8*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) {=0D + //=0D + // Write a word if StartAddress is word aligned=0D + //=0D + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));=0D + StartAddress +=3D sizeof (UINT16);=0D + Size -=3D sizeof (UINT16);=0D + Buffer =3D (UINT16*)Buffer + 1;=0D + }=0D +=0D + while (Size >=3D sizeof (UINT32)) {=0D + //=0D + // Write as many double words as possible=0D + //=0D + PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));=0D + StartAddress +=3D sizeof (UINT32);=0D + Size -=3D sizeof (UINT32);=0D + Buffer =3D (UINT32*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT16)) {=0D + //=0D + // Write the last remaining word if exist=0D + //=0D + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));=0D + StartAddress +=3D sizeof (UINT16);=0D + Size -=3D sizeof (UINT16);=0D + Buffer =3D (UINT16*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT8)) {=0D + //=0D + // Write the last remaining byte if exist=0D + //=0D + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);=0D + }=0D +=0D + return ReturnValue;=0D +}=0D diff --git a/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c b/UefiPay= loadPkg/Library/BasePciLibPciExpress/PciLib.c new file mode 100644 index 000000000000..fba5914462c8 --- /dev/null +++ b/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c @@ -0,0 +1,1302 @@ +/** @file=0D + PCI Library functions that use the 256 MB PCI Express MMIO window to per= form PCI=0D + Configuration cycles. Layers on PCI Express Library.=0D +=0D + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +=0D +STATIC BOOLEAN mMMCONFEnabled;=0D +=0D +/**=0D + Registers a PCI device so PCI configuration registers may be accessed af= ter=0D + SetVirtualAddressMap().=0D +=0D + Registers the PCI device specified by Address so all the PCI configurati= on registers=0D + associated with that PCI device may be accessed after SetVirtualAddressM= ap() is called.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @retval RETURN_SUCCESS The PCI device was registered for runti= me access.=0D + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on=0D + after ExitBootServices().=0D + @retval RETURN_UNSUPPORTED The resources required to access the PC= I device=0D + at runtime could not be mapped.=0D + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to=0D + complete the registration.=0D +=0D +**/=0D +RETURN_STATUS=0D +EFIAPI=0D +PciRegisterForRuntimeAccess (=0D + IN UINTN Address=0D + )=0D +{=0D + return PciExpressRegisterForRuntimeAccess (Address);=0D +}=0D +=0D +/**=0D + Performs platform specific initialization required for the CPU to access= =0D + the MMCONF space. This function does not initialize the MMCONF itself.= =0D +=0D + @retval RETURN_SUCCESS The platform specific initialization succee= ded.=0D + @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed.=0D +=0D +**/=0D +RETURN_STATUS=0D +EFIAPI=0D +PciLibInitialize (=0D + VOID=0D + )=0D +{=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + ACPI_BOARD_INFO *AcpiBoardInfoPtr;=0D +=0D + //=0D + // Find the acpi board information guid hob=0D + //=0D + GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);=0D + if (GuidHob =3D=3D NULL) {=0D + return EFI_SUCCESS;=0D + }=0D + AcpiBoardInfoPtr =3D (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);=0D +=0D + mMMCONFEnabled =3D AcpiBoardInfoPtr->PcieBaseAddress !=3D 0 &&=0D + AcpiBoardInfoPtr->PcieBaseSize !=3D 0;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Reads an 8-bit PCI configuration register.=0D +=0D + Reads and returns the 8-bit PCI configuration register specified by Addr= ess.=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @return The read value from the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciRead8 (=0D + IN UINTN Address=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressRead8 (Address);=0D + } else {=0D + return PciCf8Read8 (Address);=0D + }=0D +}=0D +=0D +/**=0D + Writes an 8-bit PCI configuration register.=0D +=0D + Writes the 8-bit PCI configuration register specified by Address with th= e=0D + value specified by Value. Value is returned. This function must guarante= e=0D + that all PCI read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param Value The value to write.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciWrite8 (=0D + IN UINTN Address,=0D + IN UINT8 Value=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressWrite8 (Address, Value);=0D + } else {=0D + return PciCf8Write8 (Address, Value);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of an 8-bit PCI configuration register with=0D + an 8-bit value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 8-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciOr8 (=0D + IN UINTN Address,=0D + IN UINT8 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressOr8 (Address, OrData);=0D + } else {=0D + return PciCf8Or8 (Address, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit=0D + value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 8-bit PCI configuration register specified by=0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciAnd8 (=0D + IN UINTN Address,=0D + IN UINT8 AndData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressAnd8 (Address, AndData);=0D + } else {=0D + return PciCf8And8 (Address, AndData);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit=0D + value, followed a bitwise OR with another 8-bit value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND between the read result and the value specified by AndData,= =0D + performs a bitwise OR between the result of the AND operation and=0D + the value specified by OrData, and writes the result to the 8-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D + @param OrData The value to OR with the result of the AND operation.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciAndThenOr8 (=0D + IN UINTN Address,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressAndThenOr8 (Address, AndData, OrData);=0D + } else {=0D + return PciCf8AndThenOr8 (Address, AndData, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciBitFieldRead8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldRead8 (Address, StartBit, EndBit);=0D + } else {=0D + return PciCf8BitFieldRead8 (Address, StartBit, EndBit);=0D + }=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 8-bit register is returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciBitFieldWrite8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 Value=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);=0D + } else {=0D + return PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and=0D + writes the result back to the bit field in the 8-bit port.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 8-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized. Extra left bits in OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciBitFieldOr8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);=0D + } else {=0D + return PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise=0D + AND, and writes the result back to the bit field in the 8-bit register.= =0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 8-bit PCI configuration register specified by=0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized. Extra left bits in AndData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciBitFieldAnd8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 AndData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);=0D + } else {=0D + return PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 8-bit port.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 8-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciBitFieldAndThenOr8 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndDat= a, OrData);=0D + } else {=0D + return PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, O= rData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a 16-bit PCI configuration register.=0D +=0D + Reads and returns the 16-bit PCI configuration register specified by Add= ress.=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @return The read value from the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciRead16 (=0D + IN UINTN Address=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressRead16 (Address);=0D + } else {=0D + return PciCf8Read16 (Address);=0D + }=0D +}=0D +=0D +/**=0D + Writes a 16-bit PCI configuration register.=0D +=0D + Writes the 16-bit PCI configuration register specified by Address with t= he=0D + value specified by Value. Value is returned. This function must guarante= e=0D + that all PCI read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param Value The value to write.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciWrite16 (=0D + IN UINTN Address,=0D + IN UINT16 Value=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressWrite16 (Address, Value);=0D + } else {=0D + return PciCf8Write16 (Address, Value);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 16-bit PCI configuration register with=0D + a 16-bit value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 16-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciOr16 (=0D + IN UINTN Address,=0D + IN UINT16 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressOr16 (Address, OrData);=0D + } else {=0D + return PciCf8Or16 (Address, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit=0D + value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 16-bit PCI configuration register specified by= =0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciAnd16 (=0D + IN UINTN Address,=0D + IN UINT16 AndData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressAnd16 (Address, AndData);=0D + } else {=0D + return PciCf8And16 (Address, AndData);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit=0D + value, followed a bitwise OR with another 16-bit value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData,= =0D + performs a bitwise OR between the result of the AND operation and=0D + the value specified by OrData, and writes the result to the 16-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D + @param OrData The value to OR with the result of the AND operation.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciAndThenOr16 (=0D + IN UINTN Address,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressAndThenOr16 (Address, AndData, OrData);=0D + } else {=0D + return PciCf8AndThenOr16 (Address, AndData, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciBitFieldRead16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldRead16 (Address, StartBit, EndBit);=0D + } else {=0D + return PciCf8BitFieldRead16 (Address, StartBit, EndBit);=0D + }=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 16-bit register is returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciBitFieldWrite16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 Value=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);=0D + } else {=0D + return PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, = and=0D + writes the result back to the bit field in the 16-bit port.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 16-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized. Extra left bits in OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciBitFieldOr16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);=0D + } else {=0D + return PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in a 16-bit PCI configuration register, performs a bit= wise=0D + AND, and writes the result back to the bit field in the 16-bit register.= =0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 16-bit PCI configuration register specified by= =0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized. Extra left bits in AndData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciBitFieldAnd16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 AndData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);=0D + } else {=0D + return PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 16-bit port.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 16-bit PCI= =0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciBitFieldAndThenOr16 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndDa= ta, OrData);=0D + } else {=0D + return PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, = OrData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a 32-bit PCI configuration register.=0D +=0D + Reads and returns the 32-bit PCI configuration register specified by Add= ress.=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @return The read value from the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciRead32 (=0D + IN UINTN Address=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressRead32 (Address);=0D + } else {=0D + return PciCf8Read32 (Address);=0D + }=0D +}=0D +=0D +/**=0D + Writes a 32-bit PCI configuration register.=0D +=0D + Writes the 32-bit PCI configuration register specified by Address with t= he=0D + value specified by Value. Value is returned. This function must guarante= e=0D + that all PCI read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param Value The value to write.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciWrite32 (=0D + IN UINTN Address,=0D + IN UINT32 Value=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressWrite32 (Address, Value);=0D + } else {=0D + return PciCf8Write32 (Address, Value);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 32-bit PCI configuration register with=0D + a 32-bit value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 32-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciOr32 (=0D + IN UINTN Address,=0D + IN UINT32 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressOr32 (Address, OrData);=0D + } else {=0D + return PciCf8Or32 (Address, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit=0D + value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 32-bit PCI configuration register specified by= =0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciAnd32 (=0D + IN UINTN Address,=0D + IN UINT32 AndData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressAnd32 (Address, AndData);=0D + } else {=0D + return PciCf8And32 (Address, AndData);=0D + }=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit=0D + value, followed a bitwise OR with another 32-bit value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData,= =0D + performs a bitwise OR between the result of the AND operation and=0D + the value specified by OrData, and writes the result to the 32-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D + @param AndData The value to AND with the PCI configuration register.=0D + @param OrData The value to OR with the result of the AND operation.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciAndThenOr32 (=0D + IN UINTN Address,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressAndThenOr32 (Address, AndData, OrData);=0D + } else {=0D + return PciCf8AndThenOr32 (Address, AndData, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciBitFieldRead32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldRead32 (Address, StartBit, EndBit);=0D + } else {=0D + return PciCf8BitFieldRead32 (Address, StartBit, EndBit);=0D + }=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 32-bit register is returned.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciBitFieldWrite32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 Value=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);=0D + } else {=0D + return PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and=0D + writes the result back to the bit field in the 32-bit port.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 32-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized. Extra left bits in OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciBitFieldOr32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);=0D + } else {=0D + return PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise=0D + AND, and writes the result back to the bit field in the 32-bit register.= =0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 32-bit PCI configuration register specified by= =0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized. Extra left bits in AndData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciBitFieldAnd32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 AndData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);=0D + } else {=0D + return PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 32-bit port.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 32-bit PCI= =0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If Address > 0x0FFFFFFF, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciBitFieldAndThenOr32 (=0D + IN UINTN Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndDa= ta, OrData);=0D + } else {=0D + return PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, = OrData);=0D + }=0D +}=0D +=0D +/**=0D + Reads a range of PCI configuration registers into a caller supplied buff= er.=0D +=0D + Reads the range of PCI configuration registers specified by StartAddress= and=0D + Size into the buffer specified by Buffer. This function only allows the = PCI=0D + configuration registers from a single PCI function to be read. Size is=0D + returned. When possible 32-bit PCI configuration read cycles are used to= read=0D + from StartAdress to StartAddress + Size. Due to alignment restrictions, = 8-bit=0D + and 16-bit PCI configuration read cycles may be used at the beginning an= d the=0D + end of the range.=0D +=0D + If StartAddress > 0x0FFFFFFF, then ASSERT().=0D + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D + If Size > 0 and Buffer is NULL, then ASSERT().=0D +=0D + @param StartAddress The starting address that encodes the PCI Bus, Dev= ice,=0D + Function and Register.=0D + @param Size The size in bytes of the transfer.=0D + @param Buffer The pointer to a buffer receiving the data read.=0D +=0D + @return Size=0D +=0D +**/=0D +UINTN=0D +EFIAPI=0D +PciReadBuffer (=0D + IN UINTN StartAddress,=0D + IN UINTN Size,=0D + OUT VOID *Buffer=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressReadBuffer (StartAddress, Size, Buffer);=0D + } else {=0D + return PciCf8ReadBuffer (StartAddress, Size, Buffer);=0D + }=0D +}=0D +=0D +/**=0D + Copies the data in a caller supplied buffer to a specified range of PCI= =0D + configuration space.=0D +=0D + Writes the range of PCI configuration registers specified by StartAddres= s and=0D + Size from the buffer specified by Buffer. This function only allows the = PCI=0D + configuration registers from a single PCI function to be written. Size i= s=0D + returned. When possible 32-bit PCI configuration write cycles are used t= o=0D + write from StartAdress to StartAddress + Size. Due to alignment restrict= ions,=0D + 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning=0D + and the end of the range.=0D +=0D + If StartAddress > 0x0FFFFFFF, then ASSERT().=0D + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D + If Size > 0 and Buffer is NULL, then ASSERT().=0D +=0D + @param StartAddress The starting address that encodes the PCI Bus, Dev= ice,=0D + Function and Register.=0D + @param Size The size in bytes of the transfer.=0D + @param Buffer The pointer to a buffer containing the data to wri= te.=0D +=0D + @return Size written to StartAddress.=0D +=0D +**/=0D +UINTN=0D +EFIAPI=0D +PciWriteBuffer (=0D + IN UINTN StartAddress,=0D + IN UINTN Size,=0D + IN VOID *Buffer=0D + )=0D +{=0D + if (mMMCONFEnabled) {=0D + return PciExpressWriteBuffer (StartAddress, Size, Buffer);=0D + } else {=0D + return PciCf8WriteBuffer (StartAddress, Size, Buffer);=0D + }=0D +}=0D diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni= b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni new file mode 100644 index 000000000000..98010ef2f929 --- /dev/null +++ b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni @@ -0,0 +1,17 @@ +// /** @file=0D +// Instance of PCI Express Library using the 256 MB PCI Express MMIO windo= w.=0D +//=0D +// PCI Express Library that uses the 256 MB PCI Express MMIO window to per= form=0D +// PCI Configuration cycles. Layers on top of an I/O Library instance.=0D +//=0D +// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
= =0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +=0D +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI E= xpress Library using the 256 MB PCI Express MMIO window"=0D +=0D +#string STR_MODULE_DESCRIPTION #language en-US "PCI Express Libra= ry that uses the 256 MB PCI Express MMIO window to perform PCI Configuratio= n cycles. Layers on top of an I/O Library instance."=0D +=0D diff --git a/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpre= ss.uni b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.u= ni new file mode 100644 index 000000000000..ccc456356cf2 --- /dev/null +++ b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni @@ -0,0 +1,17 @@ +// /** @file=0D +// Instance of PCI Library based on PCI Express Library.=0D +//=0D +// PCI Library that uses the 256 MB PCI Express MMIO window to perform PCI= =0D +// Configuration cycles. Layers on one PCI Express Library instance.=0D +//=0D +// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
= =0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +=0D +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI L= ibrary based on PCI Express Library"=0D +=0D +#string STR_MODULE_DESCRIPTION #language en-US "PCI Library that = uses the 256 MB PCI Express MMIO window to perform PCI Configuration cycles= . Layers on an PCI Express Library instance."=0D +=0D --=20 2.25.4