[PATCH edk2-platforms v2 1/6] Silicon/NXP: Add comments explaining RCW bits' parsing

["Pankaj Bansal" <pankaj.bansal@nxp.com>]

From: Pankaj Bansal <pankaj.bansal@nxp.com>

RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.

Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
 Silicon/NXP/LS1043A/Include/Soc.h | 27 +++++++++++++++++++
 Silicon/NXP/LX2160A/Include/Soc.h | 28 +++++++++++++++++++-
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index 21b0dafffe91..c694576ed18d 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -50,6 +50,33 @@
 
 /**
   Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+------------------------------------------------------------------------------------------------
+LE       | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+  Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name  | Description                  | Notes/comments
+----------------------------------------------------------------------
+ 2-6   | SYS_PLL_RAT | System PLL Multiplier/Ratio  | This field selects the platform
+       |             |                              | clock:SYSCLK ratio.
+       |             |                              | 0_0011 3:1
+       |             |                              | 0_0100 4:1
+       |             |                              | 0_1101 13:1
+       |             |                              | 0_1111 15:1
+       |             |                              | 1_0000 16:1
+
+  which is why the RCW bits in RCWSR registers are parsed this way
 **/
 #define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
 
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h b/Silicon/NXP/LX2160A/Include/Soc.h
index d62b8adcdbe7..e8198addc966 100644
--- a/Silicon/NXP/LX2160A/Include/Soc.h
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -36,8 +36,34 @@
 
 /**
   Reset Control Word (RCW) Bits
+
+  RCWSR contains the Reset Configuration Word (RCW) information written with
+  values read from flash memory by the device at power-on reset and read-only
+  upon exiting reset.
+
+  RCW bits in RCWSR registers are same as bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(LSBit 0)| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+------------------------------------------------------------------------------------------------
+LE       | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+  Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name  | Description                  | Notes/comments
+----------------------------------------------------------------------
+ 6-2   | SYS_PLL_RAT | System PLL Multiplier/Ratio  | This field selects the platform
+       |             |                              | clock:SYSCLK ratio.
+       |             |                              | 0_0100 4:1
+       |             |                              | 0_0110 6:1
+       |             |                              | 0_1000 8:1
+       |             |                              | 0_1101 13:1
+       |             |                              | 0_1111 15:1
+
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 6-2
 
 typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
 
-- 
2.17.1