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X-MS-Exchange-AntiSpam-MessageData: 47OpSr1eVnL594zHzXPI4XX4drtB/JEmWx6SQYqJaj+OPA6gjvn6oZNZHJ09RJKdDl17KBzJXOm5F8G541uqZ8WwhUitGyAh9fS24qRrxLemTMmmOG+emhLV5ksNf7z63pCGPIxRumssGj9adU1f6+9bV+SOot5F0+wvQ7YXLIB3LnQGSxIq+9D3WDEDzLrowFxRWe0MsF81SnA5SNYJwomofLdUD+m/KuwJQpVMvh1/IvcHhmoj1tZue4l55QUCgyjcdAS6cTzuh0Me0fiwmIuVSLrJKJRxVpYhZm2cdMaGDq5UCL4e9g4yAbIRg0/kmcjp0XZtkiaOA4ik7/aEMH/FmNwINvKKNJjedxHR+gGO8Wb76QieWY8bHiniKjSPs0d7fH3zLr9lsaqAA/gY+GDbZ8JnruMYarSCqnD2XnCeuXPmzpA9Jx80fGW2TK4HSmLM41bIXJoRfdn0BsRiEWNtqUgGTYiI/uqAnDImTk4EVoHyft9qbCvujgUicLWK X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 83eb9d9e-0af7-4f07-9edb-08d821860d3a X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5933.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2020 08:24:50.7493 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dGy8Tdvw5hA8ASKDdZx+w2JCkbMuD+ENdXe0srcNRl6B8rpS0tGxITVOi7XOxYcd/r8kuVGVY+gpKHUYeKu00g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6782 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Pankaj Bansal For LS1043A SOC the DCFG registers are read in big endian format. After Reading the registers in code we have the registers in Little Endian Bit format i.e. LSBit 0. However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0 format. Currently, we are parsing the RCW bits in LE bit format i.e. LSBit 0. Therefore, Fix the RCW bits' parsing as per MSBit 0. Signed-off-by: Pankaj Bansal --- Silicon/NXP/LS1043A/Include/Soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Includ= e/Soc.h index c694576ed18d..40619536c6fe 100644 --- a/Silicon/NXP/LS1043A/Include/Soc.h +++ b/Silicon/NXP/LS1043A/Include/Soc.h @@ -78,7 +78,7 @@ Bit(s) | Field Name | Description | Not= es/comments =20 which is why the RCW bits in RCWSR registers are parsed this way **/ -#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 +#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 =20 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG; =20 --=20 2.17.1