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Co-authored-by: Pramod Kumar Co-authored-by: Pankaj Bansal Signed-off-by: Pankaj Bansal --- Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec | = 23 +++ Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | = 46 ++++++ Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 1= 68 ++++++++++++++++++++ Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | = 4 + Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c | = 53 +++++- Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | = 49 +++++- 6 files changed, 341 insertions(+), 2 deletions(-) diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec b/Platform/NXP/= LS1046aFrwyPkg/LS1046aFrwyPkg.dec new file mode 100644 index 000000000000..a693d8262444 --- /dev/null +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec @@ -0,0 +1,23 @@ +# LS1046aFrwyPkg.dec +# LS1046a board package. +# +# Copyright 2019-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + PACKAGE_NAME =3D LS1046aFrwyPkg + PACKAGE_GUID =3D 3547d88c-62c2-4fb2-a11b-80245f80928f + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/= LS1046aFrwyPkg/LS1046aFrwyPkg.dsc new file mode 100644 index 000000000000..3f29dadd5d1d --- /dev/null +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc @@ -0,0 +1,46 @@ +# LS1046aFrwyPkg.dsc +# +# LS1046AFRWY Board package. +# +# Copyright 2019-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_NAME =3D LS1046aFrwyPkg + PLATFORM_GUID =3D 79adaa48-5f50-49f0-aa9a-544ac9260ef8 + OUTPUT_DIRECTORY =3D Build/LS1046aFrwyPkg + FLASH_DEFINITION =3D Platform/NXP/LS1046aFrwyPkg/LS1046aFr= wyPkg.fdf + +!include Silicon/NXP/NxpQoriqLs.dsc.inc +!include Silicon/NXP/LS1046A/LS1046A.dsc.inc + +[LibraryClasses.common] + ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPla= tformLib.inf + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal= TimeClockLib.inf + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # Architectural Protocols + # + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + } + +## diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/= LS1046aFrwyPkg/LS1046aFrwyPkg.fdf new file mode 100644 index 000000000000..8da5b57cb49e --- /dev/null +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf @@ -0,0 +1,168 @@ +# LS1046aFrwyPkg.fdf +# +# FLASH layout file for LS1046a board. +# +# Copyright 2019-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.LS1046AFRWY_EFI] +BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. +Size =3D 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x1000 +NumBlocks =3D 0x140 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### +0x00000000|0x00140000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +!include Platform/NXP/FVRules.fdf.inc +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 1037c42b-8452-4c41-aac7-41e6c31468da +BlockSize =3D 0x1 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.i= nf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatform= Lib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib= .inf index de93681708e3..7802696bf39b 100644 --- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -18,10 +18,14 @@ [Packages] ArmPlatformPkg/ArmPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/NXP/Chassis2/Chassis2.dec + Silicon/NXP/LS1046A/LS1046A.dec + Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] ArmLib DebugLib + SocLib =20 [Sources.common] ArmPlatformLib.c diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatform= Lib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c index f59e7aa556a3..e1f20da09337 100644 --- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -8,8 +8,10 @@ =20 #include #include +#include =20 #include +#include =20 ARM_CORE_INFO mLS1046aMpCoreInfoTable[] =3D { { @@ -38,6 +40,54 @@ ArmPlatformGetBootMode ( return BOOT_WITH_FULL_CONFIGURATION; } =20 +/** + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs + + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] ... Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. + if ClockType is NXP_CORE_CLOCK, then second argum= ent + is interpreted as cluster number and third argume= nt is + interpreted as core number (within the cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +EFIAPI +NxpPlatformGetClock( + IN UINT32 ClockType, + ... + ) +{ + UINT64 Clock; + VA_LIST Args; + + Clock =3D 0; + + VA_START (Args, ClockType); + + switch (ClockType) { + case NXP_SYSTEM_CLOCK: + Clock =3D 100 * 1000 * 1000; // 100 MHz + break; + case NXP_I2C_CLOCK: + case NXP_UART_CLOCK: + Clock =3D NxpPlatformGetClock (NXP_SYSTEM_CLOCK); + Clock =3D SocGetClock (Clock, ClockType, Args); + break; + default: + break; + } + + VA_END (Args); + + return Clock; +} + /** Initialize controllers that must setup in the normal world =20 @@ -50,7 +100,7 @@ ArmPlatformInitialize ( IN UINTN MpId ) { - //TODO: Implement me + SocInit (); =20 return EFI_SUCCESS; } @@ -71,6 +121,7 @@ PrePeiCoreGetMpCoreInfo ( } =20 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi =3D { NxpPlatformGetClock = }; =20 EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { { diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatform= LibMem.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLi= bMem.c index 24d949369b98..f712d5931821 100644 --- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.= c +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.= c @@ -7,7 +7,12 @@ **/ =20 #include +#include #include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5 =20 /** Return the Virtual Memory Map of your platform @@ -24,5 +29,47 @@ ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap ) { - ASSERT(0); + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + Index =3D 0; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTO= R) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + if (VirtualMemoryTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION_= _)); + return; + } + + VirtualMemoryTable[Index].PhysicalBase =3D LS1046A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1046A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1046A_DRAM0_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + VirtualMemoryTable[Index].PhysicalBase =3D LS1046A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1046A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1046A_DRAM1_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // CCSR Space + VirtualMemoryTable[Index].PhysicalBase =3D LS1046A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1046A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1046A_CCSR_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QSPI + VirtualMemoryTable[Index].PhysicalBase =3D LS1046A_QSPI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1046A_QSPI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1046A_QSPI0_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // End of Table + ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTO= R)); + + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; } --=20 2.17.1