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From: "Pankaj Bansal" <pankaj.bansal@nxp.com>
To: Leif Lindholm <leif@nuviainc.com>,
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
devel@edk2.groups.io,
Varun Sethi <V.Sethi@nxp.com>,
Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>,
Augustine Philips <Augustine.Philips@arm.com>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Arokia Samy <arokia.samy@puresoftware.com>,
Kuldip Dwivedi <kuldip.dwivedi@puresoftware.com>
Subject: [PATCH edk2-platforms v3 1/5] Silicon/NXP: Add comments explaining RCW bits' parsing
Date: Tue, 7 Jul 2020 23:57:15 -0500
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From: Pankaj Bansal <pankaj.bansal@nxp.com>
RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.
Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Notes:
V3:
- Added Reviewed-by: Leif Lindholm <leif@nuviainc.com>
=20
V2:
- new commit
Silicon/NXP/LS1043A/Include/Soc.h | 27 +++++++++++++++++++
Silicon/NXP/LX2160A/Include/Soc.h | 28 +++++++++++++++++++-
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Includ=
e/Soc.h
index 21b0dafffe91..c694576ed18d 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -50,6 +50,33 @@
=20
/**
Reset Control Word (RCW) Bits
+
+ RCWSR contains the Reset Configuration Word (RCW) information written wi=
th
+ values read from flash memory by the device at power-on reset and read-o=
nly
+ upon exiting reset.
+
+ RCW bits in RCWSR registers are mirror of bit position in Little Endian =
(LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2=
4 25 26 27 28 29 30 31
+--------------------------------------------------------------------------=
----------------------
+LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 =
10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+ Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name | Description | Notes/comments
+----------------------------------------------------------------------
+ 2-6 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects t=
he platform
+ | | | clock:SYSCLK ratio.
+ | | | 0_0011 3:1
+ | | | 0_0100 4:1
+ | | | 0_1101 13:1
+ | | | 0_1111 15:1
+ | | | 1_0000 16:1
+
+ which is why the RCW bits in RCWSR registers are parsed this way
**/
#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
=20
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h b/Silicon/NXP/LX2160A/Includ=
e/Soc.h
index d62b8adcdbe7..e8198addc966 100644
--- a/Silicon/NXP/LX2160A/Include/Soc.h
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -36,8 +36,34 @@
=20
/**
Reset Control Word (RCW) Bits
+
+ RCWSR contains the Reset Configuration Word (RCW) information written wi=
th
+ values read from flash memory by the device at power-on reset and read-o=
nly
+ upon exiting reset.
+
+ RCW bits in RCWSR registers are same as bit position in Little Endian (L=
E)
+
+RCW Bits |
+in RCWSR |
+(LSBit 0)| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 =
10 9 8 7 6 5 4 3 2 1 0
+--------------------------------------------------------------------------=
----------------------
+LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 =
10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+ Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name | Description | Notes/comments
+----------------------------------------------------------------------
+ 6-2 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects t=
he platform
+ | | | clock:SYSCLK ratio.
+ | | | 0_0100 4:1
+ | | | 0_0110 6:1
+ | | | 0_1000 8:1
+ | | | 0_1101 13:1
+ | | | 0_1111 15:1
+
**/
-#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 6-2
=20
typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
=20
--=20
2.17.1