* [PATCH edk2-platforms v3 1/5] Silicon/NXP: Add comments explaining RCW bits' parsing
2020-07-08 4:57 [PATCH edk2-platforms v3 0/5] Add LS1046AFRWY Platform Pankaj Bansal
@ 2020-07-08 4:57 ` Pankaj Bansal
2020-07-08 4:57 ` [PATCH edk2-platforms v3 2/5] Silicon/NXP/LS1043A: Fix the " Pankaj Bansal
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Pankaj Bansal @ 2020-07-08 4:57 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Augustine Philips,
Ard Biesheuvel, Arokia Samy, Kuldip Dwivedi
From: Pankaj Bansal <pankaj.bansal@nxp.com>
RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.
Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Notes:
V3:
- Added Reviewed-by: Leif Lindholm <leif@nuviainc.com>
V2:
- new commit
Silicon/NXP/LS1043A/Include/Soc.h | 27 +++++++++++++++++++
Silicon/NXP/LX2160A/Include/Soc.h | 28 +++++++++++++++++++-
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index 21b0dafffe91..c694576ed18d 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -50,6 +50,33 @@
/**
Reset Control Word (RCW) Bits
+
+ RCWSR contains the Reset Configuration Word (RCW) information written with
+ values read from flash memory by the device at power-on reset and read-only
+ upon exiting reset.
+
+ RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+------------------------------------------------------------------------------------------------
+LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+ Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name | Description | Notes/comments
+----------------------------------------------------------------------
+ 2-6 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
+ | | | clock:SYSCLK ratio.
+ | | | 0_0011 3:1
+ | | | 0_0100 4:1
+ | | | 0_1101 13:1
+ | | | 0_1111 15:1
+ | | | 1_0000 16:1
+
+ which is why the RCW bits in RCWSR registers are parsed this way
**/
#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h b/Silicon/NXP/LX2160A/Include/Soc.h
index d62b8adcdbe7..e8198addc966 100644
--- a/Silicon/NXP/LX2160A/Include/Soc.h
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -36,8 +36,34 @@
/**
Reset Control Word (RCW) Bits
+
+ RCWSR contains the Reset Configuration Word (RCW) information written with
+ values read from flash memory by the device at power-on reset and read-only
+ upon exiting reset.
+
+ RCW bits in RCWSR registers are same as bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(LSBit 0)| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+------------------------------------------------------------------------------------------------
+LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+ Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name | Description | Notes/comments
+----------------------------------------------------------------------
+ 6-2 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
+ | | | clock:SYSCLK ratio.
+ | | | 0_0100 4:1
+ | | | 0_0110 6:1
+ | | | 0_1000 8:1
+ | | | 0_1101 13:1
+ | | | 0_1111 15:1
+
**/
-#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 6-2
typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH edk2-platforms v3 2/5] Silicon/NXP/LS1043A: Fix the RCW bits' parsing
2020-07-08 4:57 [PATCH edk2-platforms v3 0/5] Add LS1046AFRWY Platform Pankaj Bansal
2020-07-08 4:57 ` [PATCH edk2-platforms v3 1/5] Silicon/NXP: Add comments explaining RCW bits' parsing Pankaj Bansal
@ 2020-07-08 4:57 ` Pankaj Bansal
2020-07-08 4:57 ` [PATCH edk2-platforms v3 3/5] Silicon/NXP: Add LS1046A Soc package Pankaj Bansal
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Pankaj Bansal @ 2020-07-08 4:57 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Augustine Philips,
Ard Biesheuvel, Arokia Samy, Kuldip Dwivedi
From: Pankaj Bansal <pankaj.bansal@nxp.com>
For LS1043A SOC the DCFG registers are read in big endian format.
After Reading the registers in code we have the registers in Little
Endian Bit format i.e. LSBit 0.
However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0
format.
Currently, we are parsing the RCW bits in LE bit format i.e. LSBit 0.
Therefore, Fix the RCW bits' parsing as per MSBit 0.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Notes:
V3:
- Added Reviewed-by: Leif Lindholm <leif@nuviainc.com>
V2:
- Changed commit header and description.
- Moved changes in comments to previous commit
Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index c694576ed18d..40619536c6fe 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -78,7 +78,7 @@ Bit(s) | Field Name | Description | Notes/comments
which is why the RCW bits in RCWSR registers are parsed this way
**/
-#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH edk2-platforms v3 3/5] Silicon/NXP: Add LS1046A Soc package
2020-07-08 4:57 [PATCH edk2-platforms v3 0/5] Add LS1046AFRWY Platform Pankaj Bansal
2020-07-08 4:57 ` [PATCH edk2-platforms v3 1/5] Silicon/NXP: Add comments explaining RCW bits' parsing Pankaj Bansal
2020-07-08 4:57 ` [PATCH edk2-platforms v3 2/5] Silicon/NXP/LS1043A: Fix the " Pankaj Bansal
@ 2020-07-08 4:57 ` Pankaj Bansal
2020-07-08 4:57 ` [PATCH edk2-platforms v3 4/5] Platform/NXP: Add LS1046AFRWY Platform Pankaj Bansal
2020-07-08 4:57 ` [PATCH edk2-platforms v3 5/5] Platform/NXP/LS1046aFrwyPkg: Add VarStore Pankaj Bansal
4 siblings, 0 replies; 7+ messages in thread
From: Pankaj Bansal @ 2020-07-08 4:57 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Augustine Philips,
Ard Biesheuvel, Arokia Samy, Kuldip Dwivedi, Vabhav Sharma
From: Pankaj Bansal <pankaj.bansal@nxp.com>
LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.
Co-authored-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Notes:
V3:
- Removed Co-authored-by: Pankaj Bansal <pankaj.bansal@nxp.com>
- Added Reviewed-by: Leif Lindholm <leif@nuviainc.com>
V2:
- No change
Silicon/NXP/LS1046A/LS1046A.dec | 13 +++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 42 +++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 27 +++++
Silicon/NXP/LS1046A/Include/Soc.h | 63 +++++++++++
Silicon/NXP/LS1046A/Include/SocSerDes.h | 33 ++++++
Silicon/NXP/LS1046A/Library/SocLib/SerDes.c | 119 ++++++++++++++++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 78 +++++++++++++
7 files changed, 375 insertions(+)
diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index 000000000000..bf4863c6d89e
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,13 @@
+# LS1046A.dec
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index 000000000000..dbe7f408fce9
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,42 @@
+# LS1046A.dsc
+# LS1046A Soc package.
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+[PcdsFeatureFlag]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+##
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
new file mode 100644
index 000000000000..01ed0f6592d2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+# @file
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/LS1046A/LS1046A.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ChassisLib
+ DebugLib
+
+[Sources.common]
+ SocLib.c
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
new file mode 100644
index 000000000000..84f433d5cb94
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -0,0 +1,63 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include <Chassis.h>
+
+/**
+ Soc Memory Map
+**/
+#define LS1046A_DRAM0_PHYS_ADDRESS (BASE_2GB)
+#define LS1046A_DRAM0_SIZE (SIZE_2GB)
+#define LS1046A_DRAM1_PHYS_ADDRESS (BASE_32GB + BASE_2GB)
+#define LS1046A_DRAM1_SIZE (SIZE_32GB - SIZE_2GB) // 30 GB
+
+#define LS1046A_CCSR_PHYS_ADDRESS (BASE_16MB)
+#define LS1046A_CCSR_SIZE (SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LS1046A_QSPI0_PHYS_ADDRESS (BASE_1GB)
+#define LS1046A_QSPI0_SIZE (SIZE_512MB)
+
+#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+ Reset Control Word (RCW) Bits
+
+ RCWSR contains the Reset Configuration Word (RCW) information written with
+ values read from flash memory by the device at power-on reset and read-only
+ upon exiting reset.
+
+ RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+------------------------------------------------------------------------------------------------
+LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+ Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name | Description | Notes/comments
+----------------------------------------------------------------------
+ 2-6 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
+ | | | clock:SYSCLK ratio.
+ | | | 0_0011 3:1
+ | | | 0_0100 4:1
+ | | | 0_1101 13:1
+ | | | 0_1111 15:1
+ | | | 1_0000 16:1
+
+ which is why the RCW bits in RCWSR registers are parsed this way
+**/
+#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+
+#endif // SOC_H__
diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h
new file mode 100644
index 000000000000..2fc5651c004c
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
@@ -0,0 +1,33 @@
+/** SocSerDes.h
+ SoC Specific header file for SerDes
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef SOC_SERDES_H
+#define SOC_SERDES_H
+
+typedef enum {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ SATA,
+ SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
+ QSGMII_FM1_A,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SERDES_PROTOCOL_COUNT
+} SERDES_PROTOCOL;
+#endif
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SerDes.c b/Silicon/NXP/LS1046A/Library/SocLib/SerDes.c
new file mode 100644
index 000000000000..a50e0b61e19a
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SerDes.c
@@ -0,0 +1,119 @@
+/** SerDes.c
+ Provides SoC specific SerDes interface
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SerDesHelperLib.h>
+#include <SocSerDes.h>
+#include <Soc.h>
+#include <Uefi.h>
+
+// SerDes1 Protocol Mask in Reset Configuration Word (RCW) Status Register
+#define SERDES1_PROTOCOL_MASK 0xffff0000
+
+// SerDes1 Protocol Shift in Reset Configuration Word (RCW) Status Register
+#define SERDES1_PROTOCOL_SHIFT 16
+
+STATIC SERDES_CONFIG mSerDes1ConfigTable[] = {
+ {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
+ {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+ {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
+ {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } },
+ {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } },
+ {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
+ {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+ {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
+ {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
+ {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
+ {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {}
+};
+
+SERDES_CONFIG *gSerDesConfig[] = {
+ mSerDes1ConfigTable
+};
+
+/**
+ Probe all SerDes for lane protocol and execute provided callback function.
+
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+VOID
+SerDesProbeLanes (
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+ UINT32 SerDesProtocol;
+ LS1046A_DEVICE_CONFIG *DeviceConfig;
+
+ DeviceConfig = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
+ SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK;
+ SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT;
+
+ SerDesInstanceProbeLanes (
+ SERDES_1,
+ SerDesProtocol,
+ FixedPcdGet8 (PcdSerDesLanes),
+ SERDES_PROTOCOL_COUNT,
+ gSerDesConfig[SERDES_1],
+ SerDesLaneProbeCallback,
+ Arg
+ );
+}
+
+/**
+ Function to return SerDes protocol map for all SerDes available on board.
+
+ @param SerDesProtocolMap Pointer to SerDes protocl map.
+
+**/
+VOID
+GetSerDesProtocolMap (
+ OUT UINT64 *SerDesProtocolMap
+ )
+{
+ UINT32 SerDesProtocol;
+ LS1046A_DEVICE_CONFIG *DeviceConfig;
+ EFI_STATUS Status;
+
+ *SerDesProtocolMap = 0;
+ DeviceConfig = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
+ SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK;
+ SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT;
+
+ Status = GetSerDesMap (
+ SERDES_1,
+ SerDesProtocol,
+ FixedPcdGet8 (PcdSerDesLanes),
+ SERDES_PROTOCOL_COUNT,
+ gSerDesConfig[SERDES_1],
+ SerDesProtocolMap
+ );
+
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__));
+ *SerDesProtocolMap = 0;
+ }
+}
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
new file mode 100644
index 000000000000..3b15aee6ecae
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -0,0 +1,78 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SocLib.h>
+#include <Soc.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multiplier/divider
+ values to be applied to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multiplier/divider values is
+ to be applied.
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] Args Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN NXP_IP_CLOCK ClockType,
+ IN VA_LIST Args
+ )
+{
+ LS1046A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ case NXP_I2C_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 1; // 1/2 Platform Clock
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Function to initialize SoC specific constructs
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ ChassisInit ();
+
+ return;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH edk2-platforms v3 4/5] Platform/NXP: Add LS1046AFRWY Platform
2020-07-08 4:57 [PATCH edk2-platforms v3 0/5] Add LS1046AFRWY Platform Pankaj Bansal
` (2 preceding siblings ...)
2020-07-08 4:57 ` [PATCH edk2-platforms v3 3/5] Silicon/NXP: Add LS1046A Soc package Pankaj Bansal
@ 2020-07-08 4:57 ` Pankaj Bansal
2020-07-13 16:23 ` Leif Lindholm
2020-07-08 4:57 ` [PATCH edk2-platforms v3 5/5] Platform/NXP/LS1046aFrwyPkg: Add VarStore Pankaj Bansal
4 siblings, 1 reply; 7+ messages in thread
From: Pankaj Bansal @ 2020-07-08 4:57 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Augustine Philips,
Ard Biesheuvel, Arokia Samy, Kuldip Dwivedi, Pramod Kumar
From: Pankaj Bansal <pankaj.bansal@nxp.com>
LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.
Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Notes:
V3:
- Squashed previous commit to this commit
V2:
- No change
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec | 23 +++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 46 ++++++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 168 ++++++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 42 +++++
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 147 +++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 75 +++++++++
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S | 45 ++++++
7 files changed, 546 insertions(+)
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
new file mode 100644
index 000000000000..a693d8262444
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
@@ -0,0 +1,23 @@
+# LS1046aFrwyPkg.dec
+# LS1046a board package.
+#
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ PACKAGE_NAME = LS1046aFrwyPkg
+ PACKAGE_GUID = 3547d88c-62c2-4fb2-a11b-80245f80928f
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
new file mode 100644
index 000000000000..3f29dadd5d1d
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -0,0 +1,46 @@
+# LS1046aFrwyPkg.dsc
+#
+# LS1046AFRWY Board package.
+#
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS1046aFrwyPkg
+ PLATFORM_GUID = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
+ OUTPUT_DIRECTORY = Build/LS1046aFrwyPkg
+ FLASH_DEFINITION = Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+ ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+ RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+ }
+
+##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
new file mode 100644
index 000000000000..8da5b57cb49e
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -0,0 +1,168 @@
+# LS1046aFrwyPkg.fdf
+#
+# FLASH layout file for LS1046a board.
+#
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1046AFRWY_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0x140
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00140000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index 000000000000..7802696bf39b
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,42 @@
+# @file
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = c61c8a13-36a0-46f4-a3bc-7bab5a55db81
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/LS1046A/LS1046A.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ DebugLib
+ SocLib
+
+[Sources.common]
+ ArmPlatformLib.c
+ ArmPlatformLibMem.c
+
+[Sources.AArch64]
+ AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index 000000000000..e1f20da09337
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,147 @@
+/** @file
+*
+* Copyright 2019-2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/SocLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] ... Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number.
+ if ClockType is NXP_CORE_CLOCK, then second argument
+ is interpreted as cluster number and third argument is
+ interpreted as core number (within the cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+ IN UINT32 ClockType,
+ ...
+ )
+{
+ UINT64 Clock;
+ VA_LIST Args;
+
+ Clock = 0;
+
+ VA_START (Args, ClockType);
+
+ switch (ClockType) {
+ case NXP_SYSTEM_CLOCK:
+ Clock = 100 * 1000 * 1000; // 100 MHz
+ break;
+ case NXP_I2C_CLOCK:
+ case NXP_UART_CLOCK:
+ Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
+ break;
+ default:
+ break;
+ }
+
+ VA_END (Args);
+
+ return Clock;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+ in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ if (ArmIsMpCore()) {
+ *CoreCount = sizeof(mLS1046aMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+ *ArmCoreTable = mLS1046aMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi = { NxpPlatformGetClock };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ if (ArmIsMpCore()) {
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+ } else {
+ *PpiListSize = 0;
+ *PpiList = NULL;
+ }
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
new file mode 100644
index 000000000000..f712d5931821
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -0,0 +1,75 @@
+/** @file
+*
+* Copyright 2019-2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Soc.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ if (VirtualMemoryTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
+ return;
+ }
+
+ VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1046A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1046A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1046A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1046A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[Index].PhysicalBase = LS1046A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1046A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1046A_CCSR_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QSPI
+ VirtualMemoryTable[Index].PhysicalBase = LS1046A_QSPI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1046A_QSPI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1046A_QSPI0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));
+
+ ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 000000000000..4f56a1c366ab
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,45 @@
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH edk2-platforms v3 4/5] Platform/NXP: Add LS1046AFRWY Platform
2020-07-08 4:57 ` [PATCH edk2-platforms v3 4/5] Platform/NXP: Add LS1046AFRWY Platform Pankaj Bansal
@ 2020-07-13 16:23 ` Leif Lindholm
0 siblings, 0 replies; 7+ messages in thread
From: Leif Lindholm @ 2020-07-13 16:23 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Augustine Philips, Ard Biesheuvel,
Arokia Samy, Kuldip Dwivedi, Pramod Kumar
On Tue, Jul 07, 2020 at 23:57:18 -0500, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> LS1046A Freeway (FRWY) is a high-performance development
> platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.
>
> Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Series pushed as d144cf773449..c654e2619874.
/
Leif
> ---
>
> Notes:
> V3:
> - Squashed previous commit to this commit
>
> V2:
> - No change
>
> Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec | 23 +++
> Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 46 ++++++
> Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 168 ++++++++++++++++++++
> Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 42 +++++
> Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 147 +++++++++++++++++
> Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 75 +++++++++
> Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S | 45 ++++++
> 7 files changed, 546 insertions(+)
>
> diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
> new file mode 100644
> index 000000000000..a693d8262444
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
> @@ -0,0 +1,23 @@
> +# LS1046aFrwyPkg.dec
> +# LS1046a board package.
> +#
> +# Copyright 2019-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LS1046aFrwyPkg
> + PACKAGE_GUID = 3547d88c-62c2-4fb2-a11b-80245f80928f
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
> new file mode 100644
> index 000000000000..3f29dadd5d1d
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
> @@ -0,0 +1,46 @@
> +# LS1046aFrwyPkg.dsc
> +#
> +# LS1046AFRWY Board package.
> +#
> +# Copyright 2019-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LS1046aFrwyPkg
> + PLATFORM_GUID = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
> + OUTPUT_DIRECTORY = Build/LS1046aFrwyPkg
> + FLASH_DEFINITION = Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
> +
> +!include Silicon/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +
> +[LibraryClasses.common]
> + ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
> + }
> +
> +##
> diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
> new file mode 100644
> index 000000000000..8da5b57cb49e
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
> @@ -0,0 +1,168 @@
> +# LS1046aFrwyPkg.fdf
> +#
> +# FLASH layout file for LS1046a board.
> +#
> +# Copyright 2019-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS1046AFRWY_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1000
> +NumBlocks = 0x140
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x00140000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include Platform/NXP/FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> + INF MdeModulePkg/Universal/Metronome/Metronome.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> + INF MdeModulePkg/Core/Pei/PeiMain.inf
> + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> + INF ArmPkg/Drivers/CpuPei/CpuPei.inf
> + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 000000000000..7802696bf39b
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,42 @@
> +# @file
> +# Copyright 2019-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformLib
> + FILE_GUID = c61c8a13-36a0-46f4-a3bc-7bab5a55db81
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> + Silicon/NXP/LS1046A/LS1046A.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + ArmLib
> + DebugLib
> + SocLib
> +
> +[Sources.common]
> + ArmPlatformLib.c
> + ArmPlatformLibMem.c
> +
> +[Sources.AArch64]
> + AArch64/ArmPlatformHelper.S
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 000000000000..e1f20da09337
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,147 @@
> +/** @file
> +*
> +* Copyright 2019-2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/ArmLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/SocLib.h>
> +
> +#include <Ppi/ArmMpCoreInfo.h>
> +#include <Ppi/NxpPlatformGetClock.h>
> +
> +ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + }
> +};
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
> +
> + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
> + is to be retrieved.
> + @param[in] ... Variable argument list which is parsed based on
> + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> + the second argument will be interpreted as controller
> + number.
> + if ClockType is NXP_CORE_CLOCK, then second argument
> + is interpreted as cluster number and third argument is
> + interpreted as core number (within the cluster)
> +
> + @return Actual Clock Frequency. Return value 0 should be
> + interpreted as clock not being provided to IP.
> +**/
> +UINT64
> +EFIAPI
> +NxpPlatformGetClock(
> + IN UINT32 ClockType,
> + ...
> + )
> +{
> + UINT64 Clock;
> + VA_LIST Args;
> +
> + Clock = 0;
> +
> + VA_START (Args, ClockType);
> +
> + switch (ClockType) {
> + case NXP_SYSTEM_CLOCK:
> + Clock = 100 * 1000 * 1000; // 100 MHz
> + break;
> + case NXP_I2C_CLOCK:
> + case NXP_UART_CLOCK:
> + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> + Clock = SocGetClock (Clock, ClockType, Args);
> + break;
> + default:
> + break;
> + }
> +
> + VA_END (Args);
> +
> + return Clock;
> +}
> +
> +/**
> + Initialize controllers that must setup in the normal world
> +
> + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
> + in the PEI phase.
> +
> +**/
> +EFI_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + SocInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + if (ArmIsMpCore()) {
> + *CoreCount = sizeof(mLS1046aMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
> + *ArmCoreTable = mLS1046aMpCoreInfoTable;
> + return EFI_SUCCESS;
> + } else {
> + return EFI_UNSUPPORTED;
> + }
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi = { NxpPlatformGetClock };
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + if (ArmIsMpCore()) {
> + *PpiListSize = sizeof(gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> + } else {
> + *PpiListSize = 0;
> + *PpiList = NULL;
> + }
> +}
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> new file mode 100644
> index 000000000000..f712d5931821
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> @@ -0,0 +1,75 @@
> +/** @file
> +*
> +* Copyright 2019-2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Soc.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +
> +**/
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
> + )
> +{
> + UINTN Index;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> +
> + Index = 0;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + if (VirtualMemoryTable == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
> + return;
> + }
> +
> + VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1046A_DRAM0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1046A_DRAM0_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1046A_DRAM1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1046A_DRAM1_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // CCSR Space
> + VirtualMemoryTable[Index].PhysicalBase = LS1046A_CCSR_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1046A_CCSR_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1046A_CCSR_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // QSPI
> + VirtualMemoryTable[Index].PhysicalBase = LS1046A_QSPI0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1046A_QSPI0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1046A_QSPI0_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // End of Table
> + ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));
> +
> + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> new file mode 100644
> index 000000000000..4f56a1c366ab
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> @@ -0,0 +1,45 @@
> +//
> +// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 4) CoreId
> +ASM_FUNC(ArmPlatformGetCorePosition)
> + and x1, x0, #ARM_CORE_MASK
> + and x0, x0, #ARM_CLUSTER_MASK
> + add x0, x1, x0, LSR #6
> + ret
> +
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
> + ret
> +
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
> + and x0, x0, x1
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
> + cmp w0, w1
> + mov x0, #1
> + mov x1, #0
> + csel x0, x0, x1, eq
> + ret
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH edk2-platforms v3 5/5] Platform/NXP/LS1046aFrwyPkg: Add VarStore
2020-07-08 4:57 [PATCH edk2-platforms v3 0/5] Add LS1046AFRWY Platform Pankaj Bansal
` (3 preceding siblings ...)
2020-07-08 4:57 ` [PATCH edk2-platforms v3 4/5] Platform/NXP: Add LS1046AFRWY Platform Pankaj Bansal
@ 2020-07-08 4:57 ` Pankaj Bansal
4 siblings, 0 replies; 7+ messages in thread
From: Pankaj Bansal @ 2020-07-08 4:57 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Augustine Philips,
Ard Biesheuvel, Arokia Samy, Kuldip Dwivedi
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Notes:
V3:
- Added Reviewed-by: Leif Lindholm <leif@nuviainc.com>
V2:
- No change
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 1 +
Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc | 91 ++++++++++++++++++++
2 files changed, 92 insertions(+)
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 8da5b57cb49e..24af547729c7 100644
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -48,6 +48,7 @@ [FD.LS1046AFRWY_EFI]
FV = FVMAIN_COMPACT
!include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
################################################################################
#
# FV Section
diff --git a/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
new file mode 100644
index 000000000000..727705feaea1
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1046aFrwyNv_EFI]
+BaseAddress = 0x40500000 #The base address of the FLASH device
+Size = 0x000C0000 #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS1046AFRWY NVRAM Area
+# LS1046AFRWY NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: Flash Size : 0x4000000
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread