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This SOC is based on Layerscape Chassis v2. Co-authored-by: Vabhav Sharma Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - Removed Co-authored-by: Pankaj Bansal - Added Reviewed-by: Leif Lindholm =20 V2: - No change Silicon/NXP/LS1046A/LS1046A.dec | 13 +++ Silicon/NXP/LS1046A/LS1046A.dsc.inc | 42 +++++++ Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 27 +++++ Silicon/NXP/LS1046A/Include/Soc.h | 63 +++++++++++ Silicon/NXP/LS1046A/Include/SocSerDes.h | 33 ++++++ Silicon/NXP/LS1046A/Library/SocLib/SerDes.c | 119 ++++++++++++++++++++ Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 78 +++++++++++++ 7 files changed, 375 insertions(+) diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.= dec new file mode 100644 index 000000000000..bf4863c6d89e --- /dev/null +++ b/Silicon/NXP/LS1046A/LS1046A.dec @@ -0,0 +1,13 @@ +# LS1046A.dec +# +# Copyright 2017, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + +[Includes] + Include diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS10= 46A.dsc.inc new file mode 100644 index 000000000000..dbe7f408fce9 --- /dev/null +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc @@ -0,0 +1,42 @@ +# LS1046A.dsc +# LS1046A Soc package. +# +# Copyright 2017-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc + +[LibraryClasses.common] + SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsDynamicDefault.common] + + # + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000 + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 + +[PcdsFeatureFlag] + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + +## diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS= 1046A/Library/SocLib/SocLib.inf new file mode 100644 index 000000000000..01ed0f6592d2 --- /dev/null +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf @@ -0,0 +1,27 @@ +# @file +# +# Copyright 2017-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocLib + FILE_GUID =3D ddd5f950-8816-4d38-8f98-f42b07333f78 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SocLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/Chassis2/Chassis2.dec + Silicon/NXP/LS1046A/LS1046A.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ChassisLib + DebugLib + +[Sources.common] + SocLib.c diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Includ= e/Soc.h new file mode 100644 index 000000000000..84f433d5cb94 --- /dev/null +++ b/Silicon/NXP/LS1046A/Include/Soc.h @@ -0,0 +1,63 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SOC_H__ +#define SOC_H__ + +#include + +/** + Soc Memory Map +**/ +#define LS1046A_DRAM0_PHYS_ADDRESS (BASE_2GB) +#define LS1046A_DRAM0_SIZE (SIZE_2GB) +#define LS1046A_DRAM1_PHYS_ADDRESS (BASE_32GB + BASE_2GB) +#define LS1046A_DRAM1_SIZE (SIZE_32GB - SIZE_2GB) // 30 GB + +#define LS1046A_CCSR_PHYS_ADDRESS (BASE_16MB) +#define LS1046A_CCSR_SIZE (SIZE_256MB - SIZE_16MB) // 240MB + +#define LS1046A_QSPI0_PHYS_ADDRESS (BASE_1GB) +#define LS1046A_QSPI0_SIZE (SIZE_512MB) + +#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS + +/** + Reset Control Word (RCW) Bits + + RCWSR contains the Reset Configuration Word (RCW) information written wi= th + values read from flash memory by the device at power-on reset and read-o= nly + upon exiting reset. + + RCW bits in RCWSR registers are mirror of bit position in Little Endian = (LE) + +RCW Bits | +in RCWSR | +(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2= 4 25 26 27 28 29 30 31 +--------------------------------------------------------------------------= ---------------------- +LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 = 10 9 8 7 6 5 4 3 2 1 0 +(LSBit 0)| + + Moreover the RCW bits are to be interpreted in below fasion + +Bit(s) | Field Name | Description | Notes/comments +---------------------------------------------------------------------- + 2-6 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects t= he platform + | | | clock:SYSCLK ratio. + | | | 0_0011 3:1 + | | | 0_0100 4:1 + | | | 0_1101 13:1 + | | | 0_1111 15:1 + | | | 1_0000 16:1 + + which is why the RCW bits in RCWSR registers are parsed this way +**/ +#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 + +typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG; + +#endif // SOC_H__ diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/= Include/SocSerDes.h new file mode 100644 index 000000000000..2fc5651c004c --- /dev/null +++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h @@ -0,0 +1,33 @@ +/** SocSerDes.h + SoC Specific header file for SerDes + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SOC_SERDES_H +#define SOC_SERDES_H + +typedef enum { + NONE =3D 0, + PCIE1, + PCIE2, + PCIE3, + SATA, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, + QSGMII_FM1_A, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SERDES_PROTOCOL_COUNT +} SERDES_PROTOCOL; +#endif diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SerDes.c b/Silicon/NXP/LS10= 46A/Library/SocLib/SerDes.c new file mode 100644 index 000000000000..a50e0b61e19a --- /dev/null +++ b/Silicon/NXP/LS1046A/Library/SocLib/SerDes.c @@ -0,0 +1,119 @@ +/** SerDes.c + Provides SoC specific SerDes interface + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +// SerDes1 Protocol Mask in Reset Configuration Word (RCW) Status Register +#define SERDES1_PROTOCOL_MASK 0xffff0000 + +// SerDes1 Protocol Shift in Reset Configuration Word (RCW) Status Registe= r +#define SERDES1_PROTOCOL_SHIFT 16 + +STATIC SERDES_CONFIG mSerDes1ConfigTable[] =3D { + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } }, + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } }, + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } }, + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } = }, + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } }, + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } }, + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } }, + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } }, + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } }= , + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM= 1_DTSEC6 } }, + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGM= II_FM1_DTSEC6 } }, + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSE= C6 } }, + {} +}; + +SERDES_CONFIG *gSerDesConfig[] =3D { + mSerDes1ConfigTable +}; + +/** + Probe all SerDes for lane protocol and execute provided callback functio= n. + + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. + +**/ +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + UINT32 SerDesProtocol; + LS1046A_DEVICE_CONFIG *DeviceConfig; + + DeviceConfig =3D (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS; + SerDesProtocol =3D DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1= _PROTOCOL_MASK; + SerDesProtocol >>=3D SERDES1_PROTOCOL_SHIFT; + + SerDesInstanceProbeLanes ( + SERDES_1, + SerDesProtocol, + FixedPcdGet8 (PcdSerDesLanes), + SERDES_PROTOCOL_COUNT, + gSerDesConfig[SERDES_1], + SerDesLaneProbeCallback, + Arg + ); +} + +/** + Function to return SerDes protocol map for all SerDes available on board= . + + @param SerDesProtocolMap Pointer to SerDes protocl map. + +**/ +VOID +GetSerDesProtocolMap ( + OUT UINT64 *SerDesProtocolMap + ) +{ + UINT32 SerDesProtocol; + LS1046A_DEVICE_CONFIG *DeviceConfig; + EFI_STATUS Status; + + *SerDesProtocolMap =3D 0; + DeviceConfig =3D (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS; + SerDesProtocol =3D DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1= _PROTOCOL_MASK; + SerDesProtocol >>=3D SERDES1_PROTOCOL_SHIFT; + + Status =3D GetSerDesMap ( + SERDES_1, + SerDesProtocol, + FixedPcdGet8 (PcdSerDesLanes), + SERDES_PROTOCOL_COUNT, + gSerDesConfig[SERDES_1], + SerDesProtocolMap + ); + + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__)); + *SerDesProtocolMap =3D 0; + } +} diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS10= 46A/Library/SocLib/SocLib.c new file mode 100644 index 000000000000..3b15aee6ecae --- /dev/null +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c @@ -0,0 +1,78 @@ +/** @Soc.c + SoC specific Library containg functions to initialize various SoC compon= ents + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Return the input clock frequency to an IP Module. + This function reads the RCW bits and calculates the PLL multiplier/divi= der + values to be applied to various IP modules. + If a module is disabled or doesn't exist on platform, then return zero. + + @param[in] BaseClock Base clock to which PLL multiplier/divider values= is + to be applied. + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] Args Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within th= e + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +SocGetClock ( + IN UINT64 BaseClock, + IN NXP_IP_CLOCK ClockType, + IN VA_LIST Args + ) +{ + LS1046A_DEVICE_CONFIG *Dcfg; + UINT32 RcwSr; + UINT64 ReturnValue; + + ReturnValue =3D 0; + Dcfg =3D (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS; + + switch (ClockType) { + case NXP_UART_CLOCK: + case NXP_I2C_CLOCK: + RcwSr =3D DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]); + ReturnValue =3D BaseClock * SYS_PLL_RAT (RcwSr); + ReturnValue >>=3D 1; // 1/2 Platform Clock + break; + default: + break; + } + + return ReturnValue; +} + +/** + Function to initialize SoC specific constructs + **/ +VOID +SocInit ( + VOID + ) +{ + ChassisInit (); + + return; +} --=20 2.17.1