Re: [PATCH edk2-platforms v3 4/5] Platform/NXP: Add LS1046AFRWY Platform

["Leif Lindholm" <leif@nuviainc.com>]

On Tue, Jul 07, 2020 at 23:57:18 -0500, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
> 
> LS1046A Freeway (FRWY) is a high-performance development
> platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.
> 
> Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>

Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Series pushed as d144cf773449..c654e2619874.

/
    Leif

> ---
> 
> Notes:
>     V3:
>     - Squashed previous commit to this commit
>     
>     V2:
>     - No change
> 
>  Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec                                 |  23 +++
>  Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc                                 |  46 ++++++
>  Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf                                 | 168 ++++++++++++++++++++
>  Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf          |  42 +++++
>  Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c            | 147 +++++++++++++++++
>  Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c         |  75 +++++++++
>  Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S |  45 ++++++
>  7 files changed, 546 insertions(+)
> 
> diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
> new file mode 100644
> index 000000000000..a693d8262444
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
> @@ -0,0 +1,23 @@
> +#  LS1046aFrwyPkg.dec
> +#  LS1046a board package.
> +#
> +#  Copyright 2019-2020 NXP
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +[Defines]
> +  PACKAGE_NAME                   = LS1046aFrwyPkg
> +  PACKAGE_GUID                   = 3547d88c-62c2-4fb2-a11b-80245f80928f
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +#                   Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> +  Include                        # Root include for the package
> diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
> new file mode 100644
> index 000000000000..3f29dadd5d1d
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
> @@ -0,0 +1,46 @@
> +#  LS1046aFrwyPkg.dsc
> +#
> +#  LS1046AFRWY Board package.
> +#
> +#  Copyright 2019-2020 NXP
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> +  #
> +  # Defines for default states.  These can be changed on the command line.
> +  # -D FLAG=VALUE
> +  #
> +  PLATFORM_NAME                  = LS1046aFrwyPkg
> +  PLATFORM_GUID                  = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
> +  OUTPUT_DIRECTORY               = Build/LS1046aFrwyPkg
> +  FLASH_DEFINITION               = Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
> +
> +!include Silicon/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +
> +[LibraryClasses.common]
> +  ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +  RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> +  #
> +  # Architectural Protocols
> +  #
> +  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> +    <PcdsFixedAtBuild>
> +    gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
> +  }
> +
> +##
> diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
> new file mode 100644
> index 000000000000..8da5b57cb49e
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
> @@ -0,0 +1,168 @@
> +#  LS1046aFrwyPkg.fdf
> +#
> +#  FLASH layout file for LS1046a board.
> +#
> +#  Copyright 2019-2020 NXP
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into  the Flash Device Image.  Each FD section
> +# defines one flash "device" image.  A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash"  image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS1046AFRWY_EFI]
> +BaseAddress   = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress  #The base address of the FLASH Device.
> +Size          = 0x00140000|gArmTokenSpaceGuid.PcdFdSize         #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize     = 0x1000
> +NumBlocks     = 0x140
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x00140000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include Platform/NXP/FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file.  This section also defines order the components and modules are positioned
> +# within the image.  The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid         = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize          = 0x1
> +NumBlocks          = 0         # This FV gets compressed so make it just big enough
> +FvAlignment        = 8         # FV alignment and FV attributes setting.
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +  INF MdeModulePkg/Core/Dxe/DxeMain.inf
> +  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> +  #
> +  # PI DXE Drivers producing Architectural Protocols (EFI Services)
> +  #
> +  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> +  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> +  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> +  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> +  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +  INF MdeModulePkg/Universal/Metronome/Metronome.inf
> +  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> +  #
> +  # Multiple Console IO support
> +  #
> +  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> +  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> +  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> +  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> +  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> +  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> +
> +  #
> +  # FAT filesystem + GPT/MBR partitioning
> +  #
> +  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> +  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +  INF FatPkg/EnhancedFatDxe/Fat.inf
> +  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +
> +  #
> +  # UEFI application (Shell Embedded Boot Loader)
> +  #
> +  INF ShellPkg/Application/Shell/Shell.inf
> +
> +  #
> +  # Bds
> +  #
> +  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> +  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> +  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment        = 8
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> +  INF MdeModulePkg/Core/Pei/PeiMain.inf
> +  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> +  INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> +  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> +  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
> +  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> +  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +
> +  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> +    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> +      SECTION FV_IMAGE = FVMAIN
> +    }
> +  }
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 000000000000..7802696bf39b
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,42 @@
> +# @file
> +# Copyright 2019-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001A
> +  BASE_NAME                      = PlatformLib
> +  FILE_GUID                      = c61c8a13-36a0-46f4-a3bc-7bab5a55db81
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = ArmPlatformLib
> +
> +[Packages]
> +  ArmPkg/ArmPkg.dec
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +  Silicon/NXP/Chassis2/Chassis2.dec
> +  Silicon/NXP/LS1046A/LS1046A.dec
> +  Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> +  ArmLib
> +  DebugLib
> +  SocLib
> +
> +[Sources.common]
> +  ArmPlatformLib.c
> +  ArmPlatformLibMem.c
> +
> +[Sources.AArch64]
> +  AArch64/ArmPlatformHelper.S
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdArmPrimaryCore
> +  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> +
> +[Ppis]
> +  gArmMpCoreInfoPpiGuid
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 000000000000..e1f20da09337
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,147 @@
> +/** @file
> +*
> +*  Copyright 2019-2020 NXP
> +*
> +*  SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/ArmLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/SocLib.h>
> +
> +#include <Ppi/ArmMpCoreInfo.h>
> +#include <Ppi/NxpPlatformGetClock.h>
> +
> +ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
> +  {
> +    // Cluster 0, Core 0
> +    0x0, 0x0,
> +
> +    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (EFI_PHYSICAL_ADDRESS)0,
> +    (UINT64)0xFFFFFFFF
> +  }
> +};
> +
> +/**
> +  Return the current Boot Mode
> +
> +  This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> +  VOID
> +  )
> +{
> +  return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> +  Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
> +
> +  @param[in]  ClockType  Variable of Type NXP_IP_CLOCK. Indicates which IP clock
> +                         is to be retrieved.
> +  @param[in]  ...        Variable argument list which is parsed based on
> +                         ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> +                         the second argument will be interpreted as controller
> +                         number.
> +                         if ClockType is NXP_CORE_CLOCK, then second argument
> +                         is interpreted as cluster number and third argument is
> +                         interpreted as core number (within the cluster)
> +
> +  @return                Actual Clock Frequency. Return value 0 should be
> +                         interpreted as clock not being provided to IP.
> +**/
> +UINT64
> +EFIAPI
> +NxpPlatformGetClock(
> +  IN  UINT32  ClockType,
> +  ...
> +  )
> +{
> +  UINT64      Clock;
> +  VA_LIST     Args;
> +
> +  Clock = 0;
> +
> +  VA_START (Args, ClockType);
> +
> +  switch (ClockType) {
> +  case NXP_SYSTEM_CLOCK:
> +    Clock = 100 * 1000 * 1000; // 100 MHz
> +    break;
> +  case NXP_I2C_CLOCK:
> +  case NXP_UART_CLOCK:
> +    Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> +    Clock = SocGetClock (Clock, ClockType, Args);
> +    break;
> +  default:
> +    break;
> +  }
> +
> +  VA_END (Args);
> +
> +  return Clock;
> +}
> +
> +/**
> +  Initialize controllers that must setup in the normal world
> +
> +  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
> +  in the PEI phase.
> +
> +**/
> +EFI_STATUS
> +ArmPlatformInitialize (
> +  IN  UINTN                     MpId
> +  )
> +{
> +  SocInit ();
> +
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> +  OUT UINTN                   *CoreCount,
> +  OUT ARM_CORE_INFO           **ArmCoreTable
> +  )
> +{
> +  if (ArmIsMpCore()) {
> +    *CoreCount    = sizeof(mLS1046aMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
> +    *ArmCoreTable = mLS1046aMpCoreInfoTable;
> +    return EFI_SUCCESS;
> +  } else {
> +    return EFI_UNSUPPORTED;
> +  }
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi = { NxpPlatformGetClock };
> +
> +EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
> +  {
> +    EFI_PEI_PPI_DESCRIPTOR_PPI,
> +    &gArmMpCoreInfoPpiGuid,
> +    &mMpCoreInfoPpi
> +  }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> +  OUT UINTN                   *PpiListSize,
> +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
> +  )
> +{
> +  if (ArmIsMpCore()) {
> +    *PpiListSize = sizeof(gPlatformPpiTable);
> +    *PpiList = gPlatformPpiTable;
> +  } else {
> +    *PpiListSize = 0;
> +    *PpiList = NULL;
> +  }
> +}
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> new file mode 100644
> index 000000000000..f712d5931821
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> @@ -0,0 +1,75 @@
> +/** @file
> +*
> +*  Copyright 2019-2020 NXP
> +*
> +*  SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Soc.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          5
> +
> +/**
> +  Return the Virtual Memory Map of your platform
> +
> +  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> +  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> +                                    Virtual Memory mapping. This array must be ended by a zero-filled
> +                                    entry
> +
> +**/
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> +  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
> +  )
> +{
> +  UINTN                            Index;
> +  ARM_MEMORY_REGION_DESCRIPTOR     *VirtualMemoryTable;
> +
> +  Index = 0;
> +
> +  ASSERT (VirtualMemoryMap != NULL);
> +
> +  VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> +                                     MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> +  if (VirtualMemoryTable == NULL) {
> +    DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
> +    return;
> +  }
> +
> +  VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM0_PHYS_ADDRESS;
> +  VirtualMemoryTable[Index].VirtualBase  = LS1046A_DRAM0_PHYS_ADDRESS;
> +  VirtualMemoryTable[Index].Length       = LS1046A_DRAM0_SIZE;
> +  VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> +  VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM1_PHYS_ADDRESS;
> +  VirtualMemoryTable[Index].VirtualBase  = LS1046A_DRAM1_PHYS_ADDRESS;
> +  VirtualMemoryTable[Index].Length       = LS1046A_DRAM1_SIZE;
> +  VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> +  // CCSR Space
> +  VirtualMemoryTable[Index].PhysicalBase = LS1046A_CCSR_PHYS_ADDRESS;
> +  VirtualMemoryTable[Index].VirtualBase  = LS1046A_CCSR_PHYS_ADDRESS;
> +  VirtualMemoryTable[Index].Length       = LS1046A_CCSR_SIZE;
> +  VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> +  // QSPI
> +  VirtualMemoryTable[Index].PhysicalBase = LS1046A_QSPI0_PHYS_ADDRESS;
> +  VirtualMemoryTable[Index].VirtualBase  = LS1046A_QSPI0_PHYS_ADDRESS;
> +  VirtualMemoryTable[Index].Length       = LS1046A_QSPI0_SIZE;
> +  VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> +  // End of Table
> +  ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));
> +
> +  ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> +  *VirtualMemoryMap = VirtualMemoryTable;
> +}
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> new file mode 100644
> index 000000000000..4f56a1c366ab
> --- /dev/null
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> @@ -0,0 +1,45 @@
> +//
> +//  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +//
> +//  SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> +  ret
> +
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +//  IN UINTN MpId
> +//  );
> +// With this function: CorePos = (ClusterId * 4)  CoreId
> +ASM_FUNC(ArmPlatformGetCorePosition)
> +  and   x1, x0, #ARM_CORE_MASK
> +  and   x0, x0, #ARM_CLUSTER_MASK
> +  add   x0, x1, x0, LSR #6
> +  ret
> +
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +//  VOID
> +//  );
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> +  MOV32  (w0, FixedPcdGet32 (PcdArmPrimaryCore))
> +  ret
> +
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +//  IN UINTN MpId
> +//  );
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> +  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
> +  and   x0, x0, x1
> +  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCore))
> +  cmp   w0, w1
> +  mov   x0, #1
> +  mov   x1, #0
> +  csel  x0, x0, x1, eq
> +  ret
> -- 
> 2.17.1
>