From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by mx.groups.io with SMTP id smtpd.web10.13583.1594900106430615110 for ; Thu, 16 Jul 2020 04:48:26 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@9elements.com header.s=google header.b=D8eAL37G; spf=pass (domain: 9elements.com, ip: 209.85.221.66, mailfrom: marcello.bauer@9elements.com) Received: by mail-wr1-f66.google.com with SMTP id o11so6731947wrv.9 for ; Thu, 16 Jul 2020 04:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=9elements.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ptJhptv2JHqs+nj9Mzm4s7jtEl52Nt17uIS24pPFZnU=; b=D8eAL37GFBJdJ33zp9gWfXHVVJ5J8o6a/yNwyJOFsYMC5bOETmXo+XhRls1Jex+ljl Yuf4WFs6I2AHDcVy1I+Ov//9ubqOA1x4WHqpaZPgU0pJwWGSLqb/8L6YDrXgziuLzFd4 ymMHgJhud4S42W1nqHazIvI9I/KJXIdN0u9s9nq0Ch3ycLs4c47lANL0PMrKxfNh3x2Y XaJ0O9P9vupoV9APRkSmJGBKtdRm8dksHgHjMoTP09qYrlsJHr/VxR/PFNaBrAZ8QjlW 6F+8SA3u5MKRqCqdqO0fNz7/2QXauLlPiYb7X6S0Y9rjwY7S7u+zn4bgfuOurjCkTL7W dWqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ptJhptv2JHqs+nj9Mzm4s7jtEl52Nt17uIS24pPFZnU=; b=U98Y2G6UpD5S03OScTp1XhztlGgsBNWGqspNdtqUFBFgifrHncP0PgMzWyq8XfHN2Y YXDGlAidHSV/Yo7L0KGhSTxQm6QveuuhAew8WqHid+Hresk753fusmR6CKyV8Wcwwk5E oISiAt4hHcGMH7bK47aYhRiprl240q5LKYgIECkDS0GgxLBFdMRsy/htDEv9rVqxfCgm sEsXbsgNpo0FUccVlaevnJHUzIantvXRYJzUoCe/uwy4TZrEL7FJsab5lvK85oMoaMRl m8pkRIFUz0AQw71yGqeh5StFL8bqnzjZAiM9efZII0Ijgm8xzlGXXHv9uh96YZEk3mRC /pBg== X-Gm-Message-State: AOAM533ozfTB429NApM6pKLo5Ox4VzGSsgBPMVe08gxpP4bcmNp3792L fLFHshaDTLXWXV6bxJSGs31Ayu5ootM= X-Google-Smtp-Source: ABdhPJzG3GRRwKY/JtgB24Mb02FGoPcBJAng2hShwUOaNFsij5vIl2cz8kULqx71jhJFeTw+sPTMLQ== X-Received: by 2002:a5d:6a04:: with SMTP id m4mr4631237wru.418.1594900104699; Thu, 16 Jul 2020 04:48:24 -0700 (PDT) Return-Path: Received: from T580.dut.n1ce.space ([2a02:908:e851:d750:f570:655a:1f30:429f]) by smtp.gmail.com with ESMTPSA id v5sm7989811wmh.12.2020.07.16.04.48.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 04:48:24 -0700 (PDT) From: "Marcello Sylvester Bauer" To: devel@edk2.groups.io Cc: Patrick Rudolph , Christian Walter , Maurice Ma , Nate DeSimone , Star Zeng , Michael D Kinney , Liming Gao Subject: [PATCH v2 2/2] MdePkg: Add support for variable size MMCONF space Date: Thu, 16 Jul 2020 13:48:20 +0200 Message-Id: <20200716114820.14211-3-marcello.bauer@9elements.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716114820.14211-1-marcello.bauer@9elements.com> References: <20200716114820.14211-1-marcello.bauer@9elements.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Patrick Rudolph On embedded AMD platforms the MMCONF window is usually only 64MiB. Add support for arbitrary sized MMCONF by introducing a new PCD. The default size is still 256MiB, but will be overwritten by UefiPayloadPkg with the real MMCONF size. Fixes crash on platforms not exposing 256 buses. Tested on: * AMD Stoney Ridge Signed-off-by: Patrick Rudolph Signed-off-by: Marcello Sylvester Bauer Cc: Patrick Rudolph Cc: Christian Walter Cc: Maurice Ma Cc: Nate DeSimone Cc: Star Zeng Cc: Michael D Kinney Cc: Liming Gao --- MdePkg/MdePkg.dec | 4 + UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 1 + MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf | 6 +- UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf | 1 + MdePkg/Include/Library/PciExpressLib.h | 5 +- MdePkg/Library/BasePciExpressLib/PciExpressLib.c | 118 +++++++++++++= ++++++- UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c | 4 +- 7 files changed, 131 insertions(+), 8 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 73f6c2407357..02e736a01126 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynami= c, PcdsDynamicEx] # @Prompt PCI Express Base Address.=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x00= 00000a=0D =0D + ## This value is used to set the size of PCI express hierarchy. The defa= ult is 256 MB.=0D + # @Prompt PCI Express Base Size.=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x0FFFFFFF|UINT64|0x00000= 00f=0D +=0D ## Default current ISO 639-2 language: English & French.=0D # @Prompt Default Value of LangCodes Variable.=0D gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|= VOID*|0x0000001c=0D diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/Uefi= PayloadPkgIa32X64.dsc index a768a8702c66..162cbf47a83f 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc @@ -363,6 +363,7 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31=0D gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0=0D =0D ##########################################################################= ######=0D #=0D diff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdePk= g/Library/BasePciExpressLib/BasePciExpressLib.inf index a7edb74cde71..12734b022ac7 100644 --- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf +++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf @@ -1,7 +1,7 @@ ## @file=0D -# Instance of PCI Express Library using the 256 MB PCI Express MMIO windo= w.=0D +# Instance of PCI Express Library using the variable size PCI Express MMI= O window.=0D #=0D -# PCI Express Library that uses the 256 MB PCI Express MMIO window to per= form=0D +# PCI Express Library that uses the variable size PCI Express MMIO window= to perform=0D # PCI Configuration cycles. Layers on top of an I/O Library instance.=0D #=0D # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= =0D @@ -38,4 +38,4 @@ [LibraryClasses] =0D [Pcd]=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES=0D -=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES=0D diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf b/UefiPayloadPkg/= BlSupportDxe/BlSupportDxe.inf index 1371d5eb7952..cebc81135565 100644 --- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf +++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf @@ -54,6 +54,7 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution=0D gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=0D =0D [Depex]=0D TRUE=0D diff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Librar= y/PciExpressLib.h index 826fdcf7db6c..d78193a0a352 100644 --- a/MdePkg/Include/Library/PciExpressLib.h +++ b/MdePkg/Include/Library/PciExpressLib.h @@ -2,8 +2,9 @@ Provides services to access PCI Configuration Space using the MMIO PCI E= xpress window.=0D =0D This library is identical to the PCI Library, except the access method f= or performing PCI=0D - configuration cycles must be through the 256 MB PCI Express MMIO window = whose base address=0D - is defined by PcdPciExpressBaseAddress.=0D + configuration cycles must be through the PCI Express MMIO window whose b= ase address=0D + is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpress= BaseSize.=0D +=0D =0D Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D diff --git a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c b/MdePkg/Libr= ary/BasePciExpressLib/PciExpressLib.c index 99a166c3609b..4d099f2c575e 100644 --- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c +++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c @@ -22,7 +22,8 @@ =0D /**=0D Assert the validity of a PCI address. A valid PCI address should contain= 1's=0D - only in the low 28 bits.=0D + only in the low 28 bits. PcdPciExpressBaseSize limits the size to the re= al=0D + number of PCI busses in this segment.=0D =0D @param A The address to validate.=0D =0D @@ -58,7 +59,6 @@ PciExpressRegisterForRuntimeAccess ( IN UINTN Address=0D )=0D {=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D return RETURN_UNSUPPORTED;=0D }=0D =0D @@ -79,6 +79,24 @@ GetPciExpressBaseAddress ( return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);=0D }=0D =0D +/**=0D + Gets the size of PCI Express.=0D +=0D + This internal functions retrieves PCI Express Base Size via a PCD entry= =0D + PcdPciExpressBaseSize.=0D +=0D + @return The base address of PCI Express.=0D +=0D +**/=0D +STATIC=0D +UINTN=0D +PcdPciExpressBaseSize (=0D + VOID=0D + )=0D +{=0D + return (UINTN) PcdGet64 (PcdPciExpressBaseSize);=0D +}=0D +=0D /**=0D Reads an 8-bit PCI configuration register.=0D =0D @@ -101,6 +119,9 @@ PciExpressRead8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);=0D }=0D =0D @@ -128,6 +149,9 @@ PciExpressWrite8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value)= ;=0D }=0D =0D @@ -159,6 +183,9 @@ PciExpressOr8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D }=0D =0D @@ -190,6 +217,9 @@ PciExpressAnd8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData)= ;=0D }=0D =0D @@ -224,6 +254,9 @@ PciExpressAndThenOr8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioAndThenOr8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D AndData,=0D @@ -261,6 +294,9 @@ PciExpressBitFieldRead8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldRead8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -302,6 +338,9 @@ PciExpressBitFieldWrite8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldWrite8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -347,6 +386,9 @@ PciExpressBitFieldOr8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldOr8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -392,6 +434,9 @@ PciExpressBitFieldAnd8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldAnd8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -442,6 +487,9 @@ PciExpressBitFieldAndThenOr8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldAndThenOr8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -474,6 +522,9 @@ PciExpressRead16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);=0D }=0D =0D @@ -502,6 +553,9 @@ PciExpressWrite16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value= );=0D }=0D =0D @@ -534,6 +588,9 @@ PciExpressOr16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D }=0D =0D @@ -566,6 +623,9 @@ PciExpressAnd16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData= );=0D }=0D =0D @@ -601,6 +661,9 @@ PciExpressAndThenOr16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioAndThenOr16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D AndData,=0D @@ -639,6 +702,9 @@ PciExpressBitFieldRead16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldRead16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -681,6 +747,9 @@ PciExpressBitFieldWrite16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldWrite16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -727,6 +796,9 @@ PciExpressBitFieldOr16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldOr16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -773,6 +845,9 @@ PciExpressBitFieldAnd16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldAnd16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -824,6 +899,9 @@ PciExpressBitFieldAndThenOr16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldAndThenOr16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -856,6 +934,9 @@ PciExpressRead32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);=0D }=0D =0D @@ -884,6 +965,9 @@ PciExpressWrite32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value= );=0D }=0D =0D @@ -916,6 +1000,9 @@ PciExpressOr32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D }=0D =0D @@ -948,6 +1035,9 @@ PciExpressAnd32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData= );=0D }=0D =0D @@ -983,6 +1073,9 @@ PciExpressAndThenOr32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioAndThenOr32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D AndData,=0D @@ -1021,6 +1114,9 @@ PciExpressBitFieldRead32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldRead32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1063,6 +1159,9 @@ PciExpressBitFieldWrite32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldWrite32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1109,6 +1208,9 @@ PciExpressBitFieldOr32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioBitFieldOr32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1155,6 +1257,9 @@ PciExpressBitFieldAnd32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioBitFieldAnd32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1206,6 +1311,9 @@ PciExpressBitFieldAndThenOr32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioBitFieldAndThenOr32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1249,6 +1357,9 @@ PciExpressReadBuffer ( UINTN ReturnValue;=0D =0D ASSERT_INVALID_PCI_ADDRESS (StartAddress);=0D + if (StartAddress >=3D PcdPciExpressBaseSize()) {=0D + return (UINTN) ~0;=0D + }=0D ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D =0D if (Size =3D=3D 0) {=0D @@ -1349,6 +1460,9 @@ PciExpressWriteBuffer ( UINTN ReturnValue;=0D =0D ASSERT_INVALID_PCI_ADDRESS (StartAddress);=0D + if (StartAddress >=3D PcdPciExpressBaseSize()) {=0D + return (UINTN) ~0;=0D + }=0D ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D =0D if (Size =3D=3D 0) {=0D diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c b/UefiPayloadPkg/Bl= SupportDxe/BlSupportDxe.c index a3974dcc02f8..a746d0581ee3 100644 --- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c +++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c @@ -155,13 +155,15 @@ BlDxeEntryPoint ( }=0D =0D //=0D - // Set PcdPciExpressBaseAddress by HOB info=0D + // Set PcdPciExpressBaseAddress and PcdPciExpressBaseSize by HOB info=0D //=0D GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);=0D if (GuidHob !=3D NULL) {=0D AcpiBoardInfo =3D (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);=0D Status =3D PcdSet64S (PcdPciExpressBaseAddress, AcpiBoardInfo->PcieBas= eAddress);=0D ASSERT_EFI_ERROR (Status);=0D + Status =3D PcdSet64S (PcdPciExpressBaseSize, AcpiBoardInfo->PcieBaseSi= ze);=0D + ASSERT_EFI_ERROR (Status);=0D }=0D =0D return EFI_SUCCESS;=0D --=20 2.27.0