From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by mx.groups.io with SMTP id smtpd.web12.8275.1594980563351030588 for ; Fri, 17 Jul 2020 03:09:23 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=rcAbRqBB; spf=pass (domain: linaro.org, ip: 209.85.210.194, mailfrom: masahisa.kojima@linaro.org) Received: by mail-pf1-f194.google.com with SMTP id 1so5166642pfn.9 for ; Fri, 17 Jul 2020 03:09:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZIfZV7iGUnhxvMj1Pswdw65wVyUzqXJIlODq+xaq6S4=; b=rcAbRqBBuad6j/fl+R+0VzaKUKFHvuR2K+jnI2LtbP+qxVHAicN/0X7AyU+tbpV0iG ZbwPaNJdYY8XHRAG9UenzTf7NCAI0GOeiyU+UzUPBWBjQmN15tfCeuO31jwDVO7ml2lV KT7oE4VC6boM+4W2Q48UJlqOll/W/Ve+1+B9F7vVwhtWbbzXNJfKfjoo3K+PkIRrOB3z ztUQymYA3ZSE0CD1QDhj6urjNF+5+XvwnMrvsP4RtehVyR+yy4xHxhJRbyPPthrl529p UCHQZTe+04c6G9Yh15QNrkUIRXzqUl600G/Y+yMPU3ADsO0cZfyxN+I7/wQ0Z6YLZBLY Xg0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZIfZV7iGUnhxvMj1Pswdw65wVyUzqXJIlODq+xaq6S4=; b=Hn83f7E7twAccQpOrXbdjrFfFjDB/tDRmfST8NjJCt8LxadwuhUi2h3QDWBMjt9UJN odTkCO6xklck0BqLVEWWH6AsyMAKo/Ufk2mFkDToCXD+Mx7n9s50lyPF0z3vwpE7bVd4 zbkp5YePED0S0C5fucMCvapaoi6oEftPK4JcGHRWhg7MfG/G5JXzpMXkQLEfhvUICgYg nIbUYfT4zDkSi0oYfM9BGdEz3DdZBHvkBiagj3gPAkrCeju3xwAdU3CMGTMp1wbQ8nv/ el1pMtYE1RoH1NtBjqwEjqy9E0HLkSnLg8uc0mSJv8UMicbxzGIOJaM8GmuztCYFCIY9 2cWQ== X-Gm-Message-State: AOAM532+NbyocLtvRCT+456418hROvU8toMAUqbYcO99PtKWlvn3LmP8 moDCKleSE/LrZDt89jHZCCc9Cq+euLT/kQ== X-Google-Smtp-Source: ABdhPJw8EaO2cwxe8x/4mCZ5IrYm6FxvtglNpy4HJ3Z/RYG2ZH7R4cx5eJD2CpemFAulQe2A3TMRJQ== X-Received: by 2002:a63:8f51:: with SMTP id r17mr8035919pgn.124.1594980562218; Fri, 17 Jul 2020 03:09:22 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([2400:2411:502:a100:82fa:5bff:fe4b:26b1]) by smtp.gmail.com with ESMTPSA id q10sm8060358pfk.86.2020.07.17.03.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2020 03:09:21 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io, ard.biesheuvel@arm.com, leif@nuviainc.com Cc: masahisa.kojima@linaro.org Subject: [PATCH edk2-platforms 1/2] Silicon/SynQuacer: add ACPI descriptor of MMIO TPM Date: Fri, 17 Jul 2020 19:09:11 +0900 Message-Id: <20200717100912.25757-2-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717100912.25757-1-masahisa.kojima@linaro.org> References: <20200717100912.25757-1-masahisa.kojima@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The second SPI controller is wired to the low speed 96boards connector on Developerbox. SynQuacer platform can exposes its SPI TPM via MMIO window that is backed by the SPI command sequencer in the SPI bus controller. This commit adds the MMIO TPM description to the DSDT. If TPM2_ENABLE build option is not enabled, existing linux SPI driver is used instead of MMIO TPM. Signed-off-by: Masahisa Kojima --- Silicon/Socionext/SynQuacer/Acpi.dsc.inc | 7 ++++++- Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/Silicon/Socionext/SynQuacer/Acpi.dsc.inc b/Silicon/Socionext/SynQuacer/Acpi.dsc.inc index acd903553368..ce5a1f6c5007 100644 --- a/Silicon/Socionext/SynQuacer/Acpi.dsc.inc +++ b/Silicon/Socionext/SynQuacer/Acpi.dsc.inc @@ -39,4 +39,9 @@ [Components.common] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 } MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf - Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf + Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf { + +!if $(TPM2_ENABLE) == TRUE + *_*_*_ASLPP_FLAGS = -DTPM2_ENABLE +!endif + } diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index 50f1753c3565..bca484763d2c 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -262,6 +262,19 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", Name (_HID, "PNP0C0C") } +#ifdef TPM2_ENABLE + // + // TPM MMIO device. + // This is backed by the SPI command sequencer in the SPI bus controller. + // + Device (TPM0) { + Name (_HID, "SCX0009") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_SPI1_MMIO_BASE, SYNQUACER_SPI1_MMIO_SIZE) + }) + } +#else Device (SPI0) { Name (_HID, "SCX0004") Name (_UID, Zero) @@ -280,5 +293,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", } }) } +#endif } // Scope (_SB) } -- 2.17.1