From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.groups.io with SMTP id smtpd.web12.17644.1595420704194980810 for ; Wed, 22 Jul 2020 05:25:04 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=hRA+CHXE; spf=pass (domain: nuviainc.com, ip: 209.85.221.68, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f68.google.com with SMTP id z15so1698906wrl.8 for ; Wed, 22 Jul 2020 05:25:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=LIqEF5U4TnVEe330KJwtprkLL0xQf+/ytCugRQTLG9M=; b=hRA+CHXEuJdPo6FjMqqzr3b5MC+X4cPlUzTWAYTsbBZQz95Ke4o06MZsDfqJYiYFC2 DgGdOLfwHGeIF2mcdA9jmPcuYn0mmzZNRMPEybQMFpDUhylnVmL6ezeEKBzrZRixq4Ge ZDG9i5hD1atmcjok8d/MTGFUwL+Cpg70Kq/glHa3PBRm2iKVa2xoSNB7WFnwvqhJn2B+ ZBlW9B2Q+Dzksa9SK6rGF94UCC2tr8si59uzzatkn3zF8DnUJUOoJ6H9RjpCqiKFk4wK 6iPUE/N/utC0iUrcVFKgNA6G4KRjj4NGzgsWdv8JPm48DyHYIgFETN4JB41woPXARvjE Dlww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=LIqEF5U4TnVEe330KJwtprkLL0xQf+/ytCugRQTLG9M=; b=GRc0vjuB5dcnOyZ1LvAIIgbL5Hz6Iqardb14xq8evwZwcleWwtFBoMf8PHvaXXgWBm Q68W1OSspXyfndoujGnV73c/6xOzziOKttbWKSgrjBNdZRh8epl3FK+IQ4r/FKKi81Nr URUHZdUqlLJDj3EAoxLo0wOuFMs9AsDl9fgQJpg9TxAqaOx+ikbxAfmJLDu3zLWbDtdr LIRXFaQdq9nCuemdOiMpi7jDHBt3KhxtvUhje/Xhz8cECumHLkiBVZ2ONd4EKqPw3raa Y7gXsgmgKEItvo5K9HjEg1sKWM65M8z51QvmkYhHQJ50gzVRBpeYDKWSuUWezdi9ighS 42/g== X-Gm-Message-State: AOAM5310cWMbpc7UvutsZshHlSW2bksLpMlbRSnJH8zWVil+3xxqCbZD uPig4HJb1jX+PrZkdLmOV/agVw== X-Google-Smtp-Source: ABdhPJwNFzQuP6bqc6wqIqFcVD4JgOokMyYqMjyYMmAhyLzE34x2eJV5VEg3IpvRBlPB5Hn5HgY6rQ== X-Received: by 2002:adf:a34f:: with SMTP id d15mr13601594wrb.281.1595420702543; Wed, 22 Jul 2020 05:25:02 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id e5sm25487369wrc.37.2020.07.22.05.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 05:25:02 -0700 (PDT) Date: Wed, 22 Jul 2020 13:25:00 +0100 From: "Leif Lindholm" To: Thomas Abraham Cc: devel@edk2.groups.io, pranav.madhu@arm.com, Ard Biesheuvel Subject: Re: [edk2-devel] [edk2-platforms][PATCH v4 2/5] Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib Message-ID: <20200722122500.GC1337@vanye> References: <1595148523-22302-1-git-send-email-pranav.madhu@arm.com> <1595148523-22302-3-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jul 21, 2020 at 23:53:36 +0530, Thomas Abraham wrote: > Hi Pranav, > > On Sun, Jul 19, 2020 at 2:19 PM Pranav Madhu wrote: > > > > From: Deepak Pandey > > > > A slave error is generated when host accesses the config space of > > non-available device or unimplemented function on a given bus. So > > implement a Neoverse N1 SoC specific PciExpressLib library with a > > workaround to return 0xffffffff for all such access. > > > > This library is inherited from MdePkg/Library/BasePciExpressLib and > > based on commit 9344f0921518 of that library in the tianocore/edk2 > > project. > > > > In addition to this, the Neoverse N1 SoC has two other limitations which > > affect the access to the PCIe root port: > > 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is > > isolated from rest of the downstream hierarchy ECAM space. > > 2. Root port ECAM space is not capable of 8bit/16bit writes. > > This library includes workaround for these limitations as well. > > > > Cc: Ard Biesheuvel > > Cc: Leif Lindholm > > Signed-off-by: Pranav Madhu > > --- > > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 4 + > > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf | 56 + > > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c | 1589 ++++++++++++++++++++ > > 3 files changed, 1649 insertions(+) > > > > <...> > > > +UINT8 > > +EFIAPI > > +PciExpressWrite8 ( > > + IN UINTN Address, > > + IN UINT8 Value > > + ) > > +{ > > + UINT8 Bus, Device, Function; > > + UINT8 Offset; > > + UINT32 Data; > > + > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > + > > + Bus = GET_BUS_NUM (Address); > > + Device = GET_DEV_NUM (Address); > > + Function = GET_FUNC_NUM (Address); > > + > > + // > > + // 8-bit and 16-bit writes to root port config space is not supported due to > > + // a hardware limitation. As a workaround, perform a read-update-write > > + // sequence on the whole 32-bit word of the root port config register such > > + // that only the specified 8-bits of that word are updated. > > + // > > + if ((Bus == 0) && (Device == 0) && (Function == 0)) { > > + Offset = Address & 0x3; > > + Address &= 0xFFFFFFFC; > > + Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address)); > > nit: There should have been a space before the GetPciExpressAddress. > This is inconsistent with the rest of the file. Actually, this is the correct way around. If the rest of the file is different, that is what should change. Regards, Leif > > Thanks, > Thomas. > > <...>