From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by mx.groups.io with SMTP id smtpd.web12.2265.1595615864846749280 for ; Fri, 24 Jul 2020 11:37:45 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=sthl+KUD; spf=pass (domain: nuviainc.com, ip: 209.85.221.66, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f66.google.com with SMTP id f18so9179511wrs.0 for ; Fri, 24 Jul 2020 11:37:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=/nzcWHaKyM71z/I7eB3Ib4W7uQpSs6bqj8xLmSpA5XE=; b=sthl+KUD2f4au9tc+n1NCC9TYpSGZX11/oNprHUTA8Q56eSwwgXc7D0Pb42DZf9pIP lx+0tozmVKmXF7PrsM/K9fVMsdscj/4EiEWe5IUa92uhNVYkBlQRuX3QlW7LEilsGOxd +qIIMkzzT6WByTyApomYWaUT0brobw5+x21vTi5SYEVbcAitNvwshBly94cm1LMjK+Kc CZvw7TV2JYj9LYey68wmivhT3A1NINy+FuBEAwv3c/3381wBDrGE1MCaZ55B1RLMEWVP mI35wsIXO6JmktgPrgdkoNP9RblfFUssRnb+QwKQ6T5ZLe1egigLxc3SiSMahCd8jfE+ Fs0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=/nzcWHaKyM71z/I7eB3Ib4W7uQpSs6bqj8xLmSpA5XE=; b=nNjjer4c83cGo0g7F+OgL1u1KiTHSS6wXTxGyK3UsrUD+GR2BQkCazm12D9HxzZ6v9 LNgJEAv3movRtI+DEB2tXmCaPu5dpA+F7+/FjuXIDGF9ulNyeUo4WEgYeOLV3eC8iSh0 7fhZIPnc+N+k6d63mIimdN1eZ7V3mvQsrnkCyIgjjPUhrqQRUMcNJ61XF7THkbzU9Tik eSeiJluLu34LO1Ik5MuGUd1AdSjH59FzoTxr2tup5P+hXCUWy+ojJ721MoIBf+iVb+4w 1w4IPVYRvcflRUW0TlNwikSlMNolVZ1U1pJyORkAfIDpTeh0zUSvZdgqUUvCrItKA454 WZUg== X-Gm-Message-State: AOAM532aqsVWZ4HZtbB33rBJXLiGjGdgFo8r4ED8TiIGeOBCuzuX5LJL gj6LwFXLowUwKMfvreJ01rpx3Q== X-Google-Smtp-Source: ABdhPJxLD60oomo2F7pCZRLqdRykos11KTJknguJaTmPqPSEEVWrcWPHPXwLd3Rp4DvYW86p8FeOOA== X-Received: by 2002:a05:6000:118c:: with SMTP id g12mr9585003wrx.212.1595615861480; Fri, 24 Jul 2020 11:37:41 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id n189sm8267554wmf.38.2020.07.24.11.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2020 11:37:40 -0700 (PDT) Date: Fri, 24 Jul 2020 19:37:38 +0100 From: "Leif Lindholm" To: Pranav Madhu Cc: devel@edk2.groups.io, Ard Biesheuvel Subject: Re: [edk2-platforms][PATCH v5 2/5] Silicon/ARM/N1SoC: Implement Neoverse N1 SoC specific PciExpressLib Message-ID: <20200724183738.GW1337@vanye> References: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> <1595431524-13782-3-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 In-Reply-To: <1595431524-13782-3-git-send-email-pranav.madhu@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jul 22, 2020 at 20:55:21 +0530, Pranav Madhu wrote: > From: Deepak Pandey > > A slave error is generated when host accesses the config space of > non-available device or unimplemented function on a given bus. So > implement a Neoverse N1 SoC specific PciExpressLib library with a > workaround to return 0xffffffff for all such access. > > This library is inherited from MdePkg/Library/BasePciExpressLib and > based on commit 9344f0921518 of that library in the tianocore/edk2 > project. > > In addition to this, the Neoverse N1 SoC has two other limitations which > affect the access to the PCIe root port: > 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is > isolated from rest of the downstream hierarchy ECAM space. > 2. Root port ECAM space is not capable of 8bit/16bit writes. > This library includes workaround for these limitations as well. > > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Signed-off-by: Pranav Madhu This is a *massive* improvement. I can easily verify what has been changed compared to the original, and I am confident I will be able to do the same in the future. The added comments mean even when I've forgotten what this works around, I have that information right in front of me if I need to review modifications in the future. Good work! Reviewed-by: Leif Lindholm > --- > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 4 + > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf | 56 + > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c | 1589 ++++++++++++++++++++ > 3 files changed, 1649 insertions(+) > > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > index dba49e6489c0..491806b81be9 100644 > --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > @@ -25,3 +25,7 @@ [Guids.common] > [PcdsFixedAtBuild] > # Secondary DDR memory > gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 > + > + #PCIe > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000002 > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000003 > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf > new file mode 100644 > index 000000000000..acb6fb62197f > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf > @@ -0,0 +1,56 @@ > +## @file > +# Instance of PCI Express Library using the 256 MB PCI Express MMIO window. > +# > +# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform > +# PCI Configuration cycles. Layers on top of an I/O Library instance. > +# > +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. > +# > +# This library is inherited from MdePkg/Library/BasePciExpressLib. On > +# NeoverseN1 SoC, with the unmodified version of this library, a slave error is > +# generated when host accesses the config space of a non-available device or > +# unimplemented function on a given bus. In order to resolve this for > +# NeoverseN1 SoC, a modified version of the MdePkg/Library/BasePciExpressLib > +# library is used. The modification includes a check to determine whether the > +# incoming PCI address can be safely accessed. > +# > +# In addition to this, the NeoverseN1 SoC has two other limitations which > +# affect the access to the PCIe root port: > +# 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated > +# from rest of the downstream hierarchy ECAM space. > +# 2. Root port ECAM space is not capable of 8bit/16bit writes. > +# This library includes workaround for these limitations as well. > +# > +# Copyright (c) 2020, ARM Limited. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = BasePciExpressLib > + FILE_GUID = b378dd06-de7f-4e8c-8fb0-5126adfb34bf > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciExpressLib > + > +[Sources] > + PciExpressLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > + > +[FixedPcd] > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize > + > +[LibraryClasses] > + BaseLib > + DebugLib > + IoLib > + PcdLib > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c > new file mode 100644 > index 000000000000..bb0246b4a9e7 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c > @@ -0,0 +1,1589 @@ > +/** @file > + Functions in this library instance make use of MMIO functions in IoLib to > + access memory mapped PCI configuration space. > + > + All assertions for I/O operations are handled in MMIO functions in the IoLib > + Library. > + > + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> + > + On the NeoverseN1Soc, a slave error is generated when host accesses the > + configuration space of non-available device or unimplemented function on a > + given bus. So this library introduces a workaround using IsBdfValid(), > + to return 0xFFFFFFFF for all such access. > + > + In addition to this, the hardware has two other limitations which affect > + access to the PCIe root port: > + 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated > + from rest of the downstream hierarchy ECAM space. > + 2. Root port ECAM space is not capable of 8bit/16bit writes. > + The description of the workarounds included for these limitations can > + be found in the comments below. > + > + Copyright (c) 2020, ARM Limited. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Assert the validity of a PCI address. A valid PCI address should contain 1's > + only in the low 28 bits. > + > + @param A The address to validate. > + > +**/ > +#define ASSERT_INVALID_PCI_ADDRESS(A) \ > + ASSERT (((A) & ~0xfffffff) == 0) > + > +/* Root port Entry, BDF Entries Count */ > +#define BDF_TABLE_ENTRY_SIZE 4 > +#define BDF_TABLE_HEADER_COUNT 2 > +#define BDF_TABLE_HEADER_SIZE 8 > + > +/* BDF table offsets for PCIe */ > +#define PCIE_BDF_TABLE_OFFSET 0 > + > +#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F) > +#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F) > +#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07) > +#define GET_REG_NUM(Address) ((Address) & 0xFFF) > + > +/** > + BDF Table structure : (Header + BDF Entries) > + -------------------------------------------- > + [Offset 0x00] ROOT PORT ADDRESS > + [Offset 0x04] BDF ENTRIES COUNT > + [Offset 0x08] BDF ENTRY 0 > + [Offset 0x0C] BDF ENTRY 1 > + [Offset 0x10] BDF ENTRY 2 > + [Offset 0x14] BDF ENTRY 3 > + [Offset 0x18] BDF ENTRY 4 > + ... > + [Offset 0x--] BDF ENTRY N > + -------------------------------------------- > +**/ > + > +/** > + Value returned for reads on configuration space of unimplemented > + device functions. > +**/ > +STATIC UINTN mDummyConfigData = 0xFFFFFFFF; > + > +/** > + Registers a PCI device so PCI configuration registers may be accessed after > + SetVirtualAddressMap(). > + > + Registers the PCI device specified by Address so all the PCI configuration > + registers associated with that PCI device may be accessed after SetVirtualAddressMap() > + is called. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @retval RETURN_SUCCESS The PCI device was registered for runtime access. > + @retval RETURN_UNSUPPORTED An attempt was made to call this function > + after ExitBootServices(). > + @retval RETURN_UNSUPPORTED The resources required to access the PCI device > + at runtime could not be mapped. > + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to > + complete the registration. > + > +**/ > +RETURN_STATUS > +EFIAPI > +PciExpressRegisterForRuntimeAccess ( > + IN UINTN Address > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return RETURN_UNSUPPORTED; > +} > + > +/** > + Check if the requested PCI address can be safely accessed. > + > + SCP performs the initial bus scan, prepares a table of valid BDF addresses > + and shares them through non-trusted SRAM. This function validates if the > + requested PCI address belongs to a valid BDF by checking the table of valid > + entries. If not, this function will return false. This is a workaround to > + avoid bus fault that occurs when accessing unavailable PCI device due to > + hardware bug. > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @return TRUE BDF can be accessed, valid. > + @return FALSE BDF should not be accessed, invalid. > + > +**/ > +STATIC > +BOOLEAN > +IsBdfValid ( > + IN UINTN Address > + ) > +{ > + UINTN BdfCount; > + UINTN BdfValue; > + UINTN BdfEntry; > + UINTN Count; > + UINTN TableBase; > + UINTN ConfigBase; > + > + ConfigBase = Address & ~0xFFF; > + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; > + BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); > + BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE; > + > + /* Skip the header & check remaining entry */ > + for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) { > + BdfValue = MmioRead32 (BdfEntry); > + if (BdfValue == ConfigBase) { > + return TRUE; > + } > + } > + > + return FALSE; > +} > + > +/** > + Get the physical address of a configuration space register. > + > + Implement a workaround to avoid generation of slave errors from the bus. That > + is, retrieve the PCI Express Base Address via a PCD entry, add the incomming > + address with that base address and check whether this converted address > + points to a accessible BDF. If it is not accessible, return the address > + of a dummy location so that a read from it does not cause a slave error. > + > + In addition to this, implement a workaround for accessing the root port's > + configuration space. The root port configuration space is not contiguous > + with the rest of the downstream hierarchy configuration space. So determine > + whether the specified address is for the root port and use a different base > + address for it. > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @return Physical address of the configuration register that corresponds to the > + PCI configuration register specified by input parameter 'Address'. > + > +**/ > +STATIC > +VOID* > +GetPciExpressAddress ( > + IN UINTN Address > + ) > +{ > + UINT8 Bus, Device, Function; > + UINTN ConfigAddress; > + > + Bus = GET_BUS_NUM (Address); > + Device = GET_DEV_NUM (Address); > + Function = GET_FUNC_NUM (Address); > + > + if ((Bus == 0) && (Device == 0) && (Function == 0)) { > + ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address; > + } else { > + ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address; > + if (!IsBdfValid(Address)) { > + ConfigAddress = (UINTN)&mDummyConfigData; > + } > + } > + > + return (VOID *)ConfigAddress; > +} > + > +/** > + Reads an 8-bit PCI configuration register. > + > + Reads and returns the 8-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations are > + serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @return The read value from the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressRead8 ( > + IN UINTN Address > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioRead8 ((UINTN)GetPciExpressAddress (Address)); > +} > + > +/** > + Writes an 8-bit PCI configuration register. > + > + Writes the 8-bit PCI configuration register specified by Address with the > + value specified by Value. Value is returned. This function must guarantee > + that all PCI read and write operations are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param Value The value to write. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressWrite8 ( > + IN UINTN Address, > + IN UINT8 Value > + ) > +{ > + UINT8 Bus, Device, Function; > + UINT8 Offset; > + UINT32 Data; > + > + ASSERT_INVALID_PCI_ADDRESS (Address); > + > + Bus = GET_BUS_NUM (Address); > + Device = GET_DEV_NUM (Address); > + Function = GET_FUNC_NUM (Address); > + > + // > + // 8-bit and 16-bit writes to root port config space is not supported due to > + // a hardware limitation. As a workaround, perform a read-update-write > + // sequence on the whole 32-bit word of the root port config register such > + // that only the specified 8-bits of that word are updated. > + // > + if ((Bus == 0) && (Device == 0) && (Function == 0)) { > + Offset = Address & 0x3; > + Address &= 0xFFFFFFFC; > + Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address)); > + Data &= ~(0xFF << (8 * Offset)); > + Data |= (Value << (8 * Offset)); > + MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data); > + return Value; > + } > + > + return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value); > +} > + > +/** > + Performs a bitwise OR of an 8-bit PCI configuration register with > + an 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 8-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressOr8 ( > + IN UINTN Address, > + IN UINT8 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData); > +} > + > +/** > + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit > + value. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 8-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressAnd8 ( > + IN UINTN Address, > + IN UINT8 AndData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData); > +} > + > +/** > + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit > + value, followed a bitwise OR with another 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, > + performs a bitwise OR between the result of the AND operation and > + the value specified by OrData, and writes the result to the 8-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressAndThenOr8 ( > + IN UINTN Address, > + IN UINT8 AndData, > + IN UINT8 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioAndThenOr8 ( > + (UINTN)GetPciExpressAddress (Address), > + AndData, > + OrData > + ); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in an 8-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param Address The PCI configuration register to read. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressBitFieldRead8 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldRead8 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit > + ); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 8-bit register is returned. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressBitFieldWrite8 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 Value > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldWrite8 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + Value > + ); > +} > + > +/** > + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 8-bit port. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 8-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. Extra left bits in OrData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressBitFieldOr8 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldOr8 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + OrData > + ); > +} > + > +/** > + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise > + AND, and writes the result back to the bit field in the 8-bit register. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 8-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. Extra left bits in AndData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressBitFieldAnd8 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 AndData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldAnd8 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + AndData > + ); > +} > + > +/** > + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 8-bit port. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 8-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciExpressBitFieldAndThenOr8 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 AndData, > + IN UINT8 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldAndThenOr8 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + AndData, > + OrData > + ); > +} > + > +/** > + Reads a 16-bit PCI configuration register. > + > + Reads and returns the 16-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations are > + serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @return The read value from the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressRead16 ( > + IN UINTN Address > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioRead16 ((UINTN)GetPciExpressAddress (Address)); > +} > + > +/** > + Writes a 16-bit PCI configuration register. > + > + Writes the 16-bit PCI configuration register specified by Address with the > + value specified by Value. Value is returned. This function must guarantee > + that all PCI read and write operations are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param Value The value to write. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressWrite16 ( > + IN UINTN Address, > + IN UINT16 Value > + ) > +{ > + UINT8 Bus, Device, Function; > + UINT8 Offset; > + UINT32 Data; > + > + ASSERT_INVALID_PCI_ADDRESS (Address); > + > + Bus = GET_BUS_NUM (Address); > + Device = GET_DEV_NUM (Address); > + Function = GET_FUNC_NUM (Address); > + > + // > + // 8-bit and 16-bit writes to root port config space is not supported due to > + // a hardware limitation. As a workaround, perform a read-update-write > + // sequence on the whole 32-bit word of the root port config register such > + // that only the specified 16-bits of that word are updated. > + // > + if ((Bus == 0) && (Device == 0) && (Function == 0)) { > + Offset = Address & 0x3; > + Address &= 0xFFFFFFFC; > + Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address)); > + Data &= ~(0xFFFF << (8 * Offset)); > + Data |= (Value << (8 * Offset)); > + MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data); > + return Value; > + } > + > + return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value); > +} > + > +/** > + Performs a bitwise OR of a 16-bit PCI configuration register with > + a 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 16-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressOr16 ( > + IN UINTN Address, > + IN UINT16 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData); > +} > + > +/** > + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit > + value. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 16-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressAnd16 ( > + IN UINTN Address, > + IN UINT16 AndData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData); > +} > + > +/** > + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit > + value, followed a bitwise OR with another 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, > + performs a bitwise OR between the result of the AND operation and > + the value specified by OrData, and writes the result to the 16-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressAndThenOr16 ( > + IN UINTN Address, > + IN UINT16 AndData, > + IN UINT16 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioAndThenOr16 ( > + (UINTN)GetPciExpressAddress (Address), > + AndData, > + OrData > + ); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in a 16-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param Address The PCI configuration register to read. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressBitFieldRead16 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldRead16 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit > + ); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 16-bit register is returned. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressBitFieldWrite16 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 Value > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldWrite16 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + Value > + ); > +} > + > +/** > + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 16-bit port. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 16-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. Extra left bits in OrData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressBitFieldOr16 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldOr16 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + OrData > + ); > +} > + > +/** > + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise > + AND, and writes the result back to the bit field in the 16-bit register. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 16-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. Extra left bits in AndData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressBitFieldAnd16 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 AndData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldAnd16 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + AndData > + ); > +} > + > +/** > + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 16-bit port. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 16-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciExpressBitFieldAndThenOr16 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 AndData, > + IN UINT16 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldAndThenOr16 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + AndData, > + OrData > + ); > +} > + > +/** > + Reads a 32-bit PCI configuration register. > + > + Reads and returns the 32-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations are > + serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @return The read value from the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressRead32 ( > + IN UINTN Address > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioRead32 ((UINTN)GetPciExpressAddress (Address)); > +} > + > +/** > + Writes a 32-bit PCI configuration register. > + > + Writes the 32-bit PCI configuration register specified by Address with the > + value specified by Value. Value is returned. This function must guarantee > + that all PCI read and write operations are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param Value The value to write. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressWrite32 ( > + IN UINTN Address, > + IN UINT32 Value > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value); > +} > + > +/** > + Performs a bitwise OR of a 32-bit PCI configuration register with > + a 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 32-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressOr32 ( > + IN UINTN Address, > + IN UINT32 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData); > +} > + > +/** > + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit > + value. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 32-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressAnd32 ( > + IN UINTN Address, > + IN UINT32 AndData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData); > +} > + > +/** > + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit > + value, followed a bitwise OR with another 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, > + performs a bitwise OR between the result of the AND operation and > + the value specified by OrData, and writes the result to the 32-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressAndThenOr32 ( > + IN UINTN Address, > + IN UINT32 AndData, > + IN UINT32 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioAndThenOr32 ( > + (UINTN)GetPciExpressAddress (Address), > + AndData, > + OrData > + ); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in a 32-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param Address The PCI configuration register to read. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressBitFieldRead32 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldRead32 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit > + ); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 32-bit register is returned. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressBitFieldWrite32 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 Value > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldWrite32 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + Value > + ); > +} > + > +/** > + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 32-bit port. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 32-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. Extra left bits in OrData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressBitFieldOr32 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldOr32 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + OrData > + ); > +} > + > +/** > + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise > + AND, and writes the result back to the bit field in the 32-bit register. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 32-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. Extra left bits in AndData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressBitFieldAnd32 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 AndData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldAnd32 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + AndData > + ); > +} > + > +/** > + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 32-bit port. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 32-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + If Address > 0x0FFFFFFF, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param Address The PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciExpressBitFieldAndThenOr32 ( > + IN UINTN Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 AndData, > + IN UINT32 OrData > + ) > +{ > + ASSERT_INVALID_PCI_ADDRESS (Address); > + return MmioBitFieldAndThenOr32 ( > + (UINTN)GetPciExpressAddress (Address), > + StartBit, > + EndBit, > + AndData, > + OrData > + ); > +} > + > +/** > + Reads a range of PCI configuration registers into a caller supplied buffer. > + > + Reads the range of PCI configuration registers specified by StartAddress and > + Size into the buffer specified by Buffer. This function only allows the PCI > + configuration registers from a single PCI function to be read. Size is > + returned. When possible 32-bit PCI configuration read cycles are used to read > + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit > + and 16-bit PCI configuration read cycles may be used at the beginning and the > + end of the range. > + > + If StartAddress > 0x0FFFFFFF, then ASSERT(). > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > + If Size > 0 and Buffer is NULL, then ASSERT(). > + > + @param StartAddress The starting address that encodes the PCI Bus, Device, > + Function and Register. > + @param Size The size in bytes of the transfer. > + @param Buffer The pointer to a buffer receiving the data read. > + > + @return Size read data from StartAddress. > + > +**/ > +UINTN > +EFIAPI > +PciExpressReadBuffer ( > + IN UINTN StartAddress, > + IN UINTN Size, > + OUT VOID *Buffer > + ) > +{ > + UINTN ReturnValue; > + > + ASSERT_INVALID_PCI_ADDRESS (StartAddress); > + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); > + > + if (Size == 0) { > + return Size; > + } > + > + ASSERT (Buffer != NULL); > + > + // > + // Save Size for return > + // > + ReturnValue = Size; > + > + if ((StartAddress & 1) != 0) { > + // > + // Read a byte if StartAddress is byte aligned > + // > + *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress); > + StartAddress += sizeof (UINT8); > + Size -= sizeof (UINT8); > + Buffer = (UINT8*)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { > + // > + // Read a word if StartAddress is word aligned > + // > + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress)); > + > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16*)Buffer + 1; > + } > + > + while (Size >= sizeof (UINT32)) { > + // > + // Read as many double words as possible > + // > + WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress)); > + > + StartAddress += sizeof (UINT32); > + Size -= sizeof (UINT32); > + Buffer = (UINT32*)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16)) { > + // > + // Read the last remaining word if exist > + // > + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16*)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT8)) { > + // > + // Read the last remaining byte if exist > + // > + *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress); > + } > + > + return ReturnValue; > +} > + > +/** > + Copies the data in a caller supplied buffer to a specified range of PCI > + configuration space. > + > + Writes the range of PCI configuration registers specified by StartAddress and > + Size from the buffer specified by Buffer. This function only allows the PCI > + configuration registers from a single PCI function to be written. Size is > + returned. When possible 32-bit PCI configuration write cycles are used to > + write from StartAdress to StartAddress + Size. Due to alignment restrictions, > + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning > + and the end of the range. > + > + If StartAddress > 0x0FFFFFFF, then ASSERT(). > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > + If Size > 0 and Buffer is NULL, then ASSERT(). > + > + @param StartAddress The starting address that encodes the PCI Bus, Device, > + Function and Register. > + @param Size The size in bytes of the transfer. > + @param Buffer The pointer to a buffer containing the data to write. > + > + @return Size written to StartAddress. > + > +**/ > +UINTN > +EFIAPI > +PciExpressWriteBuffer ( > + IN UINTN StartAddress, > + IN UINTN Size, > + IN VOID *Buffer > + ) > +{ > + UINTN ReturnValue; > + > + ASSERT_INVALID_PCI_ADDRESS (StartAddress); > + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); > + > + if (Size == 0) { > + return 0; > + } > + > + ASSERT (Buffer != NULL); > + > + // > + // Save Size for return > + // > + ReturnValue = Size; > + > + if ((StartAddress & 1) != 0) { > + // > + // Write a byte if StartAddress is byte aligned > + // > + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); > + StartAddress += sizeof (UINT8); > + Size -= sizeof (UINT8); > + Buffer = (UINT8*)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { > + // > + // Write a word if StartAddress is word aligned > + // > + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16*)Buffer + 1; > + } > + > + while (Size >= sizeof (UINT32)) { > + // > + // Write as many double words as possible > + // > + PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer)); > + StartAddress += sizeof (UINT32); > + Size -= sizeof (UINT32); > + Buffer = (UINT32*)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16)) { > + // > + // Write the last remaining word if exist > + // > + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16*)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT8)) { > + // > + // Write the last remaining byte if exist > + // > + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); > + } > + > + return ReturnValue; > +} > -- > 2.7.4 >