From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by mx.groups.io with SMTP id smtpd.web10.2298.1595616216699386913 for ; Fri, 24 Jul 2020 11:43:37 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=mojb3x3e; spf=pass (domain: nuviainc.com, ip: 209.85.221.67, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f67.google.com with SMTP id f7so9190304wrw.1 for ; Fri, 24 Jul 2020 11:43:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=zrkdduDz6NVIQyM8bqAGiYV++wpJaqjC9vOB5jCiRkc=; b=mojb3x3eE4NrkhrGHjhn5L0xxhPHbghBG4AyKXXSUvtrueIbfHrMo001wkxjnEohCT CVF+97Ok9EkQ+7d09HTKjhuwK6E3dtqOL8Yxfx+3dvcEWqIDe6EFKLox++TBdMUsZ+ym sGq4HJ3y+akOdSmU3QPc78dlZTA3fnYqRqKRvJYEVlY+K37FfAYikwgMnUWCTxItrG9Z f7BUUdVsCQ0i2lkU2itiqIr3pafQ3AVGbeAnvY5DvovU2FqvjHi8agRh8Sx78fOsmSNk lkqEsXLzTaC9xtPZAtviUFXYVwZrl1x/uV6Z8jTjJsuUEQ/63cRXCTwhbCXqHe0MtlUR mzSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=zrkdduDz6NVIQyM8bqAGiYV++wpJaqjC9vOB5jCiRkc=; b=OpcbDDg9jxhuZdYT5MPAH7r5GrsYFp6Qqajr6GGsR35SyEm8OsRROaioAg7Jt5CcTj ayau6xzdpxI4dcyDQGoRIWdEQJJHzC0V9ZsKP1D9dtfl3h+whalaHSsHE0bpsO17i3R6 upoAy0O83k5DAbLInyG3It3N0jxKpeSip+OyIQlhiEAc3S0ljh4pPNIPE0OFydBxB/jd ko/5SrGmsX3WneQ4QLhDOF3rUATznRgepM+1AU0J3uLVP/fP9UnI1nE9+aZW3rJMIK2p vH7SZl6ck0KURkLI+57+aj8Pxgtky3vbPyhZCJVbSFtwe6PcDtYMiy9LLpklYWpNWfcu zZTg== X-Gm-Message-State: AOAM532E1aYQfZyhoCVSbmHXHkcl44XrX3aE3haDYsTbGpoocvX87b/z 69jEjrH1b65onkCwIfOEIaph0A== X-Google-Smtp-Source: ABdhPJwsU/2Nyn2z+EOnqK3xBmGwyT6OzGLZaOjXGOJ3RSbWY2C4vy/RbOwmZ+CtcKjvCPp0u0qfqw== X-Received: by 2002:a5d:4906:: with SMTP id x6mr10151179wrq.142.1595616215306; Fri, 24 Jul 2020 11:43:35 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id b63sm8367321wme.41.2020.07.24.11.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2020 11:43:33 -0700 (PDT) Date: Fri, 24 Jul 2020 19:43:32 +0100 From: "Leif Lindholm" To: Pranav Madhu Cc: devel@edk2.groups.io, Ard Biesheuvel Subject: Re: [edk2-platforms][PATCH v5 0/5] Add initial support for N1SDP board Message-ID: <20200724184332.GX1337@vanye> References: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 In-Reply-To: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline For the whole series: Reviewed-by: Leif Lindholm Pushed as 7de21b6aa3e0..a8eecf187198. Thanks! On Wed, Jul 22, 2020 at 20:55:19 +0530, Pranav Madhu wrote: > Changes since v4: > - Updated indents and spacing, functionally same as v4. > > Changes since v3: > - Addressed all the comments from Leif. As part of the clean up that > resulted from addressing the comments, some of the comments where not > applicable anymore (due to fragments of code that had comments were > removed during cleanup). > - Included detailed description of the workarounds applied to the > Neoverse N1 SoC specific PciExpressLib library. > - Updated Maintainers.txt to add Silicon/ARM/ directory under ARM entry. > - Picked up Leif's Reviewed-by tag for the 4th patch of this series. > - Addressed all the comments from Ard. > > Changes since v2: > - Addressed comments from Thomas. > - Renamed Silicon/ARM/N1SDP to Silicon/ARM/NeoverseN1Soc. > > Changes since v1: > - Addressed comments from Ard. > - Split the code between Silicon and Platform directories. > > Arm's N1SDP is a Arm v8.2-A Neoverse N1 CPU based reference design platform > primariliy intended for development on Arm64 based platform. This patch series > adds initial support for Arm's Neoverse N1 SoC and platform support for the > N1SDP board. > > The first patch in this series adds the platform libary implementation. The > second patch adds a custom implementation of the PciExpressLib due to a PCIe > integration issue which results in all config space accesses to non-existing > BDFs resulting in a Serror (bus abort). To avoid this, the N1SDP specific > PciExpressLib implementation provides a workaround for this issue. The third > patch in this series adds the platform library for the PciHostBridge. The > fourth patch adds the initial platform support for the N1SDP platform. The > fifth patch adds Silicon/ARM/ to ARM entry in maintainers file. > > Deepak Pandey (4): > Silicon/ARM/N1SoC: Add platform library implementation > Silicon/ARM/N1SoC: Implement Neoverse N1 SoC specific PciExpressLib > Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library > Platform/ARM/N1SDP: Add initial N1SDP platform support > > Pranav Madhu (1): > Maintainers.txt: Add Silicon/ARM directory > > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 46 + > Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 245 +++ > Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 294 ++++ > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf | 56 + > Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 49 + > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 54 + > Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 66 + > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c | 1589 ++++++++++++++++++++ > Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c | 184 +++ > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 67 + > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 151 ++ > Maintainers.txt | 1 + > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S | 84 ++ > 13 files changed, 2886 insertions(+) > create mode 100644 Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.dsc > create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.fdf > create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf > create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf > create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > create mode 100644 Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h > create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c > create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c > create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S > > -- > 2.7.4 >