From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f195.google.com (mail-qk1-f195.google.com [209.85.222.195]) by mx.groups.io with SMTP id smtpd.web10.51156.1595837938663284110 for ; Mon, 27 Jul 2020 01:18:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@9elements.com header.s=google header.b=a7EgrUzj; spf=pass (domain: 9elements.com, ip: 209.85.222.195, mailfrom: marcello.bauer@9elements.com) Received: by mail-qk1-f195.google.com with SMTP id d14so14453549qke.13 for ; Mon, 27 Jul 2020 01:18:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=9elements.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8nPmj68JsSEIfFeLREB5UzXQ3cfRAAtCOsiXCliPRbM=; b=a7EgrUzjAdD4WXKHrfmj3NIYjvlnjo5VGa8T0PYRM06hT50FfLVkZK/oUwEY0Cjl/1 NMdR4axggfy9GoJFqGYjibtvStBe9zZVM6HFVOVncd7vc/Vab4Ni7Rqt4mGgXFQMoWZJ Y5g85F/a0jFJvZNT2mS1QC0fLujhc3CQ3u6y3XdjNMoyn64OWnJ3qdX9jQeDrVzCcEx8 yfJQ/riPv9zmIFXJ7BcyNiVQi7n9jfTQgdOirSV3zNdlSRonmdxRn06qtfu7Ec6hdc6m 1ivZwpyTpOcWM4R7cWwcljOMpAsIGahoM8DIgj46fDqV5mgGeOv8wipIIbWP4uCZMPXv scOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8nPmj68JsSEIfFeLREB5UzXQ3cfRAAtCOsiXCliPRbM=; b=W0Qs8p0+VI+DnpCzC2JhyD2G26o8NeQOnJF++lBGKSO1b2lA5ONL3bK+3Z7op8Tz0R WFGSTxedFEJ4BKprpeP6d4/b3s+R2vNhDaj0DUkSJV5xDLxKhAhvSZeOavg7jT2DrfcQ mkfPdgRequfdn4+IDOIf5pJot0kUQN/HNYeYfKJZUDt45x013qKU7NTyjXfp8jECKE9t j48IBs5phfZoa7wsUMRnNW2URFpT0Pb5DeS8IbQ1gedCG0xkGhf0BNpOT1M3wv89koKp rBjiOKJMGhQfyJXV0xscrD6sHU2KbkOzANDWSUX18Wot7U83pWQAcKbfEg3h53KU8AET Rwcg== X-Gm-Message-State: AOAM530fGE8Vc/Py4soSQQOqm5jWSL09loHwF2vEXH8thtj4V/O8x+YT 6MTY9HjHAyQ68AWSKktCGlzyBX8LqD4= X-Google-Smtp-Source: ABdhPJyplMuS45+u8v998eLSbx/0u/yvWU+ghBhK5TDheQg18/MABFJEOdUPb4RTeSCTb6DVeqhO9Q== X-Received: by 2002:a37:a982:: with SMTP id s124mr21464505qke.171.1595837937567; Mon, 27 Jul 2020 01:18:57 -0700 (PDT) Return-Path: Received: from T14.n1ce.space ([2a02:908:e851:d750:39c4:c509:9b27:775a]) by smtp.gmail.com with ESMTPSA id m4sm14413550qtf.43.2020.07.27.01.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 01:18:55 -0700 (PDT) From: "Marcello Sylvester Bauer" To: devel@edk2.groups.io Cc: Patrick Rudolph , Christian Walter , Michael D Kinney , Liming Gao Subject: [PATCH v4 2/3] MdePkg/BasePciExpressLib: Support variable size MMCONF Date: Mon, 27 Jul 2020 10:18:41 +0200 Message-Id: <20200727081842.28843-3-marcello.bauer@9elements.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200727081842.28843-1-marcello.bauer@9elements.com> References: <20200727081842.28843-1-marcello.bauer@9elements.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Add support for arbitrary sized MMCONF by introducing a new PCD. Signed-off-by: Patrick Rudolph Signed-off-by: Marcello Sylvester Bauer Cc: Patrick Rudolph Cc: Christian Walter Cc: Michael D Kinney Cc: Liming Gao --- MdePkg/MdePkg.dec | 4 + MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf | 6 +- MdePkg/Include/Library/PciExpressLib.h | 5 +- MdePkg/Library/BasePciExpressLib/PciExpressLib.c | 216 +++++++++++++= ++++--- 4 files changed, 193 insertions(+), 38 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 73f6c2407357..812be75fb3b2 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynami= c, PcdsDynamicEx] # @Prompt PCI Express Base Address.=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x00= 00000a=0D =0D + ## This value is used to set the size of PCI express hierarchy. The defa= ult is 256 MB.=0D + # @Prompt PCI Express Base Size.=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000|UINT64|0x00000= 00f=0D +=0D ## Default current ISO 639-2 language: English & French.=0D # @Prompt Default Value of LangCodes Variable.=0D gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|= VOID*|0x0000001c=0D diff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdePk= g/Library/BasePciExpressLib/BasePciExpressLib.inf index a7edb74cde71..12734b022ac7 100644 --- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf +++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf @@ -1,7 +1,7 @@ ## @file=0D -# Instance of PCI Express Library using the 256 MB PCI Express MMIO windo= w.=0D +# Instance of PCI Express Library using the variable size PCI Express MMI= O window.=0D #=0D -# PCI Express Library that uses the 256 MB PCI Express MMIO window to per= form=0D +# PCI Express Library that uses the variable size PCI Express MMIO window= to perform=0D # PCI Configuration cycles. Layers on top of an I/O Library instance.=0D #=0D # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= =0D @@ -38,4 +38,4 @@ [LibraryClasses] =0D [Pcd]=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES=0D -=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES=0D diff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Librar= y/PciExpressLib.h index 826fdcf7db6c..d78193a0a352 100644 --- a/MdePkg/Include/Library/PciExpressLib.h +++ b/MdePkg/Include/Library/PciExpressLib.h @@ -2,8 +2,9 @@ Provides services to access PCI Configuration Space using the MMIO PCI E= xpress window.=0D =0D This library is identical to the PCI Library, except the access method f= or performing PCI=0D - configuration cycles must be through the 256 MB PCI Express MMIO window = whose base address=0D - is defined by PcdPciExpressBaseAddress.=0D + configuration cycles must be through the PCI Express MMIO window whose b= ase address=0D + is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpress= BaseSize.=0D +=0D =0D Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D diff --git a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c b/MdePkg/Libr= ary/BasePciExpressLib/PciExpressLib.c index 99a166c3609b..0311ecb3025f 100644 --- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c +++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c @@ -22,7 +22,8 @@ =0D /**=0D Assert the validity of a PCI address. A valid PCI address should contain= 1's=0D - only in the low 28 bits.=0D + only in the low 28 bits. PcdPciExpressBaseSize limits the size to the re= al=0D + number of PCI busses in this segment.=0D =0D @param A The address to validate.=0D =0D @@ -79,6 +80,24 @@ GetPciExpressBaseAddress ( return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);=0D }=0D =0D +/**=0D + Gets the size of PCI Express.=0D +=0D + This internal functions retrieves PCI Express Base Size via a PCD entry= =0D + PcdPciExpressBaseSize.=0D +=0D + @return The base size of PCI Express.=0D +=0D +**/=0D +STATIC=0D +UINTN=0D +PcdPciExpressBaseSize (=0D + VOID=0D + )=0D +{=0D + return (UINTN) PcdGet64 (PcdPciExpressBaseSize);=0D +}=0D +=0D /**=0D Reads an 8-bit PCI configuration register.=0D =0D @@ -91,7 +110,8 @@ GetPciExpressBaseAddress ( @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D Register.=0D =0D - @return The read value from the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The read value from the PCI configuration register.=0D =0D **/=0D UINT8=0D @@ -101,6 +121,9 @@ PciExpressRead8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);=0D }=0D =0D @@ -117,7 +140,8 @@ PciExpressRead8 ( Register.=0D @param Value The value to write.=0D =0D - @return The value written to the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value written to the PCI configuration register.=0D =0D **/=0D UINT8=0D @@ -128,6 +152,9 @@ PciExpressWrite8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value)= ;=0D }=0D =0D @@ -148,7 +175,8 @@ PciExpressWrite8 ( Register.=0D @param OrData The value to OR with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value written to the PCI configuration register.=0D =0D **/=0D UINT8=0D @@ -159,6 +187,9 @@ PciExpressOr8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D }=0D =0D @@ -179,7 +210,8 @@ PciExpressOr8 ( Register.=0D @param AndData The value to AND with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register.= =0D =0D **/=0D UINT8=0D @@ -190,6 +222,9 @@ PciExpressAnd8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData)= ;=0D }=0D =0D @@ -212,7 +247,8 @@ PciExpressAnd8 ( @param AndData The value to AND with the PCI configuration register.=0D @param OrData The value to OR with the result of the AND operation.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register.= =0D =0D **/=0D UINT8=0D @@ -224,6 +260,9 @@ PciExpressAndThenOr8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioAndThenOr8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D AndData,=0D @@ -249,7 +288,9 @@ PciExpressAndThenOr8 ( @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D Range 0..7.=0D =0D - @return The value of the bit field read from the PCI configuration regis= ter.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value of the bit field read from the PCI configuration= =0D + register.=0D =0D **/=0D UINT8=0D @@ -261,6 +302,9 @@ PciExpressBitFieldRead8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldRead8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -289,7 +333,8 @@ PciExpressBitFieldRead8 ( Range 0..7.=0D @param Value The new value of the bit field.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register.= =0D =0D **/=0D UINT8=0D @@ -302,6 +347,9 @@ PciExpressBitFieldWrite8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldWrite8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -334,7 +382,8 @@ PciExpressBitFieldWrite8 ( Range 0..7.=0D @param OrData The value to OR with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register.= =0D =0D **/=0D UINT8=0D @@ -347,6 +396,9 @@ PciExpressBitFieldOr8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldOr8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -379,7 +431,8 @@ PciExpressBitFieldOr8 ( Range 0..7.=0D @param AndData The value to AND with the PCI configuration register.= =0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register.= =0D =0D **/=0D UINT8=0D @@ -392,6 +445,9 @@ PciExpressBitFieldAnd8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldAnd8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -428,7 +484,8 @@ PciExpressBitFieldAnd8 ( @param AndData The value to AND with the PCI configuration register.= =0D @param OrData The value to OR with the result of the AND operation.= =0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register.= =0D =0D **/=0D UINT8=0D @@ -442,6 +499,9 @@ PciExpressBitFieldAndThenOr8 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT8) ~0;=0D + }=0D return MmioBitFieldAndThenOr8 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -464,7 +524,8 @@ PciExpressBitFieldAndThenOr8 ( @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D Register.=0D =0D - @return The read value from the PCI configuration register.=0D + @retval 0xFF Invalid PCI address.=0D + @retval other The read value from the PCI configuration register.=0D =0D **/=0D UINT16=0D @@ -474,6 +535,9 @@ PciExpressRead16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);=0D }=0D =0D @@ -491,7 +555,8 @@ PciExpressRead16 ( Register.=0D @param Value The value to write.=0D =0D - @return The value written to the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value written to the PCI configuration register.=0D =0D **/=0D UINT16=0D @@ -502,6 +567,9 @@ PciExpressWrite16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value= );=0D }=0D =0D @@ -523,7 +591,8 @@ PciExpressWrite16 ( Register.=0D @param OrData The value to OR with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register= .=0D =0D **/=0D UINT16=0D @@ -534,6 +603,9 @@ PciExpressOr16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D }=0D =0D @@ -555,7 +627,8 @@ PciExpressOr16 ( Register.=0D @param AndData The value to AND with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register= .=0D =0D **/=0D UINT16=0D @@ -566,6 +639,9 @@ PciExpressAnd16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData= );=0D }=0D =0D @@ -589,7 +665,8 @@ PciExpressAnd16 ( @param AndData The value to AND with the PCI configuration register.=0D @param OrData The value to OR with the result of the AND operation.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register= .=0D =0D **/=0D UINT16=0D @@ -601,6 +678,9 @@ PciExpressAndThenOr16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioAndThenOr16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D AndData,=0D @@ -627,7 +707,9 @@ PciExpressAndThenOr16 ( @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D Range 0..15.=0D =0D - @return The value of the bit field read from the PCI configuration regis= ter.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value of the bit field read from the PCI configurati= on=0D + register.=0D =0D **/=0D UINT16=0D @@ -639,6 +721,9 @@ PciExpressBitFieldRead16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldRead16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -668,7 +753,8 @@ PciExpressBitFieldRead16 ( Range 0..15.=0D @param Value The new value of the bit field.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register= .=0D =0D **/=0D UINT16=0D @@ -681,6 +767,9 @@ PciExpressBitFieldWrite16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldWrite16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -714,7 +803,8 @@ PciExpressBitFieldWrite16 ( Range 0..15.=0D @param OrData The value to OR with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register= .=0D =0D **/=0D UINT16=0D @@ -727,6 +817,9 @@ PciExpressBitFieldOr16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldOr16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -760,7 +853,8 @@ PciExpressBitFieldOr16 ( Range 0..15.=0D @param AndData The value to AND with the PCI configuration register.= =0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register= .=0D =0D **/=0D UINT16=0D @@ -773,6 +867,9 @@ PciExpressBitFieldAnd16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldAnd16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -810,7 +907,8 @@ PciExpressBitFieldAnd16 ( @param AndData The value to AND with the PCI configuration register.= =0D @param OrData The value to OR with the result of the AND operation.= =0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration register= .=0D =0D **/=0D UINT16=0D @@ -824,6 +922,9 @@ PciExpressBitFieldAndThenOr16 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT16) ~0;=0D + }=0D return MmioBitFieldAndThenOr16 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -846,7 +947,8 @@ PciExpressBitFieldAndThenOr16 ( @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D Register.=0D =0D - @return The read value from the PCI configuration register.=0D + @retval 0xFFFF Invalid PCI address.=0D + @retval other The read value from the PCI configuration register.=0D =0D **/=0D UINT32=0D @@ -856,6 +958,9 @@ PciExpressRead32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);=0D }=0D =0D @@ -873,7 +978,8 @@ PciExpressRead32 ( Register.=0D @param Value The value to write.=0D =0D - @return The value written to the PCI configuration register.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value written to the PCI configuration register.= =0D =0D **/=0D UINT32=0D @@ -884,6 +990,9 @@ PciExpressWrite32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value= );=0D }=0D =0D @@ -905,7 +1014,8 @@ PciExpressWrite32 ( Register.=0D @param OrData The value to OR with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration regi= ster.=0D =0D **/=0D UINT32=0D @@ -916,6 +1026,9 @@ PciExpressOr32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);= =0D }=0D =0D @@ -937,7 +1050,8 @@ PciExpressOr32 ( Register.=0D @param AndData The value to AND with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration regi= ster.=0D =0D **/=0D UINT32=0D @@ -948,6 +1062,9 @@ PciExpressAnd32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData= );=0D }=0D =0D @@ -971,7 +1088,8 @@ PciExpressAnd32 ( @param AndData The value to AND with the PCI configuration register.=0D @param OrData The value to OR with the result of the AND operation.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration regi= ster.=0D =0D **/=0D UINT32=0D @@ -983,6 +1101,9 @@ PciExpressAndThenOr32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioAndThenOr32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D AndData,=0D @@ -1009,7 +1130,9 @@ PciExpressAndThenOr32 ( @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D Range 0..31.=0D =0D - @return The value of the bit field read from the PCI configuration regis= ter.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value of the bit field read from the PCI=0D + configuration register.=0D =0D **/=0D UINT32=0D @@ -1021,6 +1144,9 @@ PciExpressBitFieldRead32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioBitFieldRead32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1050,7 +1176,8 @@ PciExpressBitFieldRead32 ( Range 0..31.=0D @param Value The new value of the bit field.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration regi= ster.=0D =0D **/=0D UINT32=0D @@ -1063,6 +1190,9 @@ PciExpressBitFieldWrite32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioBitFieldWrite32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1096,7 +1226,8 @@ PciExpressBitFieldWrite32 ( Range 0..31.=0D @param OrData The value to OR with the PCI configuration register.=0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration regi= ster.=0D =0D **/=0D UINT32=0D @@ -1109,6 +1240,9 @@ PciExpressBitFieldOr32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioBitFieldOr32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1142,7 +1276,8 @@ PciExpressBitFieldOr32 ( Range 0..31.=0D @param AndData The value to AND with the PCI configuration register.= =0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration regi= ster.=0D =0D **/=0D UINT32=0D @@ -1155,6 +1290,9 @@ PciExpressBitFieldAnd32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioBitFieldAnd32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1192,7 +1330,8 @@ PciExpressBitFieldAnd32 ( @param AndData The value to AND with the PCI configuration register.= =0D @param OrData The value to OR with the result of the AND operation.= =0D =0D - @return The value written back to the PCI configuration register.=0D + @retval 0xFFFFFFFF Invalid PCI address.=0D + @retval other The value written back to the PCI configuration regi= ster.=0D =0D **/=0D UINT32=0D @@ -1206,6 +1345,9 @@ PciExpressBitFieldAndThenOr32 ( )=0D {=0D ASSERT_INVALID_PCI_ADDRESS (Address);=0D + if (Address >=3D PcdPciExpressBaseSize()) {=0D + return (UINT32) ~0;=0D + }=0D return MmioBitFieldAndThenOr32 (=0D (UINTN) GetPciExpressBaseAddress () + Address,=0D StartBit,=0D @@ -1235,7 +1377,8 @@ PciExpressBitFieldAndThenOr32 ( @param Size The size in bytes of the transfer.=0D @param Buffer The pointer to a buffer receiving the data read.=0D =0D - @return Size read data from StartAddress.=0D + @retval (UINTN)~0 Invalid PCI address.=0D + @retval other Size read data from StartAddress.=0D =0D **/=0D UINTN=0D @@ -1249,6 +1392,9 @@ PciExpressReadBuffer ( UINTN ReturnValue;=0D =0D ASSERT_INVALID_PCI_ADDRESS (StartAddress);=0D + if (StartAddress >=3D PcdPciExpressBaseSize()) {=0D + return (UINTN) ~0;=0D + }=0D ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D =0D if (Size =3D=3D 0) {=0D @@ -1335,7 +1481,8 @@ PciExpressReadBuffer ( @param Size The size in bytes of the transfer.=0D @param Buffer The pointer to a buffer containing the data to wri= te.=0D =0D - @return Size written to StartAddress.=0D + @retval (UINTN)~0 Invalid PCI address.=0D + @retval other Size written to StartAddress.=0D =0D **/=0D UINTN=0D @@ -1349,6 +1496,9 @@ PciExpressWriteBuffer ( UINTN ReturnValue;=0D =0D ASSERT_INVALID_PCI_ADDRESS (StartAddress);=0D + if (StartAddress >=3D PcdPciExpressBaseSize()) {=0D + return (UINTN) ~0;=0D + }=0D ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D =0D if (Size =3D=3D 0) {=0D --=20 2.27.0