From: "Daniel Schaefer" <daniel.schaefer@hpe.com>
To: <devel@edk2.groups.io>
Cc: Abner Chang <abner.chang@hpe.com>,
Gilbert Chen <gilbert.chen@hpe.com>,
Leif Lindholm <leif@nuviainc.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH 1/1] edk2-platforms: Deduplicate RISC-V SMBIOS
Date: Fri, 7 Aug 2020 18:44:44 +0200 [thread overview]
Message-ID: <20200807164444.1304-2-daniel.schaefer@hpe.com> (raw)
In-Reply-To: <20200807164444.1304-1-daniel.schaefer@hpe.com>
There was too much code, which wasn't called but it could have generated those SMBIOS table entries:
- Type 4 for each core (4xU51, 1xE51)
- Type 7 L1 instruction/data for each core
- Type 7 L2 for U54
- Type 44 for each core
- Type 4 for the coreplex
- Type 7 L2 for the coreplex
Now it only has code for those entries:
- Type 4 for SOC [1x]
- Type 7 L1 for SOC [1x] (even though every hart has own L1, but my Laptop's Intel i5 does that also)
- Type 7 L2 for SOC [1x]
- Type 44 for each hart, associated with CPU [5x]
In addition to simplifying the SMBIOS tables, the code for U54 and E51 is
combined, like Leif suggested in his review.
Here's what happened to the files:
Expanded:
- Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
Deleted file:
- Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
- Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
Merged with E51 code into single file:
- Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
Added SMBIOS Type 7 for L1 Cache, removed duplicated SMBIOS (Type 4 and 7 code):
- Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/SiFive/SiFive.dec | 2 -
.../FreedomU500VC707Board/U500.dsc | 1 -
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 -
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 1 -
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 ----
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 4 +
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 ----
.../FirmwareContextProcessorSpecificLib.h | 11 +
.../Include/ProcessorSpecificHobData.h | 3 +-
Silicon/SiFive/Include/Library/SiFiveE51.h | 60 -----
Silicon/SiFive/Include/Library/SiFiveU54.h | 50 ++--
.../Include/Library/SiFiveU54MCCoreplex.h | 55 ----
.../FirmwareContextProcessorSpecificLib.c | 26 ++
.../Universal/Pei/PlatformPei/Platform.c | 2 +-
.../Universal/Pei/PlatformPei/Platform.c | 2 +-
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 58 +----
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 235 -----------------
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 244 +++++++-----------
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 -------------
19 files changed, 178 insertions(+), 854 deletions(-)
delete mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
delete mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
delete mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
delete mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
delete mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
delete mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
diff --git a/Silicon/SiFive/SiFive.dec b/Silicon/SiFive/SiFive.dec
index 85ddfe0bf235..bf280864be63 100644
--- a/Silicon/SiFive/SiFive.dec
+++ b/Silicon/SiFive/SiFive.dec
@@ -28,8 +28,6 @@ [PcdsFixedAtBuild]
gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid |{0xD4, 0x69, 0x54, 0x87, 0x96, 0x96, 0x48, 0x7F, 0x9F, 0x57, 0xB6, 0xF1, 0xDE, 0x7D, 0x97, 0x42}|VOID*|0x00001000
# U54 Core GUID
gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid |{0x64, 0x70, 0xF6, 0x90, 0x11, 0x59, 0x47, 0xF1, 0xB8, 0xD5, 0xCF, 0x89, 0x10, 0xC5, 0x30, 0x20}|VOID*|0x00001001
- # U54 MC Coreplex GUID
- gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid |{0x67, 0xBF, 0x15, 0xD9, 0x7E, 0x4F, 0x48, 0x27, 0x87, 0x19, 0x79, 0x0B, 0xA6, 0x22, 0x7C, 0xBE}|VOID*|0x00001002
# U5 MC Coreplex GUID
gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU5MCCoreplexGuid |{0x06, 0x38, 0x9F, 0x33, 0xF9, 0xDB, 0x43, 0x13, 0x9A, 0x9B, 0x1C, 0x68, 0xD6, 0x04, 0xEA, 0xFF}|VOID*|0x00001003
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index 03f7006b9bb0..61a0cdedaaf4 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -203,7 +203,6 @@ [LibraryClasses.common.PEIM]
#
# RISC-V core libraries
#
- SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index 4809c7c6b7e8..2d7dabafaceb 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -204,7 +204,6 @@ [LibraryClasses.common.PEIM]
#
# RISC-V core libraries
#
- SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
index ab248b3718b9..b3124a6daf77 100644
--- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -37,7 +37,6 @@ [LibraryClasses]
PcdLib
MemoryAllocationLib
PrintLib
- SiliconSiFiveE51CoreInfoLib
SiliconSiFiveU54CoreInfoLib
[Guids]
diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
deleted file mode 100644
index 6c06c96be580..000000000000
--- a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+++ /dev/null
@@ -1,47 +0,0 @@
-## @file
-# Library instance to create core information HOB
-#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = SiliconSiFiveE51CoreInfoLib
- FILE_GUID = 80A59B85-1245-4309-AC58-2CFA4199B46C
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SiliconSiFiveE51CoreInfoLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- CoreInfoHob.c
-
-[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
- Silicon/SiFive/SiFive.dec
-
-[LibraryClasses]
- BaseLib
- FirmwareContextProcessorSpecificLib
- MemoryAllocationLib
- PcdLib
- PrintLib
- RiscVEdk2SbiLib
-
-[FixedPcd]
- gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid
- gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
- gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
- gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
- gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
index 9bbe2f064190..072024dc1be3 100644
--- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -29,6 +29,7 @@ [Packages]
MdeModulePkg/MdeModulePkg.dec
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
Silicon/SiFive/SiFive.dec
[LibraryClasses]
@@ -45,3 +46,6 @@ [FixedPcd]
gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU5MCCoreplexGuid
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
deleted file mode 100644
index 89bd702b8e0f..000000000000
--- a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+++ /dev/null
@@ -1,46 +0,0 @@
-## @file
-# Library instance to create core information HOB
-#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = SiliconSiFiveU54MCCoreplexInfoLib
- FILE_GUID = 483DE090-267E-4278-A0A1-15D9836780EA
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SiliconSiFiveU54MCCoreplexInfoLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- CoreInfoHob.c
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- Silicon/RISC-V/ProcessorPkg/RiscVPkg.dec
- Silicon/SiFive/SiFive.dec
-
-[LibraryClasses]
- BaseLib
- PcdLib
- MemoryAllocationLib
- PrintLib
- SiliconSiFiveE51CoreInfoLib
- SiliconSiFiveU54CoreInfoLib
-
-[FixedPcd]
- gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
- gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
- gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
- gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid
-
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
index c53d09b69eea..f3b096c257f4 100644
--- a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -39,4 +39,15 @@ CommonFirmwareContextHartSpecificInfo (
RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecDataHob
);
+/**
+ Print debug information of the processor specific data for a hart
+
+ @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+**/
+VOID
+EFIAPI
+DebugPrintHartSpecificInfo (
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ );
+
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
index c19f355853ae..2f5847e53e07 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
@@ -86,8 +86,7 @@ typedef struct {
///
typedef struct {
RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCache;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCache;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;
RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
} RISC_V_PROCESSOR_SMBIOS_HOB_DATA;
diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h b/Silicon/SiFive/Include/Library/SiFiveE51.h
deleted file mode 100644
index 6b587661860c..000000000000
--- a/Silicon/SiFive/Include/Library/SiFiveE51.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/** @file
- SiFive E51 Core library definitions.
-
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-#ifndef SIFIVE_E51_CORE_H_
-#define SIFIVE_E51_CORE_H_
-
-#include <PiPei.h>
-
-#include <SmbiosProcessorSpecificData.h>
-#include <ProcessorSpecificHobData.h>
-
-/**
- Function to build core specific information HOB.
-
- @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
- could be the same as CoreGuid if one processor has
- only one core.
- @param ParentProcessorUid Unique ID of pysical processor which owns this core.
- @param HartId Hart ID of this core.
- @param IsBootHart TRUE means this is the boot HART.
- @param GuidHobData Pointer to receive RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-CreateE51CoreProcessorSpecificDataHob (
- IN EFI_GUID *ParentProcessorGuid,
- IN UINTN ParentProcessorUid,
- IN UINTN HartId,
- IN BOOLEAN IsBootHart,
- OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData
- );
-
-/**
- Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
- this information and build SMBIOS Type4 and Type7 record.
-
- @param ProcessorUid Unique ID of pysical processor which owns this core.
- @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
- maintained in this structure is only valid before memory is discovered.
- Access to those pointers after memory is installed will cause unexpected issues.
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-CreateE51ProcessorSmbiosDataHob (
- IN UINTN ProcessorUid,
- OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
- );
-
-#endif
diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h b/Silicon/SiFive/Include/Library/SiFiveU54.h
index 9920a55309b2..ddd2b9203404 100644
--- a/Silicon/SiFive/Include/Library/SiFiveU54.h
+++ b/Silicon/SiFive/Include/Library/SiFiveU54.h
@@ -11,11 +11,10 @@
#include <PiPei.h>
-#include <SmbiosProcessorSpecificData.h>
#include <ProcessorSpecificHobData.h>
/**
- Function to build core specific information HOB.
+ Function to build core specific information HOB for U54 or E51 core.
@param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
could be the same as CoreGuid if one processor has
@@ -23,38 +22,55 @@
@param ParentProcessorUid Unique ID of pysical processor which owns this core.
@param HartId Hart ID of this core.
@param IsBootHart TRUE means this is the boot HART.
- @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
+ @param IsManagementCore TRUE means this is for the E51 management core, not U54
+ @param GuidHobData Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
@return EFI_SUCCESS The PEIM initialized successfully.
**/
EFI_STATUS
EFIAPI
-CreateU54CoreProcessorSpecificDataHob (
+CreateU54E51CoreProcessorSpecificDataHob (
IN EFI_GUID *ParentProcessorGuid,
IN UINTN ParentProcessorUid,
IN UINTN HartId,
IN BOOLEAN IsBootHart,
- OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobdata
- );
+ IN BOOLEAN IsManagementCore,
+ OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData
+);
/**
- Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
- this information and build SMBIOS Type4 and Type7 record.
+ Function to build cache related SMBIOS information. RISC-V SMBIOS DXE driver collects
+ this information and builds SMBIOS Type 7 record.
- @param ProcessorUid Unique ID of pysical processor which owns this core.
- @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
- maintained in this structure is only valid before memory is discovered.
- Access to those pointers after memory is installed will cause unexpected issues.
+ The caller can adjust the allocated hob data to their needs.
- @return EFI_SUCCESS The PEIM initialized successfully.
+ @param ProcessorUid Unique ID of physical processor which owns this core.
+ @param L1CacheDataHobPtr Pointer to allocated HOB data.
**/
-EFI_STATUS
+VOID
EFIAPI
-CreateU54ProcessorSmbiosDataHob (
+CreateU54SmbiosType7L1DataHob (
IN UINTN ProcessorUid,
- IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
- );
+ OUT RISC_V_PROCESSOR_TYPE7_HOB_DATA **L1CacheDataHobPtr
+);
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collects
+ this information and builds SMBIOS Type 4 record.
+
+ The caller can adjust the allocated hob data to their needs.
+
+ @param ProcessorUid Unique ID of physical processor which owns this core.
+ @param ProcessorDataHobPtr Pointer to allocated HOB data.
+
+**/
+VOID
+EFIAPI
+CreateU54SmbiosType4DataHob (
+ IN UINTN ProcessorUid,
+ OUT RISC_V_PROCESSOR_TYPE4_HOB_DATA **ProcessorDataHobPtr
+);
#endif
diff --git a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h b/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
deleted file mode 100644
index 0e14b285543a..000000000000
--- a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/** @file
- SiFive U54 Coreplex library definitions.
-
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-#ifndef SIFIVE_U54MC_COREPLEX_CORE_H_
-#define SIFIVE_U54MC_COREPLEX_CORE_H_
-
-#include <PiPei.h>
-
-#include <SmbiosProcessorSpecificData.h>
-#include <ProcessorSpecificHobData.h>
-
-#define SIFIVE_U54MC_COREPLEX_E51_HART_ID 0
-#define SIFIVE_U54MC_COREPLEX_U54_0_HART_ID 1
-#define SIFIVE_U54MC_COREPLEX_U54_1_HART_ID 2
-#define SIFIVE_U54MC_COREPLEX_U54_2_HART_ID 3
-#define SIFIVE_U54MC_COREPLEX_U54_3_HART_ID 4
-
-/**
- Build up U54MC coreplex processor core-specific information.
-
- @param UniqueId U54MC unique ID.
-
- @return EFI_STATUS
-
-**/
-EFI_STATUS
-EFIAPI
-CreateU54MCCoreplexProcessorSpecificDataHob (
- IN UINTN UniqueId
- );
-
-/**
- Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
- this information and build SMBIOS Type4 and Type7 record.
-
- @param ProcessorUid Unique ID of pysical processor which owns this core.
- @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
- maintained in this structure is only valid before memory is discovered.
- Access to those pointers after memory is installed will cause unexpected issues.
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-CreateU54MCProcessorSmbiosDataHob (
- IN UINTN ProcessorUid,
- IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
- );
-#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
index 066d1170c6f0..c62f77bc49ba 100644
--- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -91,3 +91,29 @@ CommonFirmwareContextHartSpecificInfo (
FirmwareContextHartSpecific->MachineImplId.Value64_H;
return EFI_SUCCESS;
}
+
+/**
+ Print debug information of the processor specific data for a hart
+
+ @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+**/
+VOID
+EFIAPI
+DebugPrintHartSpecificInfo (
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ )
+{
+ DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *Is Boot Hart? = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.BootHartId));
+ DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported));
+ DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.HartXlen ));
+ DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineModeXlen));
+ DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.SupervisorModeXlen));
+ DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.UserModeXlen));
+ DEBUG ((DEBUG_INFO, " *InstSetSupported = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported));
+ DEBUG ((DEBUG_INFO, " *MachineVendorId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineArchId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineImplId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineImplId.Value64_L));
+}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
index 3d3f67d92092..6641e10f2ec3 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
@@ -258,7 +258,7 @@ BuildCoreInformationHob (
if (EFI_ERROR (Status)) {
ASSERT(FALSE);
}
- Status = CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr);
+ Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
if (EFI_ERROR (Status)) {
ASSERT(FALSE);
}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
index 3d3f67d92092..6641e10f2ec3 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
@@ -258,7 +258,7 @@ BuildCoreInformationHob (
if (EFI_ERROR (Status)) {
ASSERT(FALSE);
}
- Status = CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr);
+ Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
if (EFI_ERROR (Status)) {
ASSERT(FALSE);
}
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
index c3bb0c45128d..57c19c8187d6 100644
--- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -22,7 +22,6 @@
#include <SmbiosProcessorSpecificData.h>
#include <ProcessorSpecificHobData.h>
#include <SiFiveU5MCCoreplex.h>
-#include <Library/SiFiveE51.h>
#include <Library/SiFiveU54.h>
/**
@@ -51,7 +50,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob (
ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid);
MCSupport = PcdGetBool (PcdE5MCSupported);
if (MCSupport == TRUE) {
- Status = CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, FALSE, &GuidHobData);
+ Status = CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, FALSE, TRUE, &GuidHobData);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\n"));
ASSERT (FALSE);
@@ -60,7 +59,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob (
DEBUG ((DEBUG_INFO, "Support E5 Monitor core on U5 platform, HOB at address 0x%x\n", GuidHobData));
}
for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSupport); HartIdNumber ++) {
- Status = CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId))? TRUE: FALSE, &GuidHobData);
+ Status = CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId)), FALSE, &GuidHobData);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\n"));
ASSERT (FALSE);
@@ -83,12 +82,12 @@ CreateU5MCCoreplexProcessorSpecificDataHob (
Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
this information and build SMBIOS Type4 and Type7 record.
- @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param ProcessorUid Unique ID of physical processor which owns this core.
@param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
maintained in this structure is only valid before memory is discovered.
Access to those pointers after memory is installed will cause unexpected issues.
- @return EFI_SUCCESS The PEIM initialized successfully.
+ @return EFI_SUCCESS The SMBIOS Hobs were created successfully.
**/
EFI_STATUS
@@ -99,10 +98,10 @@ CreateU5MCProcessorSmbiosDataHob (
)
{
EFI_GUID *GuidPtr;
- RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;
RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1CacheDataHobPtr;
RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;
RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
@@ -112,6 +111,9 @@ CreateU5MCProcessorSmbiosDataHob (
return EFI_INVALID_PARAMETER;
}
+ CreateU54SmbiosType7L1DataHob (ProcessorUid, &L1CacheDataHobPtr);
+ CreateU54SmbiosType4DataHob (ProcessorUid, &ProcessorDataHobPtr);
+
//
// Build up SMBIOS type 7 L2 cache record.
//
@@ -138,51 +140,12 @@ CreateU5MCProcessorSmbiosDataHob (
ASSERT (FALSE);
}
- //
- // Build up SMBIOS type 4 record.
- //
- ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
- ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
- ProcessorDataHob.ProcessorUid = ProcessorUid;
- ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
- ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
- ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
- SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
- ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
- ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
- ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
- ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
- ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
- ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
- ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.CoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
- ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
- ProcessorDataHob.SmbiosType4Processor.ThreadCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
- ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
- ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
- ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
- ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
- ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
- ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
- if (ProcessorDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
-
ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
SmbiosDataHob.Processor = ProcessorDataHobPtr;
- SmbiosDataHob.L1InstCache = NULL;
- SmbiosDataHob.L1DataCache = NULL;
+ SmbiosDataHob.L1Cache = L1CacheDataHobPtr;
SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
SmbiosDataHob.L3Cache = NULL;
+
GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
if (SmbiosDataHobPtr == NULL) {
@@ -191,5 +154,6 @@ CreateU5MCProcessorSmbiosDataHob (
}
*SmbiosHobPtr = SmbiosDataHobPtr;
DEBUG ((DEBUG_INFO, "%a: Exit\n", __FUNCTION__));
+
return EFI_SUCCESS;
}
diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
deleted file mode 100644
index 0f9db4012f75..000000000000
--- a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/**@file
- Build up platform processor information.
-
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
-//
-// The Library classes this module consumes
-//
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/FirmwareContextProcessorSpecificLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <IndustryStandard/RiscVOpensbi.h>
-#include <Library/ResourcePublicationLib.h>
-
-#include <Library/RiscVEdk2SbiLib.h>
-#include <ProcessorSpecificHobData.h>
-#include <RiscVImpl.h>
-#include <sbi/sbi_hart.h>
-#include <sbi/sbi_scratch.h>
-#include <sbi/sbi_platform.h>
-#include <SmbiosProcessorSpecificData.h>
-
-/**
- Function to build core specific information HOB. RISC-V SMBIOS DXE driver collect
- this information and build SMBIOS Type44.
-
- @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
- could be the same as CoreGuid if one processor has
- only one core.
- @param ParentProcessorUid Unique ID of pysical processor which owns this core.
- @param HartId Hart ID of this core.
- @param IsBootHart TRUE means this is the boot HART.
- @param GuidHobData Pointer to receive EFI_HOB_GUID_TYPE.
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-CreateE51CoreProcessorSpecificDataHob (
- IN EFI_GUID *ParentProcessorGuid,
- IN UINTN ParentProcessorUid,
- IN UINTN HartId,
- IN BOOLEAN IsBootHart,
- OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData
- )
-{
- RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob;
- EFI_GUID *ProcessorSpecDataHobGuid;
- RISC_V_PROCESSOR_SPECIFIC_HOB_DATA ProcessorSpecDataHob;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
- EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
-
- DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
-
- if (GuidHobData == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- ASSERT_EFI_ERROR (SbiGetFirmwareContext (&FirmwareContext));
- DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContext));
- FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
- DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", FirmwareContextHartSpecific));
-
- //
- // Build up RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
- //
- CommonFirmwareContextHartSpecificInfo (
- FirmwareContextHartSpecific,
- ParentProcessorGuid,
- ParentProcessorUid,
- (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid),
- HartId,
- IsBootHart,
- &ProcessorSpecDataHob
- );
- ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L = TO_BE_FILLED;
- ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_H = TO_BE_FILLED;
- ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L = TO_BE_FILLED;
- ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_H = TO_BE_FILLED;
- ProcessorSpecDataHob.ProcessorSpecificData.HartXlen = RegisterLen64;
- ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen = RegisterLen64;
- ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
- ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen = RegisterLen64;
-
- DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartId.Value64_L));
- DEBUG ((DEBUG_INFO, " *Is Boot Hart? = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.BootHartId));
- DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported));
- DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L));
- DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
- DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartXlen ));
- DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen));
- DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen));
- DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen));
- DEBUG ((DEBUG_INFO, " *InstSetSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.InstSetSupported));
- DEBUG ((DEBUG_INFO, " *MachineVendorId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineVendorId.Value64_L));
- DEBUG ((DEBUG_INFO, " *MachineArchId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineArchId.Value64_L));
- DEBUG ((DEBUG_INFO, " *MachineImplId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineImplId.Value64_L));
-
- //
- // Build GUID HOB for E51 core, this is for SMBIOS type 44
- //
- ProcessorSpecDataHobGuid = PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid);
- CoreGuidHob = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA));
- if (CoreGuidHob == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n"));
- ASSERT (FALSE);
- }
- *GuidHobData = CoreGuidHob;
- return EFI_SUCCESS;
-}
-
-/**
- Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
- this information and build SMBIOS Type4 and Type7 record.
-
- @param ProcessorUid Unique ID of pysical processor which owns this core.
- @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
- maintained in this structure is only valid before memory is discovered.
- Access to those pointers after memory is installed will cause unexpected issues.
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-CreateE51ProcessorSmbiosDataHob (
- IN UINTN ProcessorUid,
- OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
- )
-{
- EFI_GUID *GuidPtr;
- RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
- RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
-
- if (SmbiosHobPtr == NULL) {
- return EFI_INVALID_PARAMETER;
- }
- //
- // Build up SMBIOS type 7 L1 instruction cache record.
- //
- ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid));
- L1InstCacheDataHob.ProcessorUid = ProcessorUid;
- L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
- RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
- RISC_V_CACHE_CONFIGURATION_ENABLED | \
- RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
- L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
- L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
- L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeInstruction;
- L1InstCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
- L1InstCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- if (L1InstCacheDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core L1 instruction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
-
- //
- // Build up SMBIOS type 4 record.
- //
- ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
- CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid));
- ProcessorDataHob.ProcessorUid = ProcessorUid;
- ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
- ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
- ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
- SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
- ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
- ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
- ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
- ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = 0xffff;
- ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
- ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
- ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.CoreCount = 1;
- ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 1;
- ProcessorDataHob.SmbiosType4Processor.ThreadCount = 1;
- ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
- ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
- ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
- ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
- ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
- ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
- if (ProcessorDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
-
- ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
- SmbiosDataHob.Processor = ProcessorDataHobPtr;
- SmbiosDataHob.L1InstCache = L1InstCacheDataHobPtr;
- SmbiosDataHob.L1DataCache = NULL;
- SmbiosDataHob.L2Cache = NULL;
- SmbiosDataHob.L3Cache = NULL;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
- SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
- if (SmbiosDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
- *SmbiosHobPtr = SmbiosDataHobPtr;
- return EFI_SUCCESS;
-}
-
-
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
index 70ac13326216..d013638f58ed 100644
--- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -1,7 +1,7 @@
/**@file
- Build up platform processor information.
+ Build up platform processor information of SiFive U54 core.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -9,11 +9,6 @@
#include <IndustryStandard/RiscVOpensbi.h>
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
//
// The Library classes this module consumes
//
@@ -21,35 +16,38 @@
#include <Library/DebugLib.h>
#include <Library/FirmwareContextProcessorSpecificLib.h>
#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
#include <Library/RiscVEdk2SbiLib.h>
+
+#include <RiscVImpl.h>
#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
#include <sbi/sbi_scratch.h>
-#include <RiscVImpl.h>
-#include <SmbiosProcessorSpecificData.h>
/**
- Function to build core specific information HOB.
+ Function to build core specific information HOB for U54 or E51 core.
- @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
+ @param ParentProcessorGuid Parent processor of this core. ParentProcessorGuid
could be the same as CoreGuid if one processor has
only one core.
@param ParentProcessorUid Unique ID of pysical processor which owns this core.
@param HartId Hart ID of this core.
@param IsBootHart TRUE means this is the boot HART.
- @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
+ @param IsManagementCore TRUE means this is for the E51 management core, not U54
+ @param GuidHobData Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
@return EFI_SUCCESS The PEIM initialized successfully.
**/
EFI_STATUS
EFIAPI
-CreateU54CoreProcessorSpecificDataHob (
+CreateU54E51CoreProcessorSpecificDataHob (
IN EFI_GUID *ParentProcessorGuid,
IN UINTN ParentProcessorUid,
IN UINTN HartId,
IN BOOLEAN IsBootHart,
- OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobdata
+ IN BOOLEAN IsManagementCore,
+ OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData
)
{
RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob;
@@ -60,7 +58,7 @@ CreateU54CoreProcessorSpecificDataHob (
DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
- if (GuidHobdata == NULL) {
+ if (GuidHobData == NULL) {
return EFI_INVALID_PARAMETER;
}
@@ -81,159 +79,112 @@ CreateU54CoreProcessorSpecificDataHob (
IsBootHart,
&ProcessorSpecDataHob
);
+
ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L = TO_BE_FILLED;
ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_H = TO_BE_FILLED;
ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L = TO_BE_FILLED;
ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_H = TO_BE_FILLED;
ProcessorSpecDataHob.ProcessorSpecificData.HartXlen = RegisterLen64;
ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen = RegisterLen64;
- ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen = RegisterLen64;
- DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartId.Value64_L));
- DEBUG ((DEBUG_INFO, " *Is Boot Hart? = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.BootHartId));
- DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported));
- DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L));
- DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
- DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartXlen ));
- DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen));
- DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen));
- DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen));
- DEBUG ((DEBUG_INFO, " *InstSetSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.InstSetSupported));
- DEBUG ((DEBUG_INFO, " *MachineVendorId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineVendorId.Value64_L));
- DEBUG ((DEBUG_INFO, " *MachineArchId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineArchId.Value64_L));
- DEBUG ((DEBUG_INFO, " *MachineImplId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineImplId.Value64_L));
+ if (IsManagementCore) {
+ // Configuration for E51
+ ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
+ } else {
+ // Configuration for U54
+ ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterLen64;
+ }
+
+
+ DebugPrintHartSpecificInfo (&ProcessorSpecDataHob);
//
- // Build GUID HOB for U54 core.
+ // Build GUID HOB for core, this is for SMBIOS type 44
//
ProcessorSpecDataHobGuid = PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid);
CoreGuidHob = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA));
if (CoreGuidHob == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n"));
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core.\n"));
ASSERT (FALSE);
}
- *GuidHobdata = CoreGuidHob;
+ *GuidHobData = CoreGuidHob;
return EFI_SUCCESS;
}
/**
- Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
- this information and build SMBIOS Type4 and Type7 record.
+ Function to build cache related SMBIOS information. RISC-V SMBIOS DXE driver collects
+ this information and builds SMBIOS Type 7 record.
- @param ProcessorUid Unique ID of pysical processor which owns this core.
- @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
- maintained in this structure is only valid before memory is discovered.
- Access to those pointers after memory is installed will cause unexpected issues.
+ The caller can adjust the allocated hob data to their needs.
- @return EFI_SUCCESS The PEIM initialized successfully.
+ @param ProcessorUid Unique ID of physical processor which owns this core.
+ @param L1CacheDataHobPtr Pointer to allocated HOB data.
**/
-EFI_STATUS
+VOID
EFIAPI
-CreateU54ProcessorSmbiosDataHob (
+CreateU54SmbiosType7L1DataHob (
IN UINTN ProcessorUid,
- IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
+ OUT RISC_V_PROCESSOR_TYPE7_HOB_DATA **L1CacheDataHobPtr
+ )
+{
+ EFI_GUID *GuidPtr;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA L1CacheDataHob;
+
+ //
+ // Build up SMBIOS type 7 L1 cache record.
+ //
+ ZeroMem((VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ L1CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
+ L1CacheDataHob.ProcessorUid = ProcessorUid;
+ L1CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L1CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L1CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L1CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L1CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L1CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L1CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L1CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L1CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
+ L1CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ *L1CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ if (L1CacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex L1 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collects
+ this information and builds SMBIOS Type 4 record.
+
+ The caller can adjust the allocated hob data to their needs.
+
+ @param ProcessorUid Unique ID of physical processor which owns this core.
+ @param ProcessorDataHobPtr Pointer to allocated HOB data.
+
+**/
+VOID
+EFIAPI
+CreateU54SmbiosType4DataHob (
+ IN UINTN ProcessorUid,
+ OUT RISC_V_PROCESSOR_TYPE4_HOB_DATA **ProcessorDataHobPtr
)
{
EFI_GUID *GuidPtr;
RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA L1DataCacheDataHob;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
- RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCacheDataHobPtr;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
-
- if (SmbiosHobPtr == NULL) {
- return EFI_INVALID_PARAMETER;
- }
- //
- // Build up SMBIOS type 7 L1 instruction cache record.
- //
- ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
- L1InstCacheDataHob.ProcessorUid = ProcessorUid;
- L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
- RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
- RISC_V_CACHE_CONFIGURATION_ENABLED | \
- RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
- L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
- L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
- L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
- L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeInstruction;
- L1InstCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
- L1InstCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- if (L1InstCacheDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 instruction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
-
- //
- // Build up SMBIOS type 7 L1 data cache record.
- //
- ZeroMem((VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- CopyGuid (&L1DataCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
- L1DataCacheDataHob.ProcessorUid = ProcessorUid;
- L1DataCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
- L1DataCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
- RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
- RISC_V_CACHE_CONFIGURATION_ENABLED | \
- RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
- L1DataCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
- L1DataCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
- L1DataCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
- L1DataCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
- L1DataCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
- L1DataCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
- L1DataCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeData;
- L1DataCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
- L1DataCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- if (L1DataCacheDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 data cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
-
- //
- // Build up SMBIOS type 7 L2 cache record.
- //
- ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- CopyGuid (&L2CacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
- L2CacheDataHob.ProcessorUid = ProcessorUid;
- L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
- RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
- RISC_V_CACHE_CONFIGURATION_ENABLED | \
- RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
- L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
- L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
- L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
- L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
- L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- if (L2CacheDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
//
// Build up SMBIOS type 4 record.
//
ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
- CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
ProcessorDataHob.ProcessorUid = ProcessorUid;
ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
@@ -253,34 +204,19 @@ CreateU54ProcessorSmbiosDataHob (
ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.CoreCount = 1;
- ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 1;
- ProcessorDataHob.SmbiosType4Processor.ThreadCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
+
GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
- ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ *ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
if (ProcessorDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
ASSERT (FALSE);
}
-
- ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
- SmbiosDataHob.Processor = ProcessorDataHobPtr;
- SmbiosDataHob.L1InstCache = L1InstCacheDataHobPtr;
- SmbiosDataHob.L1DataCache = L1DataCacheDataHobPtr;
- SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
- SmbiosDataHob.L3Cache = NULL;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
- SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
- if (SmbiosDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
- *SmbiosHobPtr = SmbiosDataHobPtr;
- return EFI_SUCCESS;
}
-
diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
deleted file mode 100644
index 97bed2ac8d27..000000000000
--- a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/**@file
- Build up platform processor information.
-
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
-//
-// The Library classes this module consumes
-//
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/SiFiveE51.h>
-#include <Library/SiFiveU54.h>
-#include <Library/SiFiveU54MCCoreplex.h>
-
-/**
- Build up processor-specific HOB for U54MC Coreplex
-
- @param UniqueId Unique ID of this U54MC Coreplex processor
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-CreateU54MCCoreplexProcessorSpecificDataHob (
- IN UINTN UniqueId
- )
-{
- EFI_STATUS Status;
- RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ThisGuidHobData;
- EFI_GUID *ParentProcessorGuid;
-
- DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
-
- ParentProcessorGuid = PcdGetPtr (PcdSiFiveU54MCCoreplexGuid);
- Status = CreateE51CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54MC_COREPLEX_E51_HART_ID, FALSE, &ThisGuidHobData);
- if (EFI_ERROR(Status)) {
- DEBUG ((DEBUG_ERROR, "%a: Faile to build E51 core information HOB for U54 Coreplex.\n", __FUNCTION__));
- return Status;
- }
- Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_0_HART_ID, TRUE, &ThisGuidHobData);
- if (EFI_ERROR(Status)) {
- DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
- return Status;
- }
- Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_1_HART_ID, FALSE, &ThisGuidHobData);
- if (EFI_ERROR(Status)) {
- DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
- return Status;
- }
- Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_2_HART_ID, FALSE, &ThisGuidHobData);
- if (EFI_ERROR(Status)) {
- DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
- return Status;
- }
- Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_3_HART_ID, FALSE, &ThisGuidHobData);
- if (EFI_ERROR(Status)) {
- DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
- return Status;
- }
- return Status;
-}
-
-/**
- Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
- this information and build SMBIOS Type4 and Type7 record.
-
- @param ProcessorUid Unique ID of pysical processor which owns this core.
- @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
- maintained in this structure is only valid before memory is discovered.
- Access to those pointers after memory is installed will cause unexpected issues.
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-CreateU54MCProcessorSmbiosDataHob (
- IN UINTN ProcessorUid,
- IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
- )
-{
- EFI_GUID *GuidPtr;
- RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
- RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
-
- if (SmbiosHobPtr == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Build up SMBIOS type 7 L2 cache record.
- //
- ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- L2CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCCoreplexGuid));
- L2CacheDataHob.ProcessorUid = ProcessorUid;
- L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
- RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
- RISC_V_CACHE_CONFIGURATION_ENABLED | \
- RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
- L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
- L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
- L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
- L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
- L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
- L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- if (L2CacheDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreplex L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
-
- //
- // Build up SMBIOS type 4 record.
- //
- ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
- ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCCoreplexGuid));
- ProcessorDataHob.ProcessorUid = ProcessorUid;
- ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
- ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
- ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
- SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
- ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
- ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
- ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
- ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
- ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
- ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
- ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
- ProcessorDataHob.SmbiosType4Processor.CoreCount = 5;
- ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 5;
- ProcessorDataHob.SmbiosType4Processor.ThreadCount = 5;
- ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
- ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
- ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
- ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
- ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
- ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
- if (ProcessorDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreplex RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
-
- ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
- SmbiosDataHob.Processor = ProcessorDataHobPtr;
- SmbiosDataHob.L1InstCache = NULL;
- SmbiosDataHob.L1DataCache = NULL;
- SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
- SmbiosDataHob.L3Cache = NULL;
- GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
- SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
- if (SmbiosDataHobPtr == NULL) {
- DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54MC Coreplex RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
- ASSERT (FALSE);
- }
- *SmbiosHobPtr = SmbiosDataHobPtr;
- return EFI_SUCCESS;
-}
--
2.28.0
next prev parent reply other threads:[~2020-08-07 16:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-07 16:44 [PATCH 0/1] edk2-platforms: Deduplicate RISC-V SMBIOS Daniel Schaefer
2020-08-07 16:44 ` Daniel Schaefer [this message]
2020-08-14 13:40 ` [edk2-devel] [PATCH 1/1] " Leif Lindholm
2020-08-15 4:53 ` Daniel Schaefer
2020-08-15 9:40 ` Abner Chang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200807164444.1304-2-daniel.schaefer@hpe.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox