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Fri, 7 Aug 2020 16:44:56 +0000 Received: from DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM ([fe80::4cbe:3dd0:cae4:b093]) by DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM ([fe80::4cbe:3dd0:cae4:b093%3]) with mapi id 15.20.3261.020; Fri, 7 Aug 2020 16:44:56 +0000 From: "Daniel Schaefer" To: CC: Abner Chang , Gilbert Chen , Leif Lindholm , Michael D Kinney , Ard Biesheuvel Subject: [PATCH 1/1] edk2-platforms: Deduplicate RISC-V SMBIOS Date: Fri, 7 Aug 2020 18:44:44 +0200 Message-ID: <20200807164444.1304-2-daniel.schaefer@hpe.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200807164444.1304-1-daniel.schaefer@hpe.com> References: <20200807164444.1304-1-daniel.schaefer@hpe.com> X-ClientProxiedBy: SN2PR01CA0059.prod.exchangelabs.com (2603:10b6:800::27) To DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:760d::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from x360-nix.fritz.box (93.215.219.173) by SN2PR01CA0059.prod.exchangelabs.com (2603:10b6:800::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: smEqHp6mSDNZjEE4+fcLqjZWkfXDVEvFzix4dOQ59vQjocDxJbE46RAthaG1QmZkJBdLqZgQwUYU31jf1+y9/8pGg9OmDCRZX558fEBHjscOCaX6EZLUcXTdjnt84b5wn6RyQjMvWpdM3dh89udeTxquRhA3y9SC3LFwOiJrq+/nLhCJT8Kh6zaE9tTc7R8LVDzkM5hzMIivRcwLqbtOwJrXr8yiMncdSc1DAzDwerjBUTmrWtv47if+6bZse/JrNmH5PIOikh1Y19bmi8Z5XvzdRTs42poutwHqs0Ehf6SD62cYRu2Z3Tq/JNf0i8tZe3yFP5bHPfd7pt8Liop0N6Sua4HNt6r7fXTTvkLvnbcoh2bYkMDgJjYHYEqZSQuW4DKrRnPEJKGq9g45qmVeDxvP5gy8V1TNdbBVcwh9+atNiZT7LTuxDGTyVzyCVgYhn+P3cdB5eZWrp/y5qC1cTUPplbjiDyFcnzZvck2ituSclD5g5m9RNA8ZotGfIjPY3clnmjjd5ah6ZjOCxSdrkXnHw0mTgc8HDkvti//rQejzSnS/YMLMe0eEzu99rl2zOgmfKSNEk174T7qS8pMGWSCrzrZ/gW1Rfc5/55ilsnoA506p7Pc7VXY4pZFx4efX6PFnIRIe3tuZkkEJE710Lg== X-MS-Exchange-CrossTenant-Network-Message-Id: 654db7e8-1c70-4a27-7b5f-08d83af136d1 X-MS-Exchange-CrossTenant-AuthSource: DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2020 16:44:56.0300 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 105b2061-b669-4b31-92ac-24d304d195dc X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FbL5N1LEkzNwiMRZ/iEeIkRyoIAklNrSB/7zKCD4UJJeG1wE5vcnO73S9VVlqCiQNt3Yj04vfAq8xMYofvbwWw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DF4PR8401MB0506 X-OriginatorOrg: hpe.com X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-08-07_15:2020-08-06,2020-08-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=4 mlxlogscore=999 spamscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008070117 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain There was too much code, which wasn't called but it could have generated th= ose SMBIOS table entries: - Type 4 for each core (4xU51, 1xE51) - Type 7 L1 instruction/data for each core - Type 7 L2 for U54 - Type 44 for each core - Type 4 for the coreplex - Type 7 L2 for the coreplex Now it only has code for those entries: - Type 4 for SOC [1x] - Type 7 L1 for SOC [1x] (even though every hart has own L1, but my Laptop'= s Intel i5 does that also) - Type 7 L2 for SOC [1x] - Type 44 for each hart, associated with CPU [5x] In addition to simplifying the SMBIOS tables, the code for U54 and E51 is combined, like Leif suggested in his review. Here's what happened to the files: Expanded: - Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/F= irmwareContextProcessorSpecificLib.c Deleted file: - Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c - Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c Merged with E51 code into single file: - Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c Added SMBIOS Type 7 for L1 Cache, removed duplicated SMBIOS (Type 4 and 7 c= ode): - Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c Cc: Abner Chang Cc: Gilbert Chen Cc: Leif Lindholm Cc: Michael D Kinney Cc: Ard Biesheuvel --- Silicon/SiFive/SiFive.dec | 2 - .../FreedomU500VC707Board/U500.dsc | 1 - .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 - .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 1 - .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 ---- .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 4 + .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 ---- .../FirmwareContextProcessorSpecificLib.h | 11 + .../Include/ProcessorSpecificHobData.h | 3 +- Silicon/SiFive/Include/Library/SiFiveE51.h | 60 ----- Silicon/SiFive/Include/Library/SiFiveU54.h | 50 ++-- .../Include/Library/SiFiveU54MCCoreplex.h | 55 ---- .../FirmwareContextProcessorSpecificLib.c | 26 ++ .../Universal/Pei/PlatformPei/Platform.c | 2 +- .../Universal/Pei/PlatformPei/Platform.c | 2 +- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 58 +---- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 235 ----------------- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 244 +++++++----------- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 ------------- 19 files changed, 178 insertions(+), 854 deletions(-) delete mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInf= oHobLib.inf delete mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= PeiCoreInfoHobLib.inf delete mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h delete mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h delete mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHo= b.c delete mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= CoreInfoHob.c diff --git a/Silicon/SiFive/SiFive.dec b/Silicon/SiFive/SiFive.dec index 85ddfe0bf235..bf280864be63 100644 --- a/Silicon/SiFive/SiFive.dec +++ b/Silicon/SiFive/SiFive.dec @@ -28,8 +28,6 @@ [PcdsFixedAtBuild] gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid |{0xD4, 0x69, 0x54,= 0x87, 0x96, 0x96, 0x48, 0x7F, 0x9F, 0x57, 0xB6, 0xF1, 0xDE, 0x7D, 0x97, 0x= 42}|VOID*|0x00001000=0D # U54 Core GUID=0D gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid |{0x64, 0x70, 0xF6,= 0x90, 0x11, 0x59, 0x47, 0xF1, 0xB8, 0xD5, 0xCF, 0x89, 0x10, 0xC5, 0x30, 0x= 20}|VOID*|0x00001001=0D - # U54 MC Coreplex GUID=0D - gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid |{0x67, 0xBF,= 0x15, 0xD9, 0x7E, 0x4F, 0x48, 0x27, 0x87, 0x19, 0x79, 0x0B, 0xA6, 0x22, 0x= 7C, 0xBE}|VOID*|0x00001002=0D # U5 MC Coreplex GUID=0D gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU5MCCoreplexGuid |{0x06, 0x38, = 0x9F, 0x33, 0xF9, 0xDB, 0x43, 0x13, 0x9A, 0x9B, 0x1C, 0x68, 0xD6, 0x04, 0xE= A, 0xFF}|VOID*|0x00001003=0D =0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/P= latform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc index 03f7006b9bb0..61a0cdedaaf4 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc @@ -203,7 +203,6 @@ [LibraryClasses.common.PEIM] #=0D # RISC-V core libraries=0D #=0D - SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf=0D SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf=0D SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/Pei= CoreInfoHobLib/PeiCoreInfoHobLib.inf=0D =0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 4809c7c6b7e8..2d7dabafaceb 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -204,7 +204,6 @@ [LibraryClasses.common.PEIM] #=0D # RISC-V core libraries=0D #=0D - SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf=0D SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf=0D SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/Pei= CoreInfoHobLib/PeiCoreInfoHobLib.inf=0D =0D diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreI= nfoHobLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCo= reInfoHobLib.inf index ab248b3718b9..b3124a6daf77 100644 --- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL= ib.inf +++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL= ib.inf @@ -37,7 +37,6 @@ [LibraryClasses] PcdLib=0D MemoryAllocationLib=0D PrintLib=0D - SiliconSiFiveE51CoreInfoLib=0D SiliconSiFiveU54CoreInfoLib=0D =0D [Guids]=0D diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf deleted file mode 100644 index 6c06c96be580..000000000000 --- a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf +++ /dev/null @@ -1,47 +0,0 @@ -## @file=0D -# Library instance to create core information HOB=0D -#=0D -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -##=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x0001001b=0D - BASE_NAME =3D SiliconSiFiveE51CoreInfoLib=0D - FILE_GUID =3D 80A59B85-1245-4309-AC58-2CFA4199B46C= =0D - MODULE_TYPE =3D PEIM=0D - VERSION_STRING =3D 1.0=0D - LIBRARY_CLASS =3D SiliconSiFiveE51CoreInfoLib=0D -=0D -#=0D -# The following information is for reference only and not required by the = build tools.=0D -#=0D -# VALID_ARCHITECTURES =3D RISCV64=0D -#=0D -=0D -[Sources]=0D - CoreInfoHob.c=0D -=0D -[Packages]=0D - MdeModulePkg/MdeModulePkg.dec=0D - MdePkg/MdePkg.dec=0D - Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D - Silicon/SiFive/SiFive.dec=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - FirmwareContextProcessorSpecificLib=0D - MemoryAllocationLib=0D - PcdLib=0D - PrintLib=0D - RiscVEdk2SbiLib=0D -=0D -[FixedPcd]=0D - gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid=0D - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid=0D - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid=0D - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid=0D - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid=0D diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf index 9bbe2f064190..072024dc1be3 100644 --- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -29,6 +29,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec=0D Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec=0D Silicon/SiFive/SiFive.dec=0D =0D [LibraryClasses]=0D @@ -45,3 +46,6 @@ [FixedPcd] gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid=0D gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid=0D gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid=0D + gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU5MCCoreplexGuid=0D + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores=0D + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported=0D diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCore= InfoHobLib.inf b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/Pei= CoreInfoHobLib.inf deleted file mode 100644 index 89bd702b8e0f..000000000000 --- a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHob= Lib.inf +++ /dev/null @@ -1,46 +0,0 @@ -## @file=0D -# Library instance to create core information HOB=0D -#=0D -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -##=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x0001001b=0D - BASE_NAME =3D SiliconSiFiveU54MCCoreplexInfoLib=0D - FILE_GUID =3D 483DE090-267E-4278-A0A1-15D9836780EA= =0D - MODULE_TYPE =3D PEIM=0D - VERSION_STRING =3D 1.0=0D - LIBRARY_CLASS =3D SiliconSiFiveU54MCCoreplexInfoLib=0D -=0D -#=0D -# The following information is for reference only and not required by the = build tools.=0D -#=0D -# VALID_ARCHITECTURES =3D RISCV64=0D -#=0D -=0D -[Sources]=0D - CoreInfoHob.c=0D -=0D -[Packages]=0D - MdePkg/MdePkg.dec=0D - MdeModulePkg/MdeModulePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVPkg.dec=0D - Silicon/SiFive/SiFive.dec=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - PcdLib=0D - MemoryAllocationLib=0D - PrintLib=0D - SiliconSiFiveE51CoreInfoLib=0D - SiliconSiFiveU54CoreInfoLib=0D -=0D -[FixedPcd]=0D - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid=0D - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid=0D - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid=0D - gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid=0D -=0D diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextPro= cessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareC= ontextProcessorSpecificLib.h index c53d09b69eea..f3b096c257f4 100644 --- a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h +++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h @@ -39,4 +39,15 @@ CommonFirmwareContextHartSpecificInfo ( RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecDataHob=0D );=0D =0D +/**=0D + Print debug information of the processor specific data for a hart=0D +=0D + @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB=0D +**/=0D +VOID=0D +EFIAPI=0D +DebugPrintHartSpecificInfo (=0D + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob=0D + );=0D +=0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h= b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h index c19f355853ae..2f5847e53e07 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h @@ -86,8 +86,7 @@ typedef struct { ///=0D typedef struct {=0D RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCache;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCache;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;=0D RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;=0D RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;=0D } RISC_V_PROCESSOR_SMBIOS_HOB_DATA;=0D diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h b/Silicon/SiFive/In= clude/Library/SiFiveE51.h deleted file mode 100644 index 6b587661860c..000000000000 --- a/Silicon/SiFive/Include/Library/SiFiveE51.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @file=0D - SiFive E51 Core library definitions.=0D -=0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D -=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -#ifndef SIFIVE_E51_CORE_H_=0D -#define SIFIVE_E51_CORE_H_=0D -=0D -#include =0D -=0D -#include =0D -#include =0D -=0D -/**=0D - Function to build core specific information HOB.=0D -=0D - @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid=0D - could be the same as CoreGuid if one proc= essor has=0D - only one core.=0D - @param ParentProcessorUid Unique ID of pysical processor which owns= this core.=0D - @param HartId Hart ID of this core.=0D - @param IsBootHart TRUE means this is the boot HART.=0D - @param GuidHobData Pointer to receive RISC_V_PROCESSOR_SPECI= FIC_HOB_DATA.=0D -=0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CreateE51CoreProcessorSpecificDataHob (=0D - IN EFI_GUID *ParentProcessorGuid,=0D - IN UINTN ParentProcessorUid,=0D - IN UINTN HartId,=0D - IN BOOLEAN IsBootHart,=0D - OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData=0D - );=0D -=0D -/**=0D - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect=0D - this information and build SMBIOS Type4 and Type7 record.=0D -=0D - @param ProcessorUid Unique ID of pysical processor which owns this c= ore.=0D - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers=0D - maintained in this structure is only valid befor= e memory is discovered.=0D - Access to those pointers after memory is install= ed will cause unexpected issues.=0D -=0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CreateE51ProcessorSmbiosDataHob (=0D - IN UINTN ProcessorUid,=0D - OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr=0D - );=0D -=0D -#endif=0D diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h b/Silicon/SiFive/In= clude/Library/SiFiveU54.h index 9920a55309b2..ddd2b9203404 100644 --- a/Silicon/SiFive/Include/Library/SiFiveU54.h +++ b/Silicon/SiFive/Include/Library/SiFiveU54.h @@ -11,11 +11,10 @@ =0D #include =0D =0D -#include =0D #include =0D =0D /**=0D - Function to build core specific information HOB.=0D + Function to build core specific information HOB for U54 or E51 core.=0D =0D @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid=0D could be the same as CoreGuid if one proc= essor has=0D @@ -23,38 +22,55 @@ @param ParentProcessorUid Unique ID of pysical processor which owns= this core.=0D @param HartId Hart ID of this core.=0D @param IsBootHart TRUE means this is the boot HART.=0D - @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_= DATA.=0D + @param IsManagementCore TRUE means this is for the E51 management= core, not U54=0D + @param GuidHobData Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_= DATA.=0D =0D @return EFI_SUCCESS The PEIM initialized successfully.=0D =0D **/=0D EFI_STATUS=0D EFIAPI=0D -CreateU54CoreProcessorSpecificDataHob (=0D +CreateU54E51CoreProcessorSpecificDataHob (=0D IN EFI_GUID *ParentProcessorGuid,=0D IN UINTN ParentProcessorUid,=0D IN UINTN HartId,=0D IN BOOLEAN IsBootHart,=0D - OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobdata=0D - );=0D + IN BOOLEAN IsManagementCore,=0D + OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData=0D +);=0D =0D /**=0D - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect=0D - this information and build SMBIOS Type4 and Type7 record.=0D + Function to build cache related SMBIOS information. RISC-V SMBIOS DXE dr= iver collects=0D + this information and builds SMBIOS Type 7 record.=0D =0D - @param ProcessorUid Unique ID of pysical processor which owns this c= ore.=0D - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers=0D - maintained in this structure is only valid befor= e memory is discovered.=0D - Access to those pointers after memory is install= ed will cause unexpected issues.=0D + The caller can adjust the allocated hob data to their needs.=0D =0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D + @param ProcessorUid Unique ID of physical processor which owns thi= s core.=0D + @param L1CacheDataHobPtr Pointer to allocated HOB data.=0D =0D **/=0D -EFI_STATUS=0D +VOID=0D EFIAPI=0D -CreateU54ProcessorSmbiosDataHob (=0D +CreateU54SmbiosType7L1DataHob (=0D IN UINTN ProcessorUid,=0D - IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr=0D - );=0D + OUT RISC_V_PROCESSOR_TYPE7_HOB_DATA **L1CacheDataHobPtr=0D +);=0D +=0D +/**=0D + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collects=0D + this information and builds SMBIOS Type 4 record.=0D +=0D + The caller can adjust the allocated hob data to their needs.=0D +=0D + @param ProcessorUid Unique ID of physical processor which owns thi= s core.=0D + @param ProcessorDataHobPtr Pointer to allocated HOB data.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +CreateU54SmbiosType4DataHob (=0D + IN UINTN ProcessorUid,=0D + OUT RISC_V_PROCESSOR_TYPE4_HOB_DATA **ProcessorDataHobPtr=0D +);=0D =0D #endif=0D diff --git a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h b/Silicon= /SiFive/Include/Library/SiFiveU54MCCoreplex.h deleted file mode 100644 index 0e14b285543a..000000000000 --- a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h +++ /dev/null @@ -1,55 +0,0 @@ -/** @file=0D - SiFive U54 Coreplex library definitions.=0D -=0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D -=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -#ifndef SIFIVE_U54MC_COREPLEX_CORE_H_=0D -#define SIFIVE_U54MC_COREPLEX_CORE_H_=0D -=0D -#include =0D -=0D -#include =0D -#include =0D -=0D -#define SIFIVE_U54MC_COREPLEX_E51_HART_ID 0=0D -#define SIFIVE_U54MC_COREPLEX_U54_0_HART_ID 1=0D -#define SIFIVE_U54MC_COREPLEX_U54_1_HART_ID 2=0D -#define SIFIVE_U54MC_COREPLEX_U54_2_HART_ID 3=0D -#define SIFIVE_U54MC_COREPLEX_U54_3_HART_ID 4=0D -=0D -/**=0D - Build up U54MC coreplex processor core-specific information.=0D -=0D - @param UniqueId U54MC unique ID.=0D -=0D - @return EFI_STATUS=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CreateU54MCCoreplexProcessorSpecificDataHob (=0D - IN UINTN UniqueId=0D - );=0D -=0D -/**=0D - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect=0D - this information and build SMBIOS Type4 and Type7 record.=0D -=0D - @param ProcessorUid Unique ID of pysical processor which owns this c= ore.=0D - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers=0D - maintained in this structure is only valid befor= e memory is discovered.=0D - Access to those pointers after memory is install= ed will cause unexpected issues.=0D -=0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CreateU54MCProcessorSmbiosDataHob (=0D - IN UINTN ProcessorUid,=0D - IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr=0D - );=0D -#endif=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSp= ecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformP= kg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpec= ificLib.c index 066d1170c6f0..c62f77bc49ba 100644 --- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c @@ -91,3 +91,29 @@ CommonFirmwareContextHartSpecificInfo ( FirmwareContextHartSpecific->MachineImplId.Value64_H;=0D return EFI_SUCCESS;=0D }=0D +=0D +/**=0D + Print debug information of the processor specific data for a hart=0D +=0D + @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB=0D +**/=0D +VOID=0D +EFIAPI=0D +DebugPrintHartSpecificInfo (=0D + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecificDataH= ob->ProcessorSpecificData.HartId.Value64_L));=0D + DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.BootHartId));=0D + DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported));=0D + DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecificDataHob->ProcessorSpecificData.MModeExcepDelegation.Value64_L));=0D + DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecificDataHob->ProcessorSpecificData.MModeInterruptDelegation.Value6= 4_L));=0D + DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecificDat= aHob->ProcessorSpecificData.HartXlen ));=0D + DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= ificDataHob->ProcessorSpecificData.MachineModeXlen));=0D + DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecificDataHob->ProcessorSpecificData.SupervisorModeXlen));=0D + DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecifi= cDataHob->ProcessorSpecificData.UserModeXlen));=0D + DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cificDataHob->ProcessorSpecificData.InstSetSupported));=0D + DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= ificDataHob->ProcessorSpecificData.MachineVendorId.Value64_L));=0D + DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.MachineArchId.Value64_L));=0D + DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.MachineImplId.Value64_L));=0D +}=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pe= i/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Boar= d/Universal/Pei/PlatformPei/Platform.c index 3d3f67d92092..6641e10f2ec3 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf= ormPei/Platform.c +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf= ormPei/Platform.c @@ -258,7 +258,7 @@ BuildCoreInformationHob ( if (EFI_ERROR (Status)) {=0D ASSERT(FALSE);=0D }=0D - Status =3D CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr);=0D + Status =3D CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);=0D if (EFI_ERROR (Status)) {=0D ASSERT(FALSE);=0D }=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Un= iversal/Pei/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU54= 0HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c index 3d3f67d92092..6641e10f2ec3 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal= /Pei/PlatformPei/Platform.c +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal= /Pei/PlatformPei/Platform.c @@ -258,7 +258,7 @@ BuildCoreInformationHob ( if (EFI_ERROR (Status)) {=0D ASSERT(FALSE);=0D }=0D - Status =3D CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr);=0D + Status =3D CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);=0D if (EFI_ERROR (Status)) {=0D ASSERT(FALSE);=0D }=0D diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfo= Hob.c b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c index c3bb0c45128d..57c19c8187d6 100644 --- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -22,7 +22,6 @@ #include =0D #include =0D #include =0D -#include =0D #include =0D =0D /**=0D @@ -51,7 +50,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob ( ParentCoreGuid =3D PcdGetPtr(PcdSiFiveU5MCCoreplexGuid);=0D MCSupport =3D PcdGetBool (PcdE5MCSupported);=0D if (MCSupport =3D=3D TRUE) {=0D - Status =3D CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, Uniq= ueId, HartIdNumber, FALSE, &GuidHobData);=0D + Status =3D CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, U= niqueId, HartIdNumber, FALSE, TRUE, &GuidHobData);=0D if (EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\= n"));=0D ASSERT (FALSE);=0D @@ -60,7 +59,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob ( DEBUG ((DEBUG_INFO, "Support E5 Monitor core on U5 platform, HOB at ad= dress 0x%x\n", GuidHobData));=0D }=0D for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSu= pport); HartIdNumber ++) {=0D - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, Uniq= ueId, HartIdNumber, (HartIdNumber =3D=3D FixedPcdGet32 (PcdBootHartId))? TR= UE: FALSE, &GuidHobData);=0D + Status =3D CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, U= niqueId, HartIdNumber, (HartIdNumber =3D=3D FixedPcdGet32 (PcdBootHartId)),= FALSE, &GuidHobData);=0D if (EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\= n"));=0D ASSERT (FALSE);=0D @@ -83,12 +82,12 @@ CreateU5MCCoreplexProcessorSpecificDataHob ( Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect=0D this information and build SMBIOS Type4 and Type7 record.=0D =0D - @param ProcessorUid Unique ID of pysical processor which owns this c= ore.=0D + @param ProcessorUid Unique ID of physical processor which owns this = core.=0D @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers=0D maintained in this structure is only valid befor= e memory is discovered.=0D Access to those pointers after memory is install= ed will cause unexpected issues.=0D =0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D + @return EFI_SUCCESS The SMBIOS Hobs were created successfully.=0D =0D **/=0D EFI_STATUS=0D @@ -99,10 +98,10 @@ CreateU5MCProcessorSmbiosDataHob ( )=0D {=0D EFI_GUID *GuidPtr;=0D - RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;=0D RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;=0D RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;=0D RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1CacheDataHobPtr;=0D RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;=0D RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;=0D =0D @@ -112,6 +111,9 @@ CreateU5MCProcessorSmbiosDataHob ( return EFI_INVALID_PARAMETER;=0D }=0D =0D + CreateU54SmbiosType7L1DataHob (ProcessorUid, &L1CacheDataHobPtr);=0D + CreateU54SmbiosType4DataHob (ProcessorUid, &ProcessorDataHobPtr);=0D +=0D //=0D // Build up SMBIOS type 7 L2 cache record.=0D //=0D @@ -138,51 +140,12 @@ CreateU5MCProcessorSmbiosDataHob ( ASSERT (FALSE);=0D }=0D =0D - //=0D - // Build up SMBIOS type 4 record.=0D - //=0D - ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA));=0D - ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MC= CoreplexGuid));=0D - ProcessorDataHob.ProcessorUid =3D ProcessorUid;=0D - ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR;= =0D - ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor= ;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR;=0D - SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1;=0D - ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R;=0D - ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER;=0D - ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER;=0D - ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff;=0D - ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE;=0D - ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R;=0D - ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR;=0D - ProcessorDataHob.SmbiosType4Processor.CoreCount =3D (UINT8)FixedPcdGet32= (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);=0D - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D (UINT8)FixedP= cdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);=0D - ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D (UINT8)FixedPcdGet= 32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64;=0D - ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0;=0D - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0;=0D - ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);= =0D - ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA));=0D - if (ProcessorDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex = RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D -=0D ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= ));=0D SmbiosDataHob.Processor =3D ProcessorDataHobPtr;=0D - SmbiosDataHob.L1InstCache =3D NULL;=0D - SmbiosDataHob.L1DataCache =3D NULL;=0D + SmbiosDataHob.L1Cache =3D L1CacheDataHobPtr;=0D SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr;=0D SmbiosDataHob.L3Cache =3D NULL;=0D +=0D GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);=0D SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A));=0D if (SmbiosDataHobPtr =3D=3D NULL) {=0D @@ -191,5 +154,6 @@ CreateU5MCProcessorSmbiosDataHob ( }=0D *SmbiosHobPtr =3D SmbiosDataHobPtr;=0D DEBUG ((DEBUG_INFO, "%a: Exit\n", __FUNCTION__));=0D +=0D return EFI_SUCCESS;=0D }=0D diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c deleted file mode 100644 index 0f9db4012f75..000000000000 --- a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ /dev/null @@ -1,235 +0,0 @@ -/**@file=0D - Build up platform processor information.=0D -=0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D -=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -//=0D -// The package level header files this module uses=0D -//=0D -#include =0D -=0D -//=0D -// The Library classes this module consumes=0D -//=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D - Function to build core specific information HOB. RISC-V SMBIOS DXE drive= r collect=0D - this information and build SMBIOS Type44.=0D -=0D - @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid=0D - could be the same as CoreGuid if one proc= essor has=0D - only one core.=0D - @param ParentProcessorUid Unique ID of pysical processor which owns= this core.=0D - @param HartId Hart ID of this core.=0D - @param IsBootHart TRUE means this is the boot HART.=0D - @param GuidHobData Pointer to receive EFI_HOB_GUID_TYPE.=0D -=0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CreateE51CoreProcessorSpecificDataHob (=0D - IN EFI_GUID *ParentProcessorGuid,=0D - IN UINTN ParentProcessorUid,=0D - IN UINTN HartId,=0D - IN BOOLEAN IsBootHart,=0D - OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData=0D - )=0D -{=0D - RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob;=0D - EFI_GUID *ProcessorSpecDataHobGuid;=0D - RISC_V_PROCESSOR_SPECIFIC_HOB_DATA ProcessorSpecDataHob;=0D - EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;=0D - EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;=0D -=0D - DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));=0D -=0D - if (GuidHobData =3D=3D NULL) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - ASSERT_EFI_ERROR (SbiGetFirmwareContext (&FirmwareContext));=0D - DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContex= t));=0D - FirmwareContextHartSpecific =3D FirmwareContext->HartSpecific[HartId];=0D - DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", = FirmwareContextHartSpecific));=0D -=0D - //=0D - // Build up RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.=0D - //=0D - CommonFirmwareContextHartSpecificInfo (=0D - FirmwareContextHartSpecific,=0D - ParentProcessorGuid,=0D - ParentProcessorUid,=0D - (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid),=0D - HartId,=0D - IsBootHart,=0D - &ProcessorSpecDataHob=0D - );=0D - ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED;=0D - ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED;=0D - ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED;=0D - ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED;=0D - ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64;=0D - ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64;=0D - ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported;=0D - ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64;=0D -=0D - DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L));=0D - DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId));=0D - DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported));=0D - DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L));=0D - DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L))= ;=0D - DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen ));=0D - DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen));=0D - DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen));=0D - DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen));=0D - DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported));=0D - DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L));=0D - DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L));=0D - DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L));=0D -=0D - //=0D - // Build GUID HOB for E51 core, this is for SMBIOS type 44=0D - //=0D - ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid);=0D - CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_HOB_DATA));=0D - if (CoreGuidHob =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n"))= ;=0D - ASSERT (FALSE);=0D - }=0D - *GuidHobData =3D CoreGuidHob;=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect=0D - this information and build SMBIOS Type4 and Type7 record.=0D -=0D - @param ProcessorUid Unique ID of pysical processor which owns this c= ore.=0D - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers=0D - maintained in this structure is only valid befor= e memory is discovered.=0D - Access to those pointers after memory is install= ed will cause unexpected issues.=0D -=0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CreateE51ProcessorSmbiosDataHob (=0D - IN UINTN ProcessorUid,=0D - OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr=0D - )=0D -{=0D - EFI_GUID *GuidPtr;=0D - RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob;=0D - RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;=0D - RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr;=0D - RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;=0D -=0D - if (SmbiosHobPtr =3D=3D NULL) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D - //=0D - // Build up SMBIOS type 7 L1 instruction cache record.=0D - //=0D - ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_= DATA));=0D - CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveE51CoreGuid));=0D - L1InstCacheDataHob.ProcessorUid =3D ProcessorUid;=0D - L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR;=0D - L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \=0D - RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \=0D - RISC_V_CACHE_CONFIGURATION_ENABLED | \=0D - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;=0D - L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR;=0D - L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR;=0D - L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1;=0D - L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1;=0D - L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R;=0D - L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR;=0D - L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion;=0D - L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);= =0D - L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _HOB_DATA));=0D - if (L1InstCacheDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D -=0D - //=0D - // Build up SMBIOS type 4 record.=0D - //=0D - ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA));=0D - CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veE51CoreGuid));=0D - ProcessorDataHob.ProcessorUid =3D ProcessorUid;=0D - ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR;= =0D - ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor= ;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR;=0D - SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1;=0D - ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R;=0D - ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER;=0D - ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D 0xffff;=0D - ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff;=0D - ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE;=0D - ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R;=0D - ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR;=0D - ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1;=0D - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1;=0D - ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64;=0D - ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0;=0D - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0;=0D - ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);= =0D - ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA));=0D - if (ProcessorDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_TYPE4_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D -=0D - ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= ));=0D - SmbiosDataHob.Processor =3D ProcessorDataHobPtr;=0D - SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr;=0D - SmbiosDataHob.L1DataCache =3D NULL;=0D - SmbiosDataHob.L2Cache =3D NULL;=0D - SmbiosDataHob.L3Cache =3D NULL;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);=0D - SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A));=0D - if (SmbiosDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_SMBIOS_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D - *SmbiosHobPtr =3D SmbiosDataHobPtr;=0D - return EFI_SUCCESS;=0D -}=0D -=0D -=0D diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c index 70ac13326216..d013638f58ed 100644 --- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -1,7 +1,7 @@ /**@file=0D - Build up platform processor information.=0D + Build up platform processor information of SiFive U54 core.=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -9,11 +9,6 @@ =0D #include =0D =0D -//=0D -// The package level header files this module uses=0D -//=0D -#include =0D -=0D //=0D // The Library classes this module consumes=0D //=0D @@ -21,35 +16,38 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D +=0D +#include =0D #include =0D #include =0D #include =0D -#include =0D -#include =0D =0D /**=0D - Function to build core specific information HOB.=0D + Function to build core specific information HOB for U54 or E51 core.=0D =0D - @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid=0D + @param ParentProcessorGuid Parent processor of this core. ParentProc= essorGuid=0D could be the same as CoreGuid if one proc= essor has=0D only one core.=0D @param ParentProcessorUid Unique ID of pysical processor which owns= this core.=0D @param HartId Hart ID of this core.=0D @param IsBootHart TRUE means this is the boot HART.=0D - @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_= DATA.=0D + @param IsManagementCore TRUE means this is for the E51 management= core, not U54=0D + @param GuidHobData Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_= DATA.=0D =0D @return EFI_SUCCESS The PEIM initialized successfully.=0D =0D **/=0D EFI_STATUS=0D EFIAPI=0D -CreateU54CoreProcessorSpecificDataHob (=0D +CreateU54E51CoreProcessorSpecificDataHob (=0D IN EFI_GUID *ParentProcessorGuid,=0D IN UINTN ParentProcessorUid,=0D IN UINTN HartId,=0D IN BOOLEAN IsBootHart,=0D - OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobdata=0D + IN BOOLEAN IsManagementCore,=0D + OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData=0D )=0D {=0D RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob;=0D @@ -60,7 +58,7 @@ CreateU54CoreProcessorSpecificDataHob ( =0D DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));=0D =0D - if (GuidHobdata =3D=3D NULL) {=0D + if (GuidHobData =3D=3D NULL) {=0D return EFI_INVALID_PARAMETER;=0D }=0D =0D @@ -81,159 +79,112 @@ CreateU54CoreProcessorSpecificDataHob ( IsBootHart,=0D &ProcessorSpecDataHob=0D );=0D +=0D ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED;=0D ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED;=0D ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED;=0D ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED;=0D ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64;=0D ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64;=0D - ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported;=0D ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64;=0D =0D - DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L));=0D - DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId));=0D - DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported));=0D - DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L));=0D - DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L))= ;=0D - DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen ));=0D - DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen));=0D - DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen));=0D - DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen));=0D - DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported));=0D - DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L));=0D - DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L));=0D - DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L));=0D + if (IsManagementCore) {=0D + // Configuration for E51=0D + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = =3D RegisterUnsupported;=0D + } else {=0D + // Configuration for U54=0D + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = =3D RegisterLen64;=0D + }=0D +=0D +=0D + DebugPrintHartSpecificInfo (&ProcessorSpecDataHob);=0D =0D //=0D - // Build GUID HOB for U54 core.=0D + // Build GUID HOB for core, this is for SMBIOS type 44=0D //=0D ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid);=0D CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_HOB_DATA));=0D if (CoreGuidHob =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n"))= ;=0D + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core.\n"))= ;=0D ASSERT (FALSE);=0D }=0D - *GuidHobdata =3D CoreGuidHob;=0D + *GuidHobData =3D CoreGuidHob;=0D return EFI_SUCCESS;=0D }=0D =0D /**=0D - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect=0D - this information and build SMBIOS Type4 and Type7 record.=0D + Function to build cache related SMBIOS information. RISC-V SMBIOS DXE dr= iver collects=0D + this information and builds SMBIOS Type 7 record.=0D =0D - @param ProcessorUid Unique ID of pysical processor which owns this c= ore.=0D - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers=0D - maintained in this structure is only valid befor= e memory is discovered.=0D - Access to those pointers after memory is install= ed will cause unexpected issues.=0D + The caller can adjust the allocated hob data to their needs.=0D =0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D + @param ProcessorUid Unique ID of physical processor which owns thi= s core.=0D + @param L1CacheDataHobPtr Pointer to allocated HOB data.=0D =0D **/=0D -EFI_STATUS=0D +VOID=0D EFIAPI=0D -CreateU54ProcessorSmbiosDataHob (=0D +CreateU54SmbiosType7L1DataHob (=0D IN UINTN ProcessorUid,=0D - IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr=0D + OUT RISC_V_PROCESSOR_TYPE7_HOB_DATA **L1CacheDataHobPtr=0D + )=0D +{=0D + EFI_GUID *GuidPtr;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA L1CacheDataHob;=0D +=0D + //=0D + // Build up SMBIOS type 7 L1 cache record.=0D + //=0D + ZeroMem((VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA= ));=0D + L1CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCo= replexGuid));=0D + L1CacheDataHob.ProcessorUid =3D ProcessorUid;=0D + L1CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR;=0D + L1CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_1 | \=0D + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \=0D + RISC_V_CACHE_CONFIGURATION_ENABLED | \=0D + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;=0D + L1CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR;=0D + L1CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR= ;=0D + L1CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1;=0D + L1CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1;=0D + L1CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR;=0D + L1CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR;=0D + L1CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified;=0D + L1CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR= ;=0D +=0D + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);= =0D + *L1CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataH= ob (GuidPtr, (VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DA= TA));=0D + if (L1CacheDataHobPtr =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex= L1 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));=0D + ASSERT (FALSE);=0D + }=0D +}=0D +=0D +/**=0D + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collects=0D + this information and builds SMBIOS Type 4 record.=0D +=0D + The caller can adjust the allocated hob data to their needs.=0D +=0D + @param ProcessorUid Unique ID of physical processor which owns thi= s core.=0D + @param ProcessorDataHobPtr Pointer to allocated HOB data.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +CreateU54SmbiosType4DataHob (=0D + IN UINTN ProcessorUid,=0D + OUT RISC_V_PROCESSOR_TYPE4_HOB_DATA **ProcessorDataHobPtr=0D )=0D {=0D EFI_GUID *GuidPtr;=0D RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA L1DataCacheDataHob;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;=0D - RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;=0D - RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCacheDataHobPtr;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;=0D - RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;=0D -=0D - if (SmbiosHobPtr =3D=3D NULL) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D - //=0D - // Build up SMBIOS type 7 L1 instruction cache record.=0D - //=0D - ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_= DATA));=0D - CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveU54CoreGuid));=0D - L1InstCacheDataHob.ProcessorUid =3D ProcessorUid;=0D - L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR;=0D - L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \=0D - RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \=0D - RISC_V_CACHE_CONFIGURATION_ENABLED | \=0D - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;=0D - L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR;=0D - L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR;=0D - L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1;=0D - L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1;=0D - L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R;=0D - L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR;=0D - L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion;=0D - L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);= =0D - L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _HOB_DATA));=0D - if (L1InstCacheDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D -=0D - //=0D - // Build up SMBIOS type 7 L1 data cache record.=0D - //=0D - ZeroMem((VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_= DATA));=0D - CopyGuid (&L1DataCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveU54CoreGuid));=0D - L1DataCacheDataHob.ProcessorUid =3D ProcessorUid;=0D - L1DataCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR;=0D - L1DataCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \=0D - RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \=0D - RISC_V_CACHE_CONFIGURATION_ENABLED | \=0D - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;=0D - L1DataCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR;=0D - L1DataCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR;=0D - L1DataCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1;=0D - L1DataCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1;=0D - L1DataCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R;=0D - L1DataCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR;=0D - L1DataCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeData;=0D - L1DataCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);= =0D - L1DataCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _HOB_DATA));=0D - if (L1DataCacheDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 da= ta cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D -=0D - //=0D - // Build up SMBIOS type 7 L2 cache record.=0D - //=0D - ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA= ));=0D - CopyGuid (&L2CacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFive= U54CoreGuid));=0D - L2CacheDataHob.ProcessorUid =3D ProcessorUid;=0D - L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR;=0D - L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \=0D - RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \=0D - RISC_V_CACHE_CONFIGURATION_ENABLED | \=0D - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;=0D - L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR;=0D - L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR= ;=0D - L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1;=0D - L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1;=0D - L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR;=0D - L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR;=0D - L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified;=0D - L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR= ;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);= =0D - L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DAT= A));=0D - if (L2CacheDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L2 ca= che RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D =0D //=0D // Build up SMBIOS type 4 record.=0D //=0D ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA));=0D - CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veU54CoreGuid));=0D + ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MC= CoreplexGuid));=0D ProcessorDataHob.ProcessorUid =3D ProcessorUid;=0D ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR;= =0D ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor= ;=0D @@ -253,34 +204,19 @@ CreateU54ProcessorSmbiosDataHob ( ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE;=0D ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R;=0D ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR;=0D - ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1;=0D - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1;=0D - ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1;=0D + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D (UINT8)FixedPcdGet32= (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);=0D + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D (UINT8)FixedP= cdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);=0D + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D (UINT8)FixedPcdGet= 32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);=0D ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable=0D ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64;=0D ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0;=0D ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0;=0D ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0;=0D +=0D GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);= =0D - ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA));=0D + *ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDat= aHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HO= B_DATA));=0D if (ProcessorDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_= V_PROCESSOR_TYPE4_HOB_DATA.\n"));=0D + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex = RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));=0D ASSERT (FALSE);=0D }=0D -=0D - ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= ));=0D - SmbiosDataHob.Processor =3D ProcessorDataHobPtr;=0D - SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr;=0D - SmbiosDataHob.L1DataCache =3D L1DataCacheDataHobPtr;=0D - SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr;=0D - SmbiosDataHob.L3Cache =3D NULL;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);=0D - SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A));=0D - if (SmbiosDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_= V_PROCESSOR_SMBIOS_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D - *SmbiosHobPtr =3D SmbiosDataHobPtr;=0D - return EFI_SUCCESS;=0D }=0D -=0D diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInf= oHob.c b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob= .c deleted file mode 100644 index 97bed2ac8d27..000000000000 --- a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ /dev/null @@ -1,184 +0,0 @@ -/**@file=0D - Build up platform processor information.=0D -=0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D -=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -//=0D -// The package level header files this module uses=0D -//=0D -#include =0D -=0D -//=0D -// The Library classes this module consumes=0D -//=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D - Build up processor-specific HOB for U54MC Coreplex=0D -=0D - @param UniqueId Unique ID of this U54MC Coreplex processor=0D -=0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CreateU54MCCoreplexProcessorSpecificDataHob (=0D - IN UINTN UniqueId=0D - )=0D -{=0D - EFI_STATUS Status;=0D - RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ThisGuidHobData;=0D - EFI_GUID *ParentProcessorGuid;=0D -=0D - DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));=0D -=0D - ParentProcessorGuid =3D PcdGetPtr (PcdSiFiveU54MCCoreplexGuid);=0D - Status =3D CreateE51CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54MC_COREPLEX_E51_HART_ID, FALSE, &ThisGuidHobData);=0D - if (EFI_ERROR(Status)) {=0D - DEBUG ((DEBUG_ERROR, "%a: Faile to build E51 core information HOB for = U54 Coreplex.\n", __FUNCTION__));=0D - return Status;=0D - }=0D - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_0_HART_ID, TRUE, &ThisGuidHobData);=0D - if (EFI_ERROR(Status)) {=0D - DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__));=0D - return Status;=0D - }=0D - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_1_HART_ID, FALSE, &ThisGuidHobData);=0D - if (EFI_ERROR(Status)) {=0D - DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__));=0D - return Status;=0D - }=0D - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_2_HART_ID, FALSE, &ThisGuidHobData);=0D - if (EFI_ERROR(Status)) {=0D - DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__));=0D - return Status;=0D - }=0D - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_3_HART_ID, FALSE, &ThisGuidHobData);=0D - if (EFI_ERROR(Status)) {=0D - DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__));=0D - return Status;=0D - }=0D - return Status;=0D -}=0D -=0D -/**=0D - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect=0D - this information and build SMBIOS Type4 and Type7 record.=0D -=0D - @param ProcessorUid Unique ID of pysical processor which owns this c= ore.=0D - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers=0D - maintained in this structure is only valid befor= e memory is discovered.=0D - Access to those pointers after memory is install= ed will cause unexpected issues.=0D -=0D - @return EFI_SUCCESS The PEIM initialized successfully.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CreateU54MCProcessorSmbiosDataHob (=0D - IN UINTN ProcessorUid,=0D - IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr=0D - )=0D -{=0D - EFI_GUID *GuidPtr;=0D - RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;=0D - RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;=0D - RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;=0D - RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;=0D -=0D - if (SmbiosHobPtr =3D=3D NULL) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - //=0D - // Build up SMBIOS type 7 L2 cache record.=0D - //=0D - ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA= ));=0D - L2CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCC= oreplexGuid));=0D - L2CacheDataHob.ProcessorUid =3D ProcessorUid;=0D - L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR;=0D - L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \=0D - RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \=0D - RISC_V_CACHE_CONFIGURATION_ENABLED | \=0D - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;=0D - L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR;=0D - L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR= ;=0D - L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1;=0D - L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1;=0D - L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR;=0D - L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR;=0D - L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified;=0D - L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR= ;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);= =0D - L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DAT= A));=0D - if (L2CacheDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D -=0D - //=0D - // Build up SMBIOS type 4 record.=0D - //=0D - ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA));=0D - ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54M= CCoreplexGuid));=0D - ProcessorDataHob.ProcessorUid =3D ProcessorUid;=0D - ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR;= =0D - ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor= ;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR;=0D - SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1;=0D - ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R;=0D - ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR;=0D - ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER;=0D - ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER;=0D - ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff;=0D - ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE;=0D - ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R;=0D - ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR;=0D - ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 5;=0D - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 5;=0D - ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 5;=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable=0D - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64;=0D - ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0;=0D - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0;=0D - ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);= =0D - ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA));=0D - if (ProcessorDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D -=0D - ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= ));=0D - SmbiosDataHob.Processor =3D ProcessorDataHobPtr;=0D - SmbiosDataHob.L1InstCache =3D NULL;=0D - SmbiosDataHob.L1DataCache =3D NULL;=0D - SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr;=0D - SmbiosDataHob.L3Cache =3D NULL;=0D - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);=0D - SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A));=0D - if (SmbiosDataHobPtr =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54MC Coreplex= RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));=0D - ASSERT (FALSE);=0D - }=0D - *SmbiosHobPtr =3D SmbiosDataHobPtr;=0D - return EFI_SUCCESS;=0D -}=0D --=20 2.28.0