BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2884 Added new approved ECR for the CXL Protocol Error Section. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu -- --- MdePkg/Include/Guid/Cper.h | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--- MdePkg/MdePkg.dec | 3 +++ 2 files changed, 75 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Guid/Cper.h b/MdePkg/Include/Guid/Cper.h index 948f586427..28a0f3d3da 100644 --- a/MdePkg/Include/Guid/Cper.h +++ b/MdePkg/Include/Guid/Cper.h @@ -1,7 +1,7 @@ /** @file GUIDs and definitions used for Common Platform Error Record. - Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2011 - 2020, Intel Corporation. All rights reserved.
(C) Copyright 2016 Hewlett Packard Enterprise Development LP
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -10,8 +10,8 @@ **/ -#ifndef __CPER_GUID_H__ -#define __CPER_GUID_H__ +#ifndef CPER_GUID_H__ +#define CPER_GUID_H__ #pragma pack(1) @@ -1249,4 +1249,73 @@ extern EFI_GUID gEfiIa32X64ErrorTypeMsCheckGuid; #endif +// +// Compute Express Link (CXL) Protocol Error Section Descriptor body +//@{ + +/// +/// CXL Protocol Error Section Type +/// +#define EFI_ERROR_SECTION_CXL_PROTOCOL_GUID \ + { \ + 0x80B9EFB4, 0x52B5, 0x4DE3, { 0xA7, 0x77, 0x68, 0x78, 0x4B, 0x77, 0x10, 0x48 } \ + } + +// +// Validation Bits to indicate the valid fields of the error section +// +#define EFI_CXL_PROTOCOL_ERROR_AGENT_TYPE_VALID BIT0 +#define EFI_CXL_PROTOCOL_ERROR_AGENT_ADDRESS_VALID BIT1 +#define EFI_CXL_PROTOCOL_ERROR_DEVICE_ID_VALID BIT2 +#define EFI_CXL_PROTOCOL_ERROR_DEVICE_SERIAL_NUMBER_VALID BIT3 +#define EFI_CXL_PROTOCOL_ERROR_CAPABILITY_STRUCTURE_VALID BIT4 +#define EFI_CXL_PROTOCOL_ERROR_CXL_DVSEC_VALID BIT5 +#define EFI_CXL_PROTOCOL_ERROR_CXL_ERROR_LOG_VALID BIT6 + +/// +/// Compute Express Link (CXL) Protocol Error Section +/// +typedef struct { + // Indicates which of the following fields are valid + UINT64 ValidationBits; + // + // error was detected by a CXL 1.1 device (0) or downstream port (1), other + // values reserved + UINT8 CxlAgentType; + UINT8 Reserved[7]; + // + // PCI address of the CXL 1.1. Device, or RCRB base address of the + // CXL 1.1 downstream port + UINT64 CxlAgentAddress; + // + // to uniquely identify CXL 1.1 Device - Vendor, Device ID, sussystem IDs, + // Class Code and slot number + UINT16 DeviceId[8]; + // + // Device Serial NUmber of the CXL 1.1 Device + UINT64 DeviceSerialNumber; + // + // PCIe Capability Structure of the CXL 1.1 Device + UINT8 CapabilityStructure[60]; + // + // The length in bytes of the CXL DVSEC field + UINT16 CxlDvsecLength; + // + // The length in bytes of the CXL Error Log field + UINT16 CxlErrorLogLength; + UINT32 Reserved2; + // + // variable-length structure, is defined by the CXL DVSEC Length field; either + // CXL 1.1 Device or CXL 1.1 downstream port + UINT8 CxlDvsec[1]; + // + // variable-length structure, is defined by the CXL Error Log Length field; + // contains copy of its “CXL RAS Capability Structure”, as defined in the + // CXL 1.1 Specification + UINT8 CxlErrorLog[0]; +} EFI_CXL_PROTOCOL_ERROR_DATA; + +extern EFI_GUID gEfiCxlProtocolErrorSectionGuid; +//@} + #endif diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 73f6c24073..0f83b21be9 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -484,6 +484,9 @@ ## Include/Guid/Cper.h gEfiIommuDMArErrorSectionGuid = { 0x036f84e1, 0x7f37, 0x428c, { 0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec }} + ## Include/Guid/Cper.h + gEfiCxlProtocolErrorSectionGuid = { 0x80B9EFB4, 0x52B5, 0x4DE3, { 0xA7, 0x77, 0x68, 0x78, 0x4B, 0x77, 0x10, 0x48 }} + # # GUID defined in UEFI2.2 # -- 2.21.0.windows.1