From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by mx.groups.io with SMTP id smtpd.web10.89393.1597847441836881480 for ; Wed, 19 Aug 2020 07:30:41 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=V485uV8B; spf=pass (domain: linaro.org, ip: 209.85.214.195, mailfrom: tanmay.jagdale@linaro.org) Received: by mail-pl1-f195.google.com with SMTP id h2so487923plr.0 for ; Wed, 19 Aug 2020 07:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q+VlE4KKXUQTLD0ZVrze60qFGMER5eV6gL1k96KYaX0=; b=V485uV8BF2L2LHb90jMyrPgj6YT1QiSJCPI+Z8gTuRRY0LntLUz2K9M+tom9rQB0bt o30pqKDhHBPSSLPYSfanxQt+SewdjzBHuxhUvDvrW95CFM6xOsdufjeuQQoohenh1oLC hTIeo8cBAgn0WlqtvVWDf8UmhdQsdIxF2cQVknvZn+IzpwSc2psDcGPpaXpyinq+wKgy kWToDMpib6nZDysBj02XQAivQv3mkU1tFGkn5nPEY5ZgavdgUa9OEgnERpPfbaQUA6kO MXtJ08po8EOASzur3aYqO9hR3ps2hHRqv7jF343h8n5114y0QvlwlQXw8atSAEt59Wai lq5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q+VlE4KKXUQTLD0ZVrze60qFGMER5eV6gL1k96KYaX0=; b=OR22jZZqe4cutj6y9xT9yDD4msj5ufmJD8/9CLIjdK0Ti6XsWzeSRBEI/Dy8D4dqz1 Y0JNgGcl3xscjPg327OR4Csuh+Vm0ZGGMYNrVAnxiYVxfRCIXQsIwpwX1mp2NR4jwk2w XrM6S6cA/+dRzAgu0UnsOZkjkIfAGYwwOSjJDj9mkEg8cUIOgxpJSN+zEW1QWaERFSpP iPST5YHpucYGuGDOvCNBsE2voFrtbjKqj83E975cErxUrnILVzdOfo7iWR9aWzVqEUo0 MTbw6sy8UYbm48EJd25GCRuu2RHCVa6ZYQabM1mVFI8WKfUF67WgmasEcqfGnZ1ecXEy sBbA== X-Gm-Message-State: AOAM531CWuTiQ4iloCs6n5hSAI9EZakQz8f2etHngZ7Wdi4ZOufl4e9G Ln0gqxb8Gntyl8qETXQx67h9M9Mto3Un+nei X-Google-Smtp-Source: ABdhPJzCt9MvLKTutXX7hB6G1KtM7rIpNvD0ZbWnNgQLuTEY9nKxoowUTycDLvfAywaEz2xEWLt8HA== X-Received: by 2002:a17:90b:252:: with SMTP id fz18mr4290701pjb.48.1597847441331; Wed, 19 Aug 2020 07:30:41 -0700 (PDT) Return-Path: Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id y10sm3320752pjv.55.2020.08.19.07.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 07:30:40 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale , Graeme Gregory Subject: [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Date: Wed, 19 Aug 2020 20:00:00 +0530 Message-Id: <20200819143005.13999-3-tanmay.jagdale@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200819143005.13999-1-tanmay.jagdale@linaro.org> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add PCI related entries to DSDT table along with the routing entries. Also add the MCFG table. Co-authored-by: Graeme Gregory Signed-off-by: Tanmay Jagdale --- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 316 ++++++++++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 +++ 3 files changed, 360 insertions(+) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf index ee524895524e..0b5017ce81c5 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -20,6 +20,7 @@ [Sources] Fadt.aslc Gtdt.aslc Spcr.aslc + Mcfg.aslc [Packages] ArmPlatformPkg/ArmPlatformPkg.dec diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl index 85339d4559d3..2d3d4a2ddedc 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl @@ -8,6 +8,23 @@ #include +#define LINK_DEVICE(Uid, LinkName, Irq) \ + Device (LinkName) { \ + Name (_HID, EISAID("PNP0C0F")) \ + Name (_UID, Uid) \ + Name (_PRS, ResourceTemplate() { \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, Pin, Link, Zero \ + } + DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU", FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { Scope (_SB) { @@ -129,5 +146,304 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU", } // USB0_RHUB } // USB0 + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_ADR, Zero) + Name (_UID, "PCI0") + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) + + Method (_CBA, 0, NotSerialized) { + return (0xf0000000) + } + + LINK_DEVICE(0, GSI0, 0x23) + LINK_DEVICE(1, GSI1, 0x24) + LINK_DEVICE(2, GSI2, 0x25) + LINK_DEVICE(3, GSI3, 0x26) + + Name (_PRT, Package () // _PRT: PCI Routing Table + { + PRT_ENTRY(0x0000FFFF, 0, GSI0), + PRT_ENTRY(0x0000FFFF, 0, GSI1), + PRT_ENTRY(0x0000FFFF, 0, GSI2), + PRT_ENTRY(0x0000FFFF, 0, GSI3), + + PRT_ENTRY(0x0001FFFF, 0, GSI1), + PRT_ENTRY(0x0001FFFF, 1, GSI2), + PRT_ENTRY(0x0001FFFF, 2, GSI3), + PRT_ENTRY(0x0001FFFF, 3, GSI0), + + PRT_ENTRY(0x0002FFFF, 0, GSI2), + PRT_ENTRY(0x0002FFFF, 1, GSI3), + PRT_ENTRY(0x0002FFFF, 2, GSI0), + PRT_ENTRY(0x0002FFFF, 3, GSI1), + + PRT_ENTRY(0x0003FFFF, 0, GSI3), + PRT_ENTRY(0x0003FFFF, 1, GSI0), + PRT_ENTRY(0x0003FFFF, 2, GSI1), + PRT_ENTRY(0x0003FFFF, 3, GSI2), + + PRT_ENTRY(0x0004FFFF, 0, GSI0), + PRT_ENTRY(0x0004FFFF, 1, GSI1), + PRT_ENTRY(0x0004FFFF, 2, GSI2), + PRT_ENTRY(0x0004FFFF, 3, GSI3), + + PRT_ENTRY(0x0005FFFF, 0, GSI1), + PRT_ENTRY(0x0005FFFF, 1, GSI2), + PRT_ENTRY(0x0005FFFF, 2, GSI3), + PRT_ENTRY(0x0005FFFF, 3, GSI0), + + PRT_ENTRY(0x0006FFFF, 0, GSI2), + PRT_ENTRY(0x0006FFFF, 1, GSI3), + PRT_ENTRY(0x0006FFFF, 2, GSI0), + PRT_ENTRY(0x0006FFFF, 3, GSI1), + + PRT_ENTRY(0x0007FFFF, 0, GSI3), + PRT_ENTRY(0x0007FFFF, 1, GSI0), + PRT_ENTRY(0x0007FFFF, 2, GSI1), + PRT_ENTRY(0x0007FFFF, 3, GSI2), + + PRT_ENTRY(0x0008FFFF, 0, GSI0), + PRT_ENTRY(0x0008FFFF, 1, GSI1), + PRT_ENTRY(0x0008FFFF, 2, GSI2), + PRT_ENTRY(0x0008FFFF, 3, GSI3), + + PRT_ENTRY(0x0009FFFF, 0, GSI1), + PRT_ENTRY(0x0009FFFF, 1, GSI2), + PRT_ENTRY(0x0009FFFF, 2, GSI3), + PRT_ENTRY(0x0009FFFF, 3, GSI0), + + PRT_ENTRY(0x000AFFFF, 0, GSI2), + PRT_ENTRY(0x000AFFFF, 1, GSI3), + PRT_ENTRY(0x000AFFFF, 2, GSI0), + PRT_ENTRY(0x000AFFFF, 3, GSI1), + + PRT_ENTRY(0x000BFFFF, 0, GSI3), + PRT_ENTRY(0x000BFFFF, 1, GSI0), + PRT_ENTRY(0x000BFFFF, 2, GSI1), + PRT_ENTRY(0x000BFFFF, 3, GSI2), + + PRT_ENTRY(0x000CFFFF, 0, GSI0), + PRT_ENTRY(0x000CFFFF, 1, GSI1), + PRT_ENTRY(0x000CFFFF, 2, GSI2), + PRT_ENTRY(0x000CFFFF, 3, GSI3), + + PRT_ENTRY(0x000DFFFF, 0, GSI1), + PRT_ENTRY(0x000DFFFF, 1, GSI2), + PRT_ENTRY(0x000DFFFF, 2, GSI3), + PRT_ENTRY(0x000DFFFF, 3, GSI0), + + PRT_ENTRY(0x000EFFFF, 0, GSI2), + PRT_ENTRY(0x000EFFFF, 1, GSI3), + PRT_ENTRY(0x000EFFFF, 2, GSI0), + PRT_ENTRY(0x000EFFFF, 3, GSI1), + + PRT_ENTRY(0x000FFFFF, 0, GSI3), + PRT_ENTRY(0x000FFFFF, 1, GSI0), + PRT_ENTRY(0x000FFFFF, 2, GSI1), + PRT_ENTRY(0x000FFFFF, 3, GSI2), + + PRT_ENTRY(0x0010FFFF, 0, GSI0), + PRT_ENTRY(0x0010FFFF, 1, GSI1), + PRT_ENTRY(0x0010FFFF, 2, GSI2), + PRT_ENTRY(0x0010FFFF, 3, GSI3), + + PRT_ENTRY(0x0011FFFF, 0, GSI1), + PRT_ENTRY(0x0011FFFF, 1, GSI2), + PRT_ENTRY(0x0011FFFF, 2, GSI3), + PRT_ENTRY(0x0011FFFF, 3, GSI0), + + PRT_ENTRY(0x0012FFFF, 0, GSI2), + PRT_ENTRY(0x0012FFFF, 1, GSI3), + PRT_ENTRY(0x0012FFFF, 2, GSI0), + PRT_ENTRY(0x0012FFFF, 3, GSI1), + + PRT_ENTRY(0x0013FFFF, 0, GSI3), + PRT_ENTRY(0x0013FFFF, 1, GSI0), + PRT_ENTRY(0x0013FFFF, 2, GSI1), + PRT_ENTRY(0x0013FFFF, 3, GSI2), + + PRT_ENTRY(0x0014FFFF, 0, GSI0), + PRT_ENTRY(0x0014FFFF, 1, GSI1), + PRT_ENTRY(0x0014FFFF, 2, GSI2), + PRT_ENTRY(0x0014FFFF, 3, GSI3), + + PRT_ENTRY(0x0015FFFF, 0, GSI1), + PRT_ENTRY(0x0015FFFF, 1, GSI2), + PRT_ENTRY(0x0015FFFF, 2, GSI3), + PRT_ENTRY(0x0015FFFF, 3, GSI0), + + PRT_ENTRY(0x0016FFFF, 0, GSI2), + PRT_ENTRY(0x0016FFFF, 1, GSI3), + PRT_ENTRY(0x0016FFFF, 2, GSI0), + PRT_ENTRY(0x0016FFFF, 3, GSI1), + + PRT_ENTRY(0x0017FFFF, 0, GSI3), + PRT_ENTRY(0x0017FFFF, 1, GSI0), + PRT_ENTRY(0x0017FFFF, 2, GSI1), + PRT_ENTRY(0x0017FFFF, 3, GSI2), + + PRT_ENTRY(0x0018FFFF, 0, GSI0), + PRT_ENTRY(0x0018FFFF, 1, GSI1), + PRT_ENTRY(0x0018FFFF, 2, GSI2), + PRT_ENTRY(0x0018FFFF, 3, GSI3), + + PRT_ENTRY(0x0019FFFF, 0, GSI1), + PRT_ENTRY(0x0019FFFF, 1, GSI2), + PRT_ENTRY(0x0019FFFF, 2, GSI3), + PRT_ENTRY(0x0019FFFF, 3, GSI0), + + PRT_ENTRY(0x001AFFFF, 0, GSI2), + PRT_ENTRY(0x001AFFFF, 1, GSI3), + PRT_ENTRY(0x001AFFFF, 2, GSI0), + PRT_ENTRY(0x001AFFFF, 3, GSI1), + + PRT_ENTRY(0x001BFFFF, 0, GSI3), + PRT_ENTRY(0x001BFFFF, 1, GSI0), + PRT_ENTRY(0x001BFFFF, 2, GSI1), + PRT_ENTRY(0x001BFFFF, 3, GSI2), + + PRT_ENTRY(0x001CFFFF, 0, GSI0), + PRT_ENTRY(0x001CFFFF, 1, GSI1), + PRT_ENTRY(0x001CFFFF, 2, GSI2), + PRT_ENTRY(0x001CFFFF, 3, GSI3), + + PRT_ENTRY(0x001DFFFF, 0, GSI1), + PRT_ENTRY(0x001DFFFF, 1, GSI2), + PRT_ENTRY(0x001DFFFF, 2, GSI3), + PRT_ENTRY(0x001DFFFF, 3, GSI0), + + PRT_ENTRY(0x001EFFFF, 0, GSI2), + PRT_ENTRY(0x001EFFFF, 1, GSI3), + PRT_ENTRY(0x001EFFFF, 2, GSI0), + PRT_ENTRY(0x001EFFFF, 3, GSI1), + + PRT_ENTRY(0x001FFFFF, 0, GSI3), + PRT_ENTRY(0x001FFFFF, 1, GSI0), + PRT_ENTRY(0x001FFFFF, 2, GSI1), + PRT_ENTRY(0x001FFFFF, 3, GSI2), + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min Base Address + 0xEFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x70000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x100000000, // Min Base Address + 0xFFFFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0xFF00000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x0000ffff, // Max Base Address + 0x7fff0000, // Translate + 0x00010000, // Length + ,,,TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000000F0000000, // Range Minimum + 0x00000000FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + // OS Control Handoff + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + * See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC,4) { + // Check for proper UUID + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3,0,CDW1) + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If (LNotEqual(And(SUPP, 0x16), 0x16)) { + And (CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And (CTRL,0x1D,CTRL) + + If (LNotEqual(Arg1,One)) { // Unknown revision + Or (CDW1,0x08,CDW1) + } + + If (LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or (CDW1,0x10,CDW1) + } + + // Update DWORD3 in the buffer + Store (CTRL,CDW3) + Return (Arg3) + } Else { + Or (CDW1,4,CDW1) // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } } // Scope (_SB) } diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc new file mode 100644 index 000000000000..e78061f9fe1c --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc @@ -0,0 +1,43 @@ +/** @file +* ACPI Memory mapped configuration space base address Description Table (MCFG). +* +* Copyright (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#pragma pack(push, 1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2]; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { + { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), + EFI_ACPI_RESERVED_QWORD + }, + { + { + SBSAQEMU_PCI_SEG0_CONFIG_BASE, + 0, + SBSAQEMU_PCI_SEG0_BUSNUM_MIN, + SBSAQEMU_PCI_SEG0_BUSNUM_MAX, + EFI_ACPI_RESERVED_DWORD + } + } +}; + +#pragma pack(pop) + +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +VOID* CONST ReferenceAcpiTable = &Mcfg; -- 2.28.0