* [PATCH edk2-platforms 1/7] SbsaQemu: Initial support for static ACPI tables
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
@ 2020-08-19 14:29 ` Tanmay Jagdale
2020-08-20 11:35 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Tanmay Jagdale
` (6 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Tanmay Jagdale @ 2020-08-19 14:29 UTC (permalink / raw)
To: leif, graeme, shashi.mallela, devel
Cc: paul.isaacs, tanmay, Tanmay Jagdale, Graeme Gregory,
Jonathan Cameron
- Add the following ACPI tables for SbsaQemu platform
DSDT, FADT, GTDT, SPCR
- Created an Include directory to hold common header files.
- Also included the Acpiview shell utility.
Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Co-authored-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 8 ++
Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 35 +++++
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 45 ++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 133 ++++++++++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 80 +++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 67 +++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 53 +++++++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 31 ++++
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 +-
10 files changed, 460 insertions(+), 2 deletions(-)
create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
create mode 100644 Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 4db3ab465163..4739443cae93 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -516,6 +516,7 @@ [Components.common]
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
@@ -675,3 +676,8 @@ [Components.common]
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # ACPI Support
+!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
+ MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
index be7c78acebfd..4526eaaa02c5 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
@@ -227,6 +227,14 @@ [FV.FvMain]
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ #
+ # ACPI support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+ INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+
#
# PCI support
#
diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
new file mode 100644
index 000000000000..c4a8d7a27b78
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2020, Linaro Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LINARO"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x554D455141534253 #SBSAQEMU
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20200810
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c #LNRO
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+
+[Components.common]
+ #
+ # ACPI support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000000..ee524895524e
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -0,0 +1,45 @@
+## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2020, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SbsaAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
new file mode 100644
index 000000000000..85339d4559d3
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -0,0 +1,133 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT).
+*
+* Copyright (c) 2020, Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <IndustryStandard/SbsaQemuAcpi.h>
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
+ FixedPcdGet32 (PcdAcpiDefaultOemRevision)) {
+ Scope (_SB) {
+ // UART PL011
+ Device (COM0) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, Zero)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x60000000, 0x00001000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
+ })
+ }
+
+ // AHCI Host Controller
+ Device (AHC0) {
+ Name (_HID, "LNRO001E")
+ Name (_CLS, Package (3) {
+ 0x01,
+ 0x06,
+ 0x01,
+ })
+ Name (_CCA, 1)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, 0x60100000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
+ })
+ }
+
+ // USB EHCI Host Controller
+ Device (USB0) {
+ Name (_HID, "LNRO0D20")
+ Name (_CID, "PNP0D20")
+
+ Method (_CRS, 0x0, Serialized) {
+ Name (RBUF, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, 0x60110000, 0x00010000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
+ })
+ Return (RBUF)
+ }
+
+ // Root Hub
+ Device (RHUB) {
+ Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec
+
+ // Ports connected to Root Hub
+ Device (HUB1) {
+ Name (_ADR, 0x00000001)
+ Name (_UPC, Package() {
+ 0x00, // Port is NOT connectable
+ 0xFF, // Don't care
+ 0x00000000, // Reserved 0 must be zero
+ 0x00000000 // Reserved 1 must be zero
+ })
+
+ Device (PRT1) {
+ Name (_ADR, 0x00000001)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer(0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT1
+ Device (PRT2) {
+ Name (_ADR, 0x00000002)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer(0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT2
+
+ Device (PRT3) {
+ Name (_ADR, 0x00000003)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer (0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT3
+
+ Device (PRT4) {
+ Name (_ADR, 0x00000004)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer (0x10){
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT4
+ } // USB0_RHUB_HUB1
+ } // USB0_RHUB
+ } // USB0
+
+ } // Scope (_SB)
+}
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
new file mode 100644
index 000000000000..894b848db8bb
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
@@ -0,0 +1,80 @@
+/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2020, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_0_HW_REDUCED_ACPI |
+ EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // GAS ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
+ // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // GAS XPm1aEvtBlk
+ NULL_GAS, // GAS XPm1bEvtBlk
+ NULL_GAS, // GAS XPm1aCntBlk
+ NULL_GAS, // GAS XPm1bCntBlk
+ NULL_GAS, // GAS XPm2CntBlk
+ NULL_GAS, // GAS XPmTmrBlk
+ NULL_GAS, // GAS XGpe0Blk
+ NULL_GAS, // GAS XGpe1Blk
+ NULL_GAS, // GAS SleepControlReg
+ NULL_GAS, // GAS SleepStatusReg
+ 0 // UINT64 HypervisorVendorId
+};
+
+// Reference the table being generated to prevent the optimizer
+// from removing the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
new file mode 100644
index 000000000000..52496acc449b
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
@@ -0,0 +1,67 @@
+/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyrignt (c) 2020, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+ #pragma pack (1)
+
+ typedef struct {
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ } GENERIC_TIMER_DESCRIPTION_TABLE;
+
+ #pragma pack ()
+
+ GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
+ {
+ SBSAQEMU_ACPI_HEADER(
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ GENERIC_TIMER_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+ 0, // UINT32 PlatformTimerCount
+ 0
+ },
+ };
+
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
new file mode 100644
index 000000000000..7b8ab7b6942f
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
@@ -0,0 +1,53 @@
+/** @file
+* Serial Port Console Redirection Table (SPCR).
+*
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <IndustryStandard/Acpi60.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ 2), /* New MS definition for PL011 support */
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
+ {
+ EFI_ACPI_6_0_SYSTEM_MEMORY,
+ 32,
+ 0,
+ EFI_ACPI_6_0_DWORD,
+ SBSAQEMU_UART0_BASE
+ },
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+ 0, /* Irq */
+ 33, /* GlobalSystemInterrupt */
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ 0, /* Flow Control */
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ EFI_ACPI_RESERVED_BYTE, /* Language */
+ 0xFFFF, /* PciDeviceId */
+ 0xFFFF, /* PciVendorId */
+ 0x00, /* PciBusNumber */
+ 0x00, /* PciDeviceNumber */
+ 0x00, /* PciFunctionNumber */
+ 0, /* PciFlags */
+ 0, /* PciSegment */
+ EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
new file mode 100644
index 000000000000..eac195b0585c
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -0,0 +1,31 @@
+/** @file
+*
+* Copyright (c) 2020, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef SBSAQEMUACPI_H
+#define SBSAQEMUACPI_H
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define SBSAQEMU_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { 'L', 'I', 'N', 'A', 'R', 'O' }, /* UINT8 OemId[6] */ \
+ FixedPcdGet64 (PcdAcpiDefaultOemTableId), /* UINT64 OemTableId */ \
+ FixedPcdGet32 (PcdAcpiDefaultOemRevision), /* UINT32 OemRevision */ \
+ FixedPcdGet32 (PcdAcpiDefaultCreatorId), /* UINT32 CreatorId */ \
+ FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \
+ }
+
+#define SBSAQEMU_UART0_BASE 0x60000000
+
+#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
+#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00
+#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF
+
+#endif
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index cd879f4dbd96..71ba55a082e2 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -21,8 +21,8 @@ [Defines]
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
-#[Includes.common]
-# Include # Root include for the package
+[Includes]
+ Include # Root include for the package
[Guids.common]
gArmVirtSbsaQemuPlatformTokenSpaceGuid = { 0xaab3bea9, 0xa8e8, 0x4e76, { 0xb5, 0x3a, 0x35, 0x22, 0x11, 0xce, 0xf7, 0xf7 } }
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH edk2-platforms 1/7] SbsaQemu: Initial support for static ACPI tables
2020-08-19 14:29 ` [PATCH edk2-platforms 1/7] SbsaQemu: Initial support for static ACPI tables Tanmay Jagdale
@ 2020-08-20 11:35 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2020-08-20 11:35 UTC (permalink / raw)
To: Tanmay Jagdale
Cc: graeme, shashi.mallela, devel, paul.isaacs, tanmay,
Graeme Gregory, Jonathan Cameron
On Wed, Aug 19, 2020 at 19:59:59 +0530, Tanmay Jagdale wrote:
> - Add the following ACPI tables for SbsaQemu platform
> DSDT, FADT, GTDT, SPCR
> - Created an Include directory to hold common header files.
> - Also included the Acpiview shell utility.
>
> Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
> Co-authored-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +
> Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 8 ++
> Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 35 +++++
> .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 45 ++++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 133 ++++++++++++++++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 80 +++++++++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 67 +++++++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 53 +++++++
> .../Include/IndustryStandard/SbsaQemuAcpi.h | 31 ++++
> Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 +-
I am mostly happy with this patch, but the above does not follow the
guidelines in
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-git-guide-for-edk2-contributors-and-maintainers#contrib-23
Two key points:
- need to add "--stat=1000 --stat-graph-width=20" to git format-patch
command line
- need to run <edk2>/BaseTools/Scripts/SetupGit.py in your
edk2-platforms repository
- There *was* a bug that meant the diff.OrderFile setting had no
effect, but that is fixed in upstream edk2, so make sure you're
staying current. (No need to re-run script if you already have,
updating edk2 solves the issue.)
I have some minor comments on remaining patches, so please do send out
a v2 once I've finished, following the above.
If v2 of this patch has no "..." in diffstat paths, and the .dec is the
first file listed:
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> 10 files changed, 460 insertions(+), 2 deletions(-)
> create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
>
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> index 4db3ab465163..4739443cae93 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> @@ -516,6 +516,7 @@ [Components.common]
> ShellPkg/Application/Shell/Shell.inf {
> <LibraryClasses>
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> @@ -675,3 +676,8 @@ [Components.common]
> MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> + #
> + # ACPI Support
> +!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> index be7c78acebfd..4526eaaa02c5 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> @@ -227,6 +227,14 @@ [FV.FvMain]
> INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
>
> + #
> + # ACPI support
> + #
> + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> + INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
> +
> #
> # PCI support
> #
> diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> new file mode 100644
> index 000000000000..c4a8d7a27b78
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> @@ -0,0 +1,35 @@
> +#
> +# Copyright (c) 2020, Linaro Limited. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> +
> +[PcdsFixedAtBuild.common]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LINARO"
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x554D455141534253 #SBSAQEMU
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20200810
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c #LNRO
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +
> +[Components.common]
> + #
> + # ACPI support
> + #
> + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> + Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> new file mode 100644
> index 000000000000..ee524895524e
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> @@ -0,0 +1,45 @@
> +## @file
> +#
> +# ACPI table data and ASL sources required to boot the platform.
> +#
> +# Copyright (c) 2020, Linaro Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = SbsaAcpiTables
> + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + Dsdt.asl
> + Fadt.aslc
> + Gtdt.aslc
> + Spcr.aslc
> +
> +[Packages]
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + ArmPkg/ArmPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +
> + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> new file mode 100644
> index 000000000000..85339d4559d3
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> @@ -0,0 +1,133 @@
> +/** @file
> +* Differentiated System Description Table Fields (DSDT).
> +*
> +* Copyright (c) 2020, Linaro Ltd. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <IndustryStandard/SbsaQemuAcpi.h>
> +
> +DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
> + FixedPcdGet32 (PcdAcpiDefaultOemRevision)) {
> + Scope (_SB) {
> + // UART PL011
> + Device (COM0) {
> + Name (_HID, "ARMH0011")
> + Name (_UID, Zero)
> + Name (_CRS, ResourceTemplate () {
> + Memory32Fixed (ReadWrite, 0x60000000, 0x00001000)
> + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
> + })
> + }
> +
> + // AHCI Host Controller
> + Device (AHC0) {
> + Name (_HID, "LNRO001E")
> + Name (_CLS, Package (3) {
> + 0x01,
> + 0x06,
> + 0x01,
> + })
> + Name (_CCA, 1)
> + Name (_CRS, ResourceTemplate() {
> + Memory32Fixed (ReadWrite, 0x60100000, 0x1000)
> + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
> + })
> + }
> +
> + // USB EHCI Host Controller
> + Device (USB0) {
> + Name (_HID, "LNRO0D20")
> + Name (_CID, "PNP0D20")
> +
> + Method (_CRS, 0x0, Serialized) {
> + Name (RBUF, ResourceTemplate() {
> + Memory32Fixed (ReadWrite, 0x60110000, 0x00010000)
> + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
> + })
> + Return (RBUF)
> + }
> +
> + // Root Hub
> + Device (RHUB) {
> + Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec
> +
> + // Ports connected to Root Hub
> + Device (HUB1) {
> + Name (_ADR, 0x00000001)
> + Name (_UPC, Package() {
> + 0x00, // Port is NOT connectable
> + 0xFF, // Don't care
> + 0x00000000, // Reserved 0 must be zero
> + 0x00000000 // Reserved 1 must be zero
> + })
> +
> + Device (PRT1) {
> + Name (_ADR, 0x00000001)
> + Name (_UPC, Package() {
> + 0xFF, // Port is connectable
> + 0x00, // Port connector is A
> + 0x00000000,
> + 0x00000000
> + })
> + Name (_PLD, Package() {
> + Buffer(0x10) {
> + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> + }
> + })
> + } // USB0_RHUB_HUB1_PRT1
> + Device (PRT2) {
> + Name (_ADR, 0x00000002)
> + Name (_UPC, Package() {
> + 0xFF, // Port is connectable
> + 0x00, // Port connector is A
> + 0x00000000,
> + 0x00000000
> + })
> + Name (_PLD, Package() {
> + Buffer(0x10) {
> + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> + }
> + })
> + } // USB0_RHUB_HUB1_PRT2
> +
> + Device (PRT3) {
> + Name (_ADR, 0x00000003)
> + Name (_UPC, Package() {
> + 0xFF, // Port is connectable
> + 0x00, // Port connector is A
> + 0x00000000,
> + 0x00000000
> + })
> + Name (_PLD, Package() {
> + Buffer (0x10) {
> + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> + }
> + })
> + } // USB0_RHUB_HUB1_PRT3
> +
> + Device (PRT4) {
> + Name (_ADR, 0x00000004)
> + Name (_UPC, Package() {
> + 0xFF, // Port is connectable
> + 0x00, // Port connector is A
> + 0x00000000,
> + 0x00000000
> + })
> + Name (_PLD, Package() {
> + Buffer (0x10){
> + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> + }
> + })
> + } // USB0_RHUB_HUB1_PRT4
> + } // USB0_RHUB_HUB1
> + } // USB0_RHUB
> + } // USB0
> +
> + } // Scope (_SB)
> +}
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
> new file mode 100644
> index 000000000000..894b848db8bb
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
> @@ -0,0 +1,80 @@
> +/** @file
> +* Fixed ACPI Description Table (FADT)
> +*
> +* Copyright (c) 2020, Linaro Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Library/AcpiLib.h>
> +#include <IndustryStandard/Acpi.h>
> +#include <IndustryStandard/SbsaQemuAcpi.h>
> +
> +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
> + SBSAQEMU_ACPI_HEADER (
> + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
> + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
> + ),
> + 0, // UINT32 FirmwareCtrl
> + 0, // UINT32 Dsdt
> + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
> + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
> + 0, // UINT16 SciInt
> + 0, // UINT32 SmiCmd
> + 0, // UINT8 AcpiEnable
> + 0, // UINT8 AcpiDisable
> + 0, // UINT8 S4BiosReq
> + 0, // UINT8 PstateCnt
> + 0, // UINT32 Pm1aEvtBlk
> + 0, // UINT32 Pm1bEvtBlk
> + 0, // UINT32 Pm1aCntBlk
> + 0, // UINT32 Pm1bCntBlk
> + 0, // UINT32 Pm2CntBlk
> + 0, // UINT32 PmTmrBlk
> + 0, // UINT32 Gpe0Blk
> + 0, // UINT32 Gpe1Blk
> + 0, // UINT8 Pm1EvtLen
> + 0, // UINT8 Pm1CntLen
> + 0, // UINT8 Pm2CntLen
> + 0, // UINT8 PmTmrLen
> + 0, // UINT8 Gpe0BlkLen
> + 0, // UINT8 Gpe1BlkLen
> + 0, // UINT8 Gpe1Base
> + 0, // UINT8 CstCnt
> + 0, // UINT16 PLvl2Lat
> + 0, // UINT16 PLvl3Lat
> + 0, // UINT16 FlushSize
> + 0, // UINT16 FlushStride
> + 0, // UINT8 DutyOffset
> + 0, // UINT8 DutyWidth
> + 0, // UINT8 DayAlrm
> + 0, // UINT8 MonAlrm
> + 0, // UINT8 Century
> + 0, // UINT16 IaPcBootArch
> + 0, // UINT8 Reserved1
> + EFI_ACPI_6_0_HW_REDUCED_ACPI |
> + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
> + NULL_GAS, // GAS ResetReg
> + 0, // UINT8 ResetValue
> + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
> + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
> + // UINT8 MinorRevision
> + 0, // UINT64 XFirmwareCtrl
> + 0, // UINT64 XDsdt
> + NULL_GAS, // GAS XPm1aEvtBlk
> + NULL_GAS, // GAS XPm1bEvtBlk
> + NULL_GAS, // GAS XPm1aCntBlk
> + NULL_GAS, // GAS XPm1bCntBlk
> + NULL_GAS, // GAS XPm2CntBlk
> + NULL_GAS, // GAS XPmTmrBlk
> + NULL_GAS, // GAS XGpe0Blk
> + NULL_GAS, // GAS XGpe1Blk
> + NULL_GAS, // GAS SleepControlReg
> + NULL_GAS, // GAS SleepStatusReg
> + 0 // UINT64 HypervisorVendorId
> +};
> +
> +// Reference the table being generated to prevent the optimizer
> +// from removing the data structure from the executable
> +VOID* CONST ReferenceAcpiTable = &Fadt;
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
> new file mode 100644
> index 000000000000..52496acc449b
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
> @@ -0,0 +1,67 @@
> +/** @file
> +* Generic Timer Description Table (GTDT)
> +*
> +* Copyrignt (c) 2020, Linaro Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Library/AcpiLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +#include <IndustryStandard/SbsaQemuAcpi.h>
> +
> +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
> +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
> +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
> +#define GTDT_GLOBAL_FLAGS_LEVEL 0
> +
> +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
> +#ifdef SYSTEM_TIMER_BASE_ADDRESS
> + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> +#else
> + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
> +#endif
> +
> +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
> +#define GTDT_TIMER_LEVEL_TRIGGERED 0
> +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
> +#define GTDT_TIMER_ACTIVE_HIGH 0
> +
> +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
> +
> + #pragma pack (1)
> +
> + typedef struct {
> + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
> + } GENERIC_TIMER_DESCRIPTION_TABLE;
> +
> + #pragma pack ()
> +
> + GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
> + {
> + SBSAQEMU_ACPI_HEADER(
> + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
> + GENERIC_TIMER_DESCRIPTION_TABLE,
> + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
> + ),
> + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
> + 0, // UINT32 Reserved
> + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
> + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
> + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
> + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
> + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
> + 0, // UINT32 PlatformTimerCount
> + 0
> + },
> + };
> +
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +VOID* CONST ReferenceAcpiTable = &Gtdt;
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
> new file mode 100644
> index 000000000000..7b8ab7b6942f
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
> @@ -0,0 +1,53 @@
> +/** @file
> +* Serial Port Console Redirection Table (SPCR).
> +*
> +* Copyright (c) 2020 Linaro Ltd. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <IndustryStandard/Acpi60.h>
> +#include <IndustryStandard/SbsaQemuAcpi.h>
> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
> +
> +#pragma pack(push, 1)
> +
> +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
> + SBSAQEMU_ACPI_HEADER (
> + EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
> + 2), /* New MS definition for PL011 support */
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
> + {
> + EFI_ACPI_6_0_SYSTEM_MEMORY,
> + 32,
> + 0,
> + EFI_ACPI_6_0_DWORD,
> + SBSAQEMU_UART0_BASE
> + },
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
> + 0, /* Irq */
> + 33, /* GlobalSystemInterrupt */
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
> + 0, /* Flow Control */
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
> + EFI_ACPI_RESERVED_BYTE, /* Language */
> + 0xFFFF, /* PciDeviceId */
> + 0xFFFF, /* PciVendorId */
> + 0x00, /* PciBusNumber */
> + 0x00, /* PciDeviceNumber */
> + 0x00, /* PciFunctionNumber */
> + 0, /* PciFlags */
> + 0, /* PciSegment */
> + EFI_ACPI_RESERVED_DWORD
> +};
> +
> +#pragma pack(pop)
> +
> +// Reference the table being generated to prevent the optimizer from removing
> +// the data structure from the executable
> +VOID* CONST ReferenceAcpiTable = &Spcr;
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> new file mode 100644
> index 000000000000..eac195b0585c
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -0,0 +1,31 @@
> +/** @file
> +*
> +* Copyright (c) 2020, Linaro Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef SBSAQEMUACPI_H
> +#define SBSAQEMUACPI_H
> +
> +// A macro to initialise the common header part of EFI ACPI tables as defined by
> +// EFI_ACPI_DESCRIPTION_HEADER structure.
> +#define SBSAQEMU_ACPI_HEADER(Signature, Type, Revision) { \
> + Signature, /* UINT32 Signature */ \
> + sizeof (Type), /* UINT32 Length */ \
> + Revision, /* UINT8 Revision */ \
> + 0, /* UINT8 Checksum */ \
> + { 'L', 'I', 'N', 'A', 'R', 'O' }, /* UINT8 OemId[6] */ \
> + FixedPcdGet64 (PcdAcpiDefaultOemTableId), /* UINT64 OemTableId */ \
> + FixedPcdGet32 (PcdAcpiDefaultOemRevision), /* UINT32 OemRevision */ \
> + FixedPcdGet32 (PcdAcpiDefaultCreatorId), /* UINT32 CreatorId */ \
> + FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \
> + }
> +
> +#define SBSAQEMU_UART0_BASE 0x60000000
> +
> +#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
> +#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00
> +#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF
> +
> +#endif
> diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> index cd879f4dbd96..71ba55a082e2 100644
> --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> @@ -21,8 +21,8 @@ [Defines]
> # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> #
> ################################################################################
> -#[Includes.common]
> -# Include # Root include for the package
> +[Includes]
> + Include # Root include for the package
>
> [Guids.common]
> gArmVirtSbsaQemuPlatformTokenSpaceGuid = { 0xaab3bea9, 0xa8e8, 0x4e76, { 0xb5, 0x3a, 0x35, 0x22, 0x11, 0xce, 0xf7, 0xf7 } }
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
2020-08-19 14:29 ` [PATCH edk2-platforms 1/7] SbsaQemu: Initial support for static ACPI tables Tanmay Jagdale
@ 2020-08-19 14:30 ` Tanmay Jagdale
2020-08-20 11:40 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 3/7] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs Tanmay Jagdale
` (5 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Tanmay Jagdale @ 2020-08-19 14:30 UTC (permalink / raw)
To: leif, graeme, shashi.mallela, devel
Cc: paul.isaacs, tanmay, Tanmay Jagdale, Graeme Gregory
Add PCI related entries to DSDT table along with the routing
entries. Also add the MCFG table.
Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 316 ++++++++++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 +++
3 files changed, 360 insertions(+)
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index ee524895524e..0b5017ce81c5 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -20,6 +20,7 @@ [Sources]
Fadt.aslc
Gtdt.aslc
Spcr.aslc
+ Mcfg.aslc
[Packages]
ArmPlatformPkg/ArmPlatformPkg.dec
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index 85339d4559d3..2d3d4a2ddedc 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -8,6 +8,23 @@
#include <IndustryStandard/SbsaQemuAcpi.h>
+#define LINK_DEVICE(Uid, LinkName, Irq) \
+ Device (LinkName) { \
+ Name (_HID, EISAID("PNP0C0F")) \
+ Name (_UID, Uid) \
+ Name (_PRS, ResourceTemplate() { \
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, Pin, Link, Zero \
+ }
+
DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
FixedPcdGet32 (PcdAcpiDefaultOemRevision)) {
Scope (_SB) {
@@ -129,5 +146,304 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
} // USB0_RHUB
} // USB0
+ Device (PCI0)
+ {
+ Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_ADR, Zero)
+ Name (_UID, "PCI0")
+ Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1)
+
+ Method (_CBA, 0, NotSerialized) {
+ return (0xf0000000)
+ }
+
+ LINK_DEVICE(0, GSI0, 0x23)
+ LINK_DEVICE(1, GSI1, 0x24)
+ LINK_DEVICE(2, GSI2, 0x25)
+ LINK_DEVICE(3, GSI3, 0x26)
+
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ PRT_ENTRY(0x0000FFFF, 0, GSI0),
+ PRT_ENTRY(0x0000FFFF, 0, GSI1),
+ PRT_ENTRY(0x0000FFFF, 0, GSI2),
+ PRT_ENTRY(0x0000FFFF, 0, GSI3),
+
+ PRT_ENTRY(0x0001FFFF, 0, GSI1),
+ PRT_ENTRY(0x0001FFFF, 1, GSI2),
+ PRT_ENTRY(0x0001FFFF, 2, GSI3),
+ PRT_ENTRY(0x0001FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0002FFFF, 0, GSI2),
+ PRT_ENTRY(0x0002FFFF, 1, GSI3),
+ PRT_ENTRY(0x0002FFFF, 2, GSI0),
+ PRT_ENTRY(0x0002FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0003FFFF, 0, GSI3),
+ PRT_ENTRY(0x0003FFFF, 1, GSI0),
+ PRT_ENTRY(0x0003FFFF, 2, GSI1),
+ PRT_ENTRY(0x0003FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0004FFFF, 0, GSI0),
+ PRT_ENTRY(0x0004FFFF, 1, GSI1),
+ PRT_ENTRY(0x0004FFFF, 2, GSI2),
+ PRT_ENTRY(0x0004FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0005FFFF, 0, GSI1),
+ PRT_ENTRY(0x0005FFFF, 1, GSI2),
+ PRT_ENTRY(0x0005FFFF, 2, GSI3),
+ PRT_ENTRY(0x0005FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0006FFFF, 0, GSI2),
+ PRT_ENTRY(0x0006FFFF, 1, GSI3),
+ PRT_ENTRY(0x0006FFFF, 2, GSI0),
+ PRT_ENTRY(0x0006FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0007FFFF, 0, GSI3),
+ PRT_ENTRY(0x0007FFFF, 1, GSI0),
+ PRT_ENTRY(0x0007FFFF, 2, GSI1),
+ PRT_ENTRY(0x0007FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0008FFFF, 0, GSI0),
+ PRT_ENTRY(0x0008FFFF, 1, GSI1),
+ PRT_ENTRY(0x0008FFFF, 2, GSI2),
+ PRT_ENTRY(0x0008FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0009FFFF, 0, GSI1),
+ PRT_ENTRY(0x0009FFFF, 1, GSI2),
+ PRT_ENTRY(0x0009FFFF, 2, GSI3),
+ PRT_ENTRY(0x0009FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x000AFFFF, 0, GSI2),
+ PRT_ENTRY(0x000AFFFF, 1, GSI3),
+ PRT_ENTRY(0x000AFFFF, 2, GSI0),
+ PRT_ENTRY(0x000AFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x000BFFFF, 0, GSI3),
+ PRT_ENTRY(0x000BFFFF, 1, GSI0),
+ PRT_ENTRY(0x000BFFFF, 2, GSI1),
+ PRT_ENTRY(0x000BFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x000CFFFF, 0, GSI0),
+ PRT_ENTRY(0x000CFFFF, 1, GSI1),
+ PRT_ENTRY(0x000CFFFF, 2, GSI2),
+ PRT_ENTRY(0x000CFFFF, 3, GSI3),
+
+ PRT_ENTRY(0x000DFFFF, 0, GSI1),
+ PRT_ENTRY(0x000DFFFF, 1, GSI2),
+ PRT_ENTRY(0x000DFFFF, 2, GSI3),
+ PRT_ENTRY(0x000DFFFF, 3, GSI0),
+
+ PRT_ENTRY(0x000EFFFF, 0, GSI2),
+ PRT_ENTRY(0x000EFFFF, 1, GSI3),
+ PRT_ENTRY(0x000EFFFF, 2, GSI0),
+ PRT_ENTRY(0x000EFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x000FFFFF, 0, GSI3),
+ PRT_ENTRY(0x000FFFFF, 1, GSI0),
+ PRT_ENTRY(0x000FFFFF, 2, GSI1),
+ PRT_ENTRY(0x000FFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0010FFFF, 0, GSI0),
+ PRT_ENTRY(0x0010FFFF, 1, GSI1),
+ PRT_ENTRY(0x0010FFFF, 2, GSI2),
+ PRT_ENTRY(0x0010FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0011FFFF, 0, GSI1),
+ PRT_ENTRY(0x0011FFFF, 1, GSI2),
+ PRT_ENTRY(0x0011FFFF, 2, GSI3),
+ PRT_ENTRY(0x0011FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0012FFFF, 0, GSI2),
+ PRT_ENTRY(0x0012FFFF, 1, GSI3),
+ PRT_ENTRY(0x0012FFFF, 2, GSI0),
+ PRT_ENTRY(0x0012FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0013FFFF, 0, GSI3),
+ PRT_ENTRY(0x0013FFFF, 1, GSI0),
+ PRT_ENTRY(0x0013FFFF, 2, GSI1),
+ PRT_ENTRY(0x0013FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0014FFFF, 0, GSI0),
+ PRT_ENTRY(0x0014FFFF, 1, GSI1),
+ PRT_ENTRY(0x0014FFFF, 2, GSI2),
+ PRT_ENTRY(0x0014FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0015FFFF, 0, GSI1),
+ PRT_ENTRY(0x0015FFFF, 1, GSI2),
+ PRT_ENTRY(0x0015FFFF, 2, GSI3),
+ PRT_ENTRY(0x0015FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0016FFFF, 0, GSI2),
+ PRT_ENTRY(0x0016FFFF, 1, GSI3),
+ PRT_ENTRY(0x0016FFFF, 2, GSI0),
+ PRT_ENTRY(0x0016FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0017FFFF, 0, GSI3),
+ PRT_ENTRY(0x0017FFFF, 1, GSI0),
+ PRT_ENTRY(0x0017FFFF, 2, GSI1),
+ PRT_ENTRY(0x0017FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0018FFFF, 0, GSI0),
+ PRT_ENTRY(0x0018FFFF, 1, GSI1),
+ PRT_ENTRY(0x0018FFFF, 2, GSI2),
+ PRT_ENTRY(0x0018FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0019FFFF, 0, GSI1),
+ PRT_ENTRY(0x0019FFFF, 1, GSI2),
+ PRT_ENTRY(0x0019FFFF, 2, GSI3),
+ PRT_ENTRY(0x0019FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x001AFFFF, 0, GSI2),
+ PRT_ENTRY(0x001AFFFF, 1, GSI3),
+ PRT_ENTRY(0x001AFFFF, 2, GSI0),
+ PRT_ENTRY(0x001AFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x001BFFFF, 0, GSI3),
+ PRT_ENTRY(0x001BFFFF, 1, GSI0),
+ PRT_ENTRY(0x001BFFFF, 2, GSI1),
+ PRT_ENTRY(0x001BFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x001CFFFF, 0, GSI0),
+ PRT_ENTRY(0x001CFFFF, 1, GSI1),
+ PRT_ENTRY(0x001CFFFF, 2, GSI2),
+ PRT_ENTRY(0x001CFFFF, 3, GSI3),
+
+ PRT_ENTRY(0x001DFFFF, 0, GSI1),
+ PRT_ENTRY(0x001DFFFF, 1, GSI2),
+ PRT_ENTRY(0x001DFFFF, 2, GSI3),
+ PRT_ENTRY(0x001DFFFF, 3, GSI0),
+
+ PRT_ENTRY(0x001EFFFF, 0, GSI2),
+ PRT_ENTRY(0x001EFFFF, 1, GSI3),
+ PRT_ENTRY(0x001EFFFF, 2, GSI0),
+ PRT_ENTRY(0x001EFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x001FFFFF, 0, GSI3),
+ PRT_ENTRY(0x001FFFFF, 1, GSI0),
+ PRT_ENTRY(0x001FFFFF, 2, GSI1),
+ PRT_ENTRY(0x001FFFFF, 3, GSI2),
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x80000000, // Min Base Address
+ 0xEFFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0x70000000 // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x100000000, // Min Base Address
+ 0xFFFFFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0xFF00000000 // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Min Base Address
+ 0x0000ffff, // Max Base Address
+ 0x7fff0000, // Translate
+ 0x00010000, // Length
+ ,,,TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x00000000F0000000, // Range Minimum
+ 0x00000000FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000010000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ }
+
+ // OS Control Handoff
+ Name (SUPP, Zero) // PCI _OSC Support Field value
+ Name (CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ * See [1] 6.2.10, [2] 4.5
+ */
+ Method (_OSC,4) {
+ // Check for proper UUID
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField (Arg3,0,CDW1)
+ CreateDWordField (Arg3,4,CDW2)
+ CreateDWordField (Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store (CDW2,SUPP)
+ Store (CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If (LNotEqual(And(SUPP, 0x16), 0x16)) {
+ And (CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ And (CTRL,0x1D,CTRL)
+
+ If (LNotEqual(Arg1,One)) { // Unknown revision
+ Or (CDW1,0x08,CDW1)
+ }
+
+ If (LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or (CDW1,0x10,CDW1)
+ }
+
+ // Update DWORD3 in the buffer
+ Store (CTRL,CDW3)
+ Return (Arg3)
+ } Else {
+ Or (CDW1,4,CDW1) // Unrecognized UUID
+ Return (Arg3)
+ }
+ } // End _OSC
+ }
} // Scope (_SB)
}
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
new file mode 100644
index 000000000000..e78061f9fe1c
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
@@ -0,0 +1,43 @@
+/** @file
+* ACPI Memory mapped configuration space base address Description Table (MCFG).
+*
+* Copyright (c) 2020, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+
+#pragma pack(push, 1)
+
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
+ {
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD
+ },
+ {
+ {
+ SBSAQEMU_PCI_SEG0_CONFIG_BASE,
+ 0,
+ SBSAQEMU_PCI_SEG0_BUSNUM_MIN,
+ SBSAQEMU_PCI_SEG0_BUSNUM_MAX,
+ EFI_ACPI_RESERVED_DWORD
+ }
+ }
+};
+
+#pragma pack(pop)
+
+// Reference the table being generated to prevent the optimizer
+// from removing the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Mcfg;
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table
2020-08-19 14:30 ` [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Tanmay Jagdale
@ 2020-08-20 11:40 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2020-08-20 11:40 UTC (permalink / raw)
To: Tanmay Jagdale
Cc: graeme, shashi.mallela, devel, paul.isaacs, tanmay,
Graeme Gregory
On Wed, Aug 19, 2020 at 20:00:00 +0530, Tanmay Jagdale wrote:
> Add PCI related entries to DSDT table along with the routing
> entries. Also add the MCFG table.
>
> Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
> Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 316 ++++++++++++++++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 +++
> 3 files changed, 360 insertions(+)
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
>
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> index ee524895524e..0b5017ce81c5 100644
> --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> @@ -20,6 +20,7 @@ [Sources]
> Fadt.aslc
> Gtdt.aslc
> Spcr.aslc
> + Mcfg.aslc
Please insert alphabetically sorted.
>
> [Packages]
> ArmPlatformPkg/ArmPlatformPkg.dec
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> index 85339d4559d3..2d3d4a2ddedc 100644
> --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> @@ -8,6 +8,23 @@
>
> #include <IndustryStandard/SbsaQemuAcpi.h>
>
> +#define LINK_DEVICE(Uid, LinkName, Irq) \
> + Device (LinkName) { \
> + Name (_HID, EISAID("PNP0C0F")) \
> + Name (_UID, Uid) \
> + Name (_PRS, ResourceTemplate() { \
> + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \
> + }) \
> + Method (_CRS, 0) { Return (_PRS) } \
> + Method (_SRS, 1) { } \
> + Method (_DIS) { } \
> + }
> +
> +#define PRT_ENTRY(Address, Pin, Link) \
> + Package (4) { \
> + Address, Pin, Link, Zero \
> + }
> +
> DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
> FixedPcdGet32 (PcdAcpiDefaultOemRevision)) {
> Scope (_SB) {
> @@ -129,5 +146,304 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
> } // USB0_RHUB
> } // USB0
>
> + Device (PCI0)
> + {
> + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
> + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
> + Name (_SEG, Zero) // PCI Segment Group number
> + Name (_BBN, Zero) // PCI Base Bus Number
> + Name (_ADR, Zero)
> + Name (_UID, "PCI0")
> + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1)
> +
> + Method (_CBA, 0, NotSerialized) {
> + return (0xf0000000)
> + }
> +
> + LINK_DEVICE(0, GSI0, 0x23)
> + LINK_DEVICE(1, GSI1, 0x24)
> + LINK_DEVICE(2, GSI2, 0x25)
> + LINK_DEVICE(3, GSI3, 0x26)
> +
> + Name (_PRT, Package () // _PRT: PCI Routing Table
> + {
> + PRT_ENTRY(0x0000FFFF, 0, GSI0),
> + PRT_ENTRY(0x0000FFFF, 0, GSI1),
> + PRT_ENTRY(0x0000FFFF, 0, GSI2),
> + PRT_ENTRY(0x0000FFFF, 0, GSI3),
> +
> + PRT_ENTRY(0x0001FFFF, 0, GSI1),
> + PRT_ENTRY(0x0001FFFF, 1, GSI2),
> + PRT_ENTRY(0x0001FFFF, 2, GSI3),
> + PRT_ENTRY(0x0001FFFF, 3, GSI0),
> +
> + PRT_ENTRY(0x0002FFFF, 0, GSI2),
> + PRT_ENTRY(0x0002FFFF, 1, GSI3),
> + PRT_ENTRY(0x0002FFFF, 2, GSI0),
> + PRT_ENTRY(0x0002FFFF, 3, GSI1),
> +
> + PRT_ENTRY(0x0003FFFF, 0, GSI3),
> + PRT_ENTRY(0x0003FFFF, 1, GSI0),
> + PRT_ENTRY(0x0003FFFF, 2, GSI1),
> + PRT_ENTRY(0x0003FFFF, 3, GSI2),
> +
> + PRT_ENTRY(0x0004FFFF, 0, GSI0),
> + PRT_ENTRY(0x0004FFFF, 1, GSI1),
> + PRT_ENTRY(0x0004FFFF, 2, GSI2),
> + PRT_ENTRY(0x0004FFFF, 3, GSI3),
> +
> + PRT_ENTRY(0x0005FFFF, 0, GSI1),
> + PRT_ENTRY(0x0005FFFF, 1, GSI2),
> + PRT_ENTRY(0x0005FFFF, 2, GSI3),
> + PRT_ENTRY(0x0005FFFF, 3, GSI0),
> +
> + PRT_ENTRY(0x0006FFFF, 0, GSI2),
> + PRT_ENTRY(0x0006FFFF, 1, GSI3),
> + PRT_ENTRY(0x0006FFFF, 2, GSI0),
> + PRT_ENTRY(0x0006FFFF, 3, GSI1),
> +
> + PRT_ENTRY(0x0007FFFF, 0, GSI3),
> + PRT_ENTRY(0x0007FFFF, 1, GSI0),
> + PRT_ENTRY(0x0007FFFF, 2, GSI1),
> + PRT_ENTRY(0x0007FFFF, 3, GSI2),
> +
> + PRT_ENTRY(0x0008FFFF, 0, GSI0),
> + PRT_ENTRY(0x0008FFFF, 1, GSI1),
> + PRT_ENTRY(0x0008FFFF, 2, GSI2),
> + PRT_ENTRY(0x0008FFFF, 3, GSI3),
> +
> + PRT_ENTRY(0x0009FFFF, 0, GSI1),
> + PRT_ENTRY(0x0009FFFF, 1, GSI2),
> + PRT_ENTRY(0x0009FFFF, 2, GSI3),
> + PRT_ENTRY(0x0009FFFF, 3, GSI0),
> +
> + PRT_ENTRY(0x000AFFFF, 0, GSI2),
> + PRT_ENTRY(0x000AFFFF, 1, GSI3),
> + PRT_ENTRY(0x000AFFFF, 2, GSI0),
> + PRT_ENTRY(0x000AFFFF, 3, GSI1),
> +
> + PRT_ENTRY(0x000BFFFF, 0, GSI3),
> + PRT_ENTRY(0x000BFFFF, 1, GSI0),
> + PRT_ENTRY(0x000BFFFF, 2, GSI1),
> + PRT_ENTRY(0x000BFFFF, 3, GSI2),
> +
> + PRT_ENTRY(0x000CFFFF, 0, GSI0),
> + PRT_ENTRY(0x000CFFFF, 1, GSI1),
> + PRT_ENTRY(0x000CFFFF, 2, GSI2),
> + PRT_ENTRY(0x000CFFFF, 3, GSI3),
> +
> + PRT_ENTRY(0x000DFFFF, 0, GSI1),
> + PRT_ENTRY(0x000DFFFF, 1, GSI2),
> + PRT_ENTRY(0x000DFFFF, 2, GSI3),
> + PRT_ENTRY(0x000DFFFF, 3, GSI0),
> +
> + PRT_ENTRY(0x000EFFFF, 0, GSI2),
> + PRT_ENTRY(0x000EFFFF, 1, GSI3),
> + PRT_ENTRY(0x000EFFFF, 2, GSI0),
> + PRT_ENTRY(0x000EFFFF, 3, GSI1),
> +
> + PRT_ENTRY(0x000FFFFF, 0, GSI3),
> + PRT_ENTRY(0x000FFFFF, 1, GSI0),
> + PRT_ENTRY(0x000FFFFF, 2, GSI1),
> + PRT_ENTRY(0x000FFFFF, 3, GSI2),
> +
> + PRT_ENTRY(0x0010FFFF, 0, GSI0),
> + PRT_ENTRY(0x0010FFFF, 1, GSI1),
> + PRT_ENTRY(0x0010FFFF, 2, GSI2),
> + PRT_ENTRY(0x0010FFFF, 3, GSI3),
> +
> + PRT_ENTRY(0x0011FFFF, 0, GSI1),
> + PRT_ENTRY(0x0011FFFF, 1, GSI2),
> + PRT_ENTRY(0x0011FFFF, 2, GSI3),
> + PRT_ENTRY(0x0011FFFF, 3, GSI0),
> +
> + PRT_ENTRY(0x0012FFFF, 0, GSI2),
> + PRT_ENTRY(0x0012FFFF, 1, GSI3),
> + PRT_ENTRY(0x0012FFFF, 2, GSI0),
> + PRT_ENTRY(0x0012FFFF, 3, GSI1),
> +
> + PRT_ENTRY(0x0013FFFF, 0, GSI3),
> + PRT_ENTRY(0x0013FFFF, 1, GSI0),
> + PRT_ENTRY(0x0013FFFF, 2, GSI1),
> + PRT_ENTRY(0x0013FFFF, 3, GSI2),
> +
> + PRT_ENTRY(0x0014FFFF, 0, GSI0),
> + PRT_ENTRY(0x0014FFFF, 1, GSI1),
> + PRT_ENTRY(0x0014FFFF, 2, GSI2),
> + PRT_ENTRY(0x0014FFFF, 3, GSI3),
> +
> + PRT_ENTRY(0x0015FFFF, 0, GSI1),
> + PRT_ENTRY(0x0015FFFF, 1, GSI2),
> + PRT_ENTRY(0x0015FFFF, 2, GSI3),
> + PRT_ENTRY(0x0015FFFF, 3, GSI0),
> +
> + PRT_ENTRY(0x0016FFFF, 0, GSI2),
> + PRT_ENTRY(0x0016FFFF, 1, GSI3),
> + PRT_ENTRY(0x0016FFFF, 2, GSI0),
> + PRT_ENTRY(0x0016FFFF, 3, GSI1),
> +
> + PRT_ENTRY(0x0017FFFF, 0, GSI3),
> + PRT_ENTRY(0x0017FFFF, 1, GSI0),
> + PRT_ENTRY(0x0017FFFF, 2, GSI1),
> + PRT_ENTRY(0x0017FFFF, 3, GSI2),
> +
> + PRT_ENTRY(0x0018FFFF, 0, GSI0),
> + PRT_ENTRY(0x0018FFFF, 1, GSI1),
> + PRT_ENTRY(0x0018FFFF, 2, GSI2),
> + PRT_ENTRY(0x0018FFFF, 3, GSI3),
> +
> + PRT_ENTRY(0x0019FFFF, 0, GSI1),
> + PRT_ENTRY(0x0019FFFF, 1, GSI2),
> + PRT_ENTRY(0x0019FFFF, 2, GSI3),
> + PRT_ENTRY(0x0019FFFF, 3, GSI0),
> +
> + PRT_ENTRY(0x001AFFFF, 0, GSI2),
> + PRT_ENTRY(0x001AFFFF, 1, GSI3),
> + PRT_ENTRY(0x001AFFFF, 2, GSI0),
> + PRT_ENTRY(0x001AFFFF, 3, GSI1),
> +
> + PRT_ENTRY(0x001BFFFF, 0, GSI3),
> + PRT_ENTRY(0x001BFFFF, 1, GSI0),
> + PRT_ENTRY(0x001BFFFF, 2, GSI1),
> + PRT_ENTRY(0x001BFFFF, 3, GSI2),
> +
> + PRT_ENTRY(0x001CFFFF, 0, GSI0),
> + PRT_ENTRY(0x001CFFFF, 1, GSI1),
> + PRT_ENTRY(0x001CFFFF, 2, GSI2),
> + PRT_ENTRY(0x001CFFFF, 3, GSI3),
> +
> + PRT_ENTRY(0x001DFFFF, 0, GSI1),
> + PRT_ENTRY(0x001DFFFF, 1, GSI2),
> + PRT_ENTRY(0x001DFFFF, 2, GSI3),
> + PRT_ENTRY(0x001DFFFF, 3, GSI0),
> +
> + PRT_ENTRY(0x001EFFFF, 0, GSI2),
> + PRT_ENTRY(0x001EFFFF, 1, GSI3),
> + PRT_ENTRY(0x001EFFFF, 2, GSI0),
> + PRT_ENTRY(0x001EFFFF, 3, GSI1),
> +
> + PRT_ENTRY(0x001FFFFF, 0, GSI3),
> + PRT_ENTRY(0x001FFFFF, 1, GSI0),
> + PRT_ENTRY(0x001FFFFF, 2, GSI1),
> + PRT_ENTRY(0x001FFFFF, 3, GSI2),
> + })
> +
> + // Root complex resources
> + Method (_CRS, 0, Serialized) {
> + Name (RBUF, ResourceTemplate () {
> + WordBusNumber ( // Bus numbers assigned to this root
> + ResourceProducer,
> + MinFixed, MaxFixed, PosDecode,
> + 0, // AddressGranularity
> + 0, // AddressMinimum - Minimum Bus Number
> + 255, // AddressMaximum - Maximum Bus Number
> + 0, // AddressTranslation - Set to 0
> + 256 // RangeLength - Number of Busses
> + )
> +
> + DWordMemory ( // 32-bit BAR Windows
> + ResourceProducer, PosDecode,
> + MinFixed, MaxFixed,
> + Cacheable, ReadWrite,
> + 0x00000000, // Granularity
> + 0x80000000, // Min Base Address
> + 0xEFFFFFFF, // Max Base Address
> + 0x00000000, // Translate
> + 0x70000000 // Length
> + )
> +
> + QWordMemory ( // 64-bit BAR Windows
> + ResourceProducer, PosDecode,
> + MinFixed, MaxFixed,
> + Cacheable, ReadWrite,
> + 0x00000000, // Granularity
> + 0x100000000, // Min Base Address
> + 0xFFFFFFFFFF, // Max Base Address
> + 0x00000000, // Translate
> + 0xFF00000000 // Length
Plese clean up horizontal alignment of comments.
/
Leif
> + )
> +
> + DWordIo ( // IO window
> + ResourceProducer,
> + MinFixed,
> + MaxFixed,
> + PosDecode,
> + EntireRange,
> + 0x00000000, // Granularity
> + 0x00000000, // Min Base Address
> + 0x0000ffff, // Max Base Address
> + 0x7fff0000, // Translate
> + 0x00010000, // Length
> + ,,,TypeTranslation
> + )
> + }) // Name(RBUF)
> +
> + Return (RBUF)
> + } // Method(_CRS)
> +
> + Device (RES0)
> + {
> + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
> + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
> + {
> + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
> + 0x0000000000000000, // Granularity
> + 0x00000000F0000000, // Range Minimum
> + 0x00000000FFFFFFFF, // Range Maximum
> + 0x0000000000000000, // Translation Offset
> + 0x0000000010000000, // Length
> + ,, , AddressRangeMemory, TypeStatic)
> + })
> + }
> +
> + // OS Control Handoff
> + Name (SUPP, Zero) // PCI _OSC Support Field value
> + Name (CTRL, Zero) // PCI _OSC Control Field value
> +
> + /*
> + * See [1] 6.2.10, [2] 4.5
> + */
> + Method (_OSC,4) {
> + // Check for proper UUID
> + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + // Create DWord-adressable fields from the Capabilities Buffer
> + CreateDWordField (Arg3,0,CDW1)
> + CreateDWordField (Arg3,4,CDW2)
> + CreateDWordField (Arg3,8,CDW3)
> +
> + // Save Capabilities DWord2 & 3
> + Store (CDW2,SUPP)
> + Store (CDW3,CTRL)
> +
> + // Only allow native hot plug control if OS supports:
> + // * ASPM
> + // * Clock PM
> + // * MSI/MSI-X
> + If (LNotEqual(And(SUPP, 0x16), 0x16)) {
> + And (CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
> + }
> +
> + // Always allow native PME, AER (no dependencies)
> +
> + // Never allow SHPC (no SHPC controller in this system)
> + And (CTRL,0x1D,CTRL)
> +
> + If (LNotEqual(Arg1,One)) { // Unknown revision
> + Or (CDW1,0x08,CDW1)
> + }
> +
> + If (LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
> + Or (CDW1,0x10,CDW1)
> + }
> +
> + // Update DWORD3 in the buffer
> + Store (CTRL,CDW3)
> + Return (Arg3)
> + } Else {
> + Or (CDW1,4,CDW1) // Unrecognized UUID
> + Return (Arg3)
> + }
> + } // End _OSC
> + }
> } // Scope (_SB)
> }
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
> new file mode 100644
> index 000000000000..e78061f9fe1c
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
> @@ -0,0 +1,43 @@
> +/** @file
> +* ACPI Memory mapped configuration space base address Description Table (MCFG).
> +*
> +* Copyright (c) 2020, Linaro Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <IndustryStandard/Acpi61.h>
> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
> +#include <IndustryStandard/SbsaQemuAcpi.h>
> +
> +#pragma pack(push, 1)
> +
> +typedef struct {
> + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
> + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];
> +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
> +
> +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
> + {
> + SBSAQEMU_ACPI_HEADER (
> + EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
> + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
> + EFI_ACPI_RESERVED_QWORD
> + },
> + {
> + {
> + SBSAQEMU_PCI_SEG0_CONFIG_BASE,
> + 0,
> + SBSAQEMU_PCI_SEG0_BUSNUM_MIN,
> + SBSAQEMU_PCI_SEG0_BUSNUM_MAX,
> + EFI_ACPI_RESERVED_DWORD
> + }
> + }
> +};
> +
> +#pragma pack(pop)
> +
> +// Reference the table being generated to prevent the optimizer
> +// from removing the data structure from the executable
> +VOID* CONST ReferenceAcpiTable = &Mcfg;
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH edk2-platforms 3/7] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
2020-08-19 14:29 ` [PATCH edk2-platforms 1/7] SbsaQemu: Initial support for static ACPI tables Tanmay Jagdale
2020-08-19 14:30 ` [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Tanmay Jagdale
@ 2020-08-19 14:30 ` Tanmay Jagdale
2020-08-20 11:46 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 4/7] SbsaQemu: AcpiDxe: Create MADT table at runtime Tanmay Jagdale
` (4 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Tanmay Jagdale @ 2020-08-19 14:30 UTC (permalink / raw)
To: leif, graeme, shashi.mallela, devel; +Cc: paul.isaacs, tanmay, Tanmay Jagdale
- Add a new ACPI driver for the SbsaQemu platform which would
handle any modifications needed for the ACPI tables.
- Move FdtLib from LibraryClasses.common.PEIM to LibraryClasses.common
so that SbsaQemuAcpiDxe driver can use the device tree APIs
- Since the core count is controlled by Qemu, move the PcdCoreCount
from PcdsFixedAtBuild to PcdsDynamic.
- Add a parser function in this driver which parses the FDT created
by Qemu to determine the number of CPUs and hence update the
PcdCoreCount variable.
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +-
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 1 +
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 76 +++++++++++++++++++
.../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 49 ++++++++++++
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 +
6 files changed, 135 insertions(+), 2 deletions(-)
create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 4739443cae93..d42b9cd4de49 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -75,6 +75,7 @@ [LibraryClasses.common]
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
@@ -217,7 +218,6 @@ [LibraryClasses.common.PEIM]
PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
- FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
ArmPlatformLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf
[LibraryClasses.common.DXE_CORE]
@@ -376,7 +376,6 @@ [PcdsFixedAtBuild.common]
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
- gArmPlatformTokenSpaceGuid.PcdCoreCount|1
gArmTokenSpaceGuid.PcdVFPEnabled|1
# System Memory Base -- fixed
@@ -477,6 +476,9 @@ [PcdsFixedAtBuild.common]
[PcdsDynamicDefault.common]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+ # Core and Cluster Count
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|1
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|1
# System Memory Size -- 128 MB initially, actual size will be fetched from DT
# TODO as no DT will be used we should pass this by some other method
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
index 4526eaaa02c5..3bcf0bf0040a 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
@@ -232,6 +232,7 @@ [FV.FvMain]
#
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
index c4a8d7a27b78..593670383750 100644
--- a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
+++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
@@ -33,3 +33,4 @@ [Components.common]
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
new file mode 100644
index 000000000000..09e5ba432a59
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -0,0 +1,76 @@
+/** @file
+* This file is an ACPI driver for the Qemu SBSA platform.
+*
+* Copyright (c) 2020, Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <Protocol/FdtClient.h>
+#include <libfdt.h>
+
+/*
+ * A function that walks through the Device Tree created
+ * by Qemu and counts the number of CPUs present in it.
+ */
+STATIC
+VOID
+CountCpusFromFdt (
+ VOID
+)
+{
+ VOID *DeviceTreeBase;
+ INT32 Node, Prev;
+ RETURN_STATUS PcdStatus;
+ INT32 CpuNode;
+ INT32 CpuCount;
+
+ DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress);
+ ASSERT (DeviceTreeBase != NULL);
+
+ // Make sure we have a valid device tree blob
+ ASSERT (fdt_check_header (DeviceTreeBase) == 0);
+
+ CpuNode = fdt_path_offset (DeviceTreeBase, "/cpus");
+ if (CpuNode <= 0) {
+ DEBUG((EFI_D_ERROR, "Unable to locate /cpus in device tree\n"));
+ return;
+ }
+
+ CpuCount = 0;
+
+ // Walk through /cpus node and count the number of subnodes.
+ // The count of these subnodes corresponds to the numer of
+ // CPUs created by Qemu.
+ Prev = fdt_first_subnode (DeviceTreeBase, CpuNode);
+ while (1) {
+ CpuCount++;
+ Node = fdt_next_subnode (DeviceTreeBase, Prev);
+ if (Node < 0) {
+ break;
+ }
+ Prev = Node;
+ }
+ ASSERT (CpuCount > 0);
+
+ PcdStatus = PcdSet32S (PcdCoreCount, CpuCount);
+ ASSERT_RETURN_ERROR (PcdStatus);
+}
+
+EFI_STATUS
+EFIAPI
+InitializeSbsaQemuAcpiDxe (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ // Parse the device tree and get the number of CPUs
+ CountCpusFromFdt ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
new file mode 100644
index 000000000000..efc4d295bfb7
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -0,0 +1,49 @@
+## @file
+# This driver modifies ACPI tables for the Qemu SBSA platform
+#
+# Copyright (c) 2020, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001d
+ BASE_NAME = SbsaQemuAcpiDxe
+ FILE_GUID = 6c592dc9-76c8-474f-93b2-bf1e8f15ae35
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeSbsaQemuAcpiDxe
+
+[Sources]
+ SbsaQemuAcpiDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmVirtPkg/ArmVirtPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ DebugLib
+ BaseLib
+ FdtLib
+ DxeServicesLib
+ PcdLib
+ UefiDriverEntryPoint
+ UefiLib
+ UefiRuntimeServicesTableLib
+
+[Pcd]
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
+
+[Depex]
+ TRUE
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index 71ba55a082e2..ed87d15de003 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -35,3 +35,7 @@ [PcdsFixedAtBuild.common]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x00000003
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT32|0x00000004
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000|UINT64|0x00000005
+
+[PcdsDynamic.common]
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000006
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x00000007
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH edk2-platforms 3/7] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs
2020-08-19 14:30 ` [PATCH edk2-platforms 3/7] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs Tanmay Jagdale
@ 2020-08-20 11:46 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2020-08-20 11:46 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: graeme, shashi.mallela, devel, paul.isaacs, tanmay
On Wed, Aug 19, 2020 at 20:00:01 +0530, Tanmay Jagdale wrote:
> - Add a new ACPI driver for the SbsaQemu platform which would
> handle any modifications needed for the ACPI tables.
>
> - Move FdtLib from LibraryClasses.common.PEIM to LibraryClasses.common
> so that SbsaQemuAcpiDxe driver can use the device tree APIs
>
> - Since the core count is controlled by Qemu, move the PcdCoreCount
> from PcdsFixedAtBuild to PcdsDynamic.
>
> - Add a parser function in this driver which parses the FDT created
> by Qemu to determine the number of CPUs and hence update the
> PcdCoreCount variable.
>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +-
> Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
> Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 1 +
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 76 +++++++++++++++++++
> .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 49 ++++++++++++
> Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 +
> 6 files changed, 135 insertions(+), 2 deletions(-)
> create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
>
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> index 4739443cae93..d42b9cd4de49 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> @@ -75,6 +75,7 @@ [LibraryClasses.common]
Ah, yes, I see here you *have* set up the diff format (probably using
SetupGit.py), so the issue is simply an out-of-date edk2 tree.
Do try to keep edk2 as up to date as possible - if edk2 changes causes
breakage in the platform ports, I'm not going to take any new patches
until those have been fixed anyway.
> ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
>
> + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
Why are we adding FdtLib?
> UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
>
> @@ -217,7 +218,6 @@ [LibraryClasses.common.PEIM]
>
> PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
>
> - FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
Why are we removing FdtLib?
> ArmPlatformLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf
>
> [LibraryClasses.common.DXE_CORE]
> @@ -376,7 +376,6 @@ [PcdsFixedAtBuild.common]
> #
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
>
> - gArmPlatformTokenSpaceGuid.PcdCoreCount|1
Why are we removing PcdCoreCount?
> gArmTokenSpaceGuid.PcdVFPEnabled|1
>
> # System Memory Base -- fixed
> @@ -477,6 +476,9 @@ [PcdsFixedAtBuild.common]
> [PcdsDynamicDefault.common]
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
>
> + # Core and Cluster Count
> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|1
Why are we adding PcdCoreCount?
(In short - stop moving things around randomly. If you want to
reorganise a file that's fine, but that should be a separate commit
without functional changes.)
> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|1
>
> # System Memory Size -- 128 MB initially, actual size will be fetched from DT
> # TODO as no DT will be used we should pass this by some other method
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> index 4526eaaa02c5..3bcf0bf0040a 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> @@ -232,6 +232,7 @@ [FV.FvMain]
> #
> INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> + INF Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
>
> diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> index c4a8d7a27b78..593670383750 100644
> --- a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> @@ -33,3 +33,4 @@ [Components.common]
> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> new file mode 100644
> index 000000000000..09e5ba432a59
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -0,0 +1,76 @@
> +/** @file
> +* This file is an ACPI driver for the Qemu SBSA platform.
> +*
> +* Copyright (c) 2020, Linaro Ltd. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/FdtClient.h>
> +#include <libfdt.h>
> +
> +/*
> + * A function that walks through the Device Tree created
> + * by Qemu and counts the number of CPUs present in it.
> + */
> +STATIC
> +VOID
> +CountCpusFromFdt (
> + VOID
> +)
> +{
> + VOID *DeviceTreeBase;
> + INT32 Node, Prev;
> + RETURN_STATUS PcdStatus;
> + INT32 CpuNode;
> + INT32 CpuCount;
> +
> + DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress);
> + ASSERT (DeviceTreeBase != NULL);
> +
> + // Make sure we have a valid device tree blob
> + ASSERT (fdt_check_header (DeviceTreeBase) == 0);
> +
> + CpuNode = fdt_path_offset (DeviceTreeBase, "/cpus");
> + if (CpuNode <= 0) {
> + DEBUG((EFI_D_ERROR, "Unable to locate /cpus in device tree\n"));
> + return;
> + }
> +
> + CpuCount = 0;
> +
> + // Walk through /cpus node and count the number of subnodes.
> + // The count of these subnodes corresponds to the numer of
> + // CPUs created by Qemu.
> + Prev = fdt_first_subnode (DeviceTreeBase, CpuNode);
> + while (1) {
> + CpuCount++;
> + Node = fdt_next_subnode (DeviceTreeBase, Prev);
> + if (Node < 0) {
> + break;
> + }
> + Prev = Node;
> + }
> + ASSERT (CpuCount > 0);
> +
> + PcdStatus = PcdSet32S (PcdCoreCount, CpuCount);
> + ASSERT_RETURN_ERROR (PcdStatus);
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +InitializeSbsaQemuAcpiDxe (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + // Parse the device tree and get the number of CPUs
> + CountCpusFromFdt ();
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> new file mode 100644
> index 000000000000..efc4d295bfb7
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> @@ -0,0 +1,49 @@
> +## @file
> +# This driver modifies ACPI tables for the Qemu SBSA platform
> +#
> +# Copyright (c) 2020, Linaro Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001d
> + BASE_NAME = SbsaQemuAcpiDxe
> + FILE_GUID = 6c592dc9-76c8-474f-93b2-bf1e8f15ae35
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> +
> + ENTRY_POINT = InitializeSbsaQemuAcpiDxe
> +
> +[Sources]
> + SbsaQemuAcpiDxe.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + ArmVirtPkg/ArmVirtPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> +
> +[LibraryClasses]
> + ArmLib
> + BaseMemoryLib
> + DebugLib
> + BaseLib
> + FdtLib
> + DxeServicesLib
Please sort Above LibraryClasses alphabetically.
/
Leif
> + PcdLib
> + UefiDriverEntryPoint
> + UefiLib
> + UefiRuntimeServicesTableLib
> +
> +[Pcd]
> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
> +
> +[Depex]
> + TRUE
> diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> index 71ba55a082e2..ed87d15de003 100644
> --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> @@ -35,3 +35,7 @@ [PcdsFixedAtBuild.common]
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x00000003
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT32|0x00000004
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000|UINT64|0x00000005
> +
> +[PcdsDynamic.common]
> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000006
> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x00000007
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH edk2-platforms 4/7] SbsaQemu: AcpiDxe: Create MADT table at runtime
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (2 preceding siblings ...)
2020-08-19 14:30 ` [PATCH edk2-platforms 3/7] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs Tanmay Jagdale
@ 2020-08-19 14:30 ` Tanmay Jagdale
2020-08-20 12:02 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 5/7] SbsaQemu: AcpiDxe: Create SSDT " Tanmay Jagdale
` (3 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Tanmay Jagdale @ 2020-08-19 14:30 UTC (permalink / raw)
To: leif, graeme, shashi.mallela, devel; +Cc: paul.isaacs, tanmay, Tanmay Jagdale
- Add support to create MADT table at runtime.
- Included a macro for GIC Redistributor structure initialisation.
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 159 ++++++++++++++++++
.../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++-
.../Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++
3 files changed, 193 insertions(+), 1 deletion(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 09e5ba432a59..569cda8b6474 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -6,11 +6,19 @@
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/Acpi10.h>
+#include <IndustryStandard/Acpi60.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiLib.h>
+#include <Protocol/AcpiTable.h>
#include <Protocol/FdtClient.h>
#include <libfdt.h>
@@ -62,6 +70,138 @@ CountCpusFromFdt (
ASSERT_RETURN_ERROR (PcdStatus);
}
+/*
+ * A Function to Compute the ACPI Table Checksum
+ */
+VOID
+AcpiPlatformChecksum (
+ IN UINT8 *Buffer,
+ IN UINTN Size
+ )
+{
+ UINTN ChecksumOffset;
+
+ ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
+
+ // Set checksum to 0 first
+ Buffer[ChecksumOffset] = 0;
+
+ // Update checksum value
+ Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
+}
+
+/*
+ * A function that add the MADT ACPI table.
+ IN EFI_ACPI_COMMON_HEADER *CurrentTable
+ */
+EFI_STATUS
+AddMadtTable (
+ IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN TableHandle;
+ UINT32 TableSize;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINT8 *New;
+ UINT32 NumCores;
+
+ // Initialize MADT ACPI Header
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = {
+ SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+ 0, 0 };
+
+ // Initialize GICC Structure
+ EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT (
+ 0, /* GicID */
+ 0, /* AcpiCpuUid */
+ 0, /* Mpidr */
+ EFI_ACPI_6_0_GIC_ENABLED, /* Flags */
+ SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */
+ FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */
+ SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */
+ SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */
+ 25, /* GsivId */
+ 0, /* GicRBase */
+ 0 /* Efficiency */
+ );
+
+ // Initialize GIC Distributor Structure
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (
+ 0,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0,
+ 3 /* GicVersion */
+ );
+
+ // Initialize GIC Redistributor Structure
+ EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
+
+ // Get CoreCount which was determined eariler after parsing device tree
+ NumCores = PcdGet32 (PcdCoreCount);
+
+ // Calculate the new table size based on the number of cores
+ TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
+ (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
+ sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
+ sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
+
+ Status = gBS->AllocatePages (
+ AllocateAnyPages,
+ EfiACPIReclaimMemory,
+ EFI_SIZE_TO_PAGES (TableSize),
+ &PageAddress
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Failed to allocate pages for MADT table\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ New = (UINT8 *)(UINTN) PageAddress;
+ ZeroMem (New, TableSize);
+
+ // Add the ACPI Description table header
+ CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
+ ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
+ New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
+
+ // Add new GICC structures for the Cores
+ for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) {
+ EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr;
+
+ CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
+ GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
+ GiccPtr->AcpiProcessorUid = NumCores;
+ GiccPtr->MPIDR = NumCores;
+ New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE);
+ }
+
+ // GIC Distributor Structure
+ CopyMem (New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE));
+ New += sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE);
+
+ // GIC ReDistributor Structure
+ CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE));
+ New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
+
+ AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ (EFI_ACPI_COMMON_HEADER *)PageAddress,
+ TableSize,
+ &TableHandle
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Failed to install MADT table\n"));
+ }
+
+ return Status;
+}
+
EFI_STATUS
EFIAPI
InitializeSbsaQemuAcpiDxe (
@@ -69,8 +209,27 @@ InitializeSbsaQemuAcpiDxe (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
+ EFI_STATUS Status;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
// Parse the device tree and get the number of CPUs
CountCpusFromFdt ();
+ // Check if ACPI Table Protocol has been installed
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTable
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Failed to locate ACPI Table Protocol\n"));
+ return Status;
+ }
+
+ Status = AddMadtTable (AcpiTable);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Failed to add MADT table\n"));
+ }
+
return EFI_SUCCESS;
}
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index efc4d295bfb7..16bc1b0c8cb1 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -41,9 +41,27 @@ [LibraryClasses]
UefiRuntimeServicesTableLib
[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
[Depex]
- TRUE
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+
+[Guids]
+ gEdkiiPlatformHasAcpiGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index eac195b0585c..7a9a0061675f 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -22,6 +22,21 @@
FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \
}
+// Defines for MADT
+#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
+#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
+#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
+#define SBSAQEMU_MADT_GICR_SIZE 0x4000000
+
+// Macro for MADT GIC Redistributor Structure
+#define SBSAQEMU_MADT_GICR_INIT() { \
+ EFI_ACPI_6_0_GICR, /* Type */ \
+ sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ \
+ EFI_ACPI_RESERVED_WORD, /* Reserved */ \
+ FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress */ \
+ SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ \
+ }
+
#define SBSAQEMU_UART0_BASE 0x60000000
#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH edk2-platforms 4/7] SbsaQemu: AcpiDxe: Create MADT table at runtime
2020-08-19 14:30 ` [PATCH edk2-platforms 4/7] SbsaQemu: AcpiDxe: Create MADT table at runtime Tanmay Jagdale
@ 2020-08-20 12:02 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2020-08-20 12:02 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: graeme, shashi.mallela, devel, paul.isaacs, tanmay
On Wed, Aug 19, 2020 at 20:00:02 +0530, Tanmay Jagdale wrote:
> - Add support to create MADT table at runtime.
> - Included a macro for GIC Redistributor structure initialisation.
>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 159 ++++++++++++++++++
> .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++-
> .../Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++
> 3 files changed, 193 insertions(+), 1 deletion(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index 09e5ba432a59..569cda8b6474 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -6,11 +6,19 @@
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> **/
> +#include <IndustryStandard/Acpi.h>
> +#include <IndustryStandard/Acpi10.h>
> +#include <IndustryStandard/Acpi60.h>
Looking at Acpi.h, that contains the line
#include <IndustryStandard/Acpi63.h>
Looking at Acpi63.h, that contains the line
#include <IndustryStandard/Acpi62.h>
Looking at Acpi62.h, that contains the line
#include <IndustryStandard/Acpi61.h>
Looking at Acpi61.h, that contains the line
#include <IndustryStandard/Acpi60.h>
...
Looking at Acpi20.h, that contains the line
#include <IndustryStandard/Acpi10.h>
I.e. - there may be a point to including a specific versioned ACPI
header, to make it clear what minimum revision is required, but there
is no need to include multiple ACPI headers.
For SbsaQemu, I would prefer not tying us to a specific revision - we
will be tracking architectural evolution. So only including Acpi.h is
probably appropriate.
> +#include <IndustryStandard/SbsaQemuAcpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/BaseMemoryLib.h>
> #include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> #include <Library/PcdLib.h>
> #include <Library/UefiBootServicesTableLib.h>
> #include <Library/UefiDriverEntryPoint.h>
> #include <Library/UefiLib.h>
> +#include <Protocol/AcpiTable.h>
> #include <Protocol/FdtClient.h>
> #include <libfdt.h>
>
> @@ -62,6 +70,138 @@ CountCpusFromFdt (
> ASSERT_RETURN_ERROR (PcdStatus);
> }
>
> +/*
> + * A Function to Compute the ACPI Table Checksum
> + */
> +VOID
> +AcpiPlatformChecksum (
> + IN UINT8 *Buffer,
> + IN UINTN Size
> + )
> +{
> + UINTN ChecksumOffset;
> +
> + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
> +
> + // Set checksum to 0 first
This comment is completely pointless ... *unless* the checksum byte is
also included in the checksum calculation. And if that is the case,
*that* is what should be pointed out. Not the arithmetic operation
that can be clearly seen happening on the next line.
> + Buffer[ChecksumOffset] = 0;
> +
> + // Update checksum value
> + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
(Or, if the checksum byte can be relied on to be the last one in
Buffer, we can calculate the sum over Size - 1.)
Note to self: this is very clearly something that should go into a
generic helper library.
/
Leif
> +}
> +
> +/*
> + * A function that add the MADT ACPI table.
> + IN EFI_ACPI_COMMON_HEADER *CurrentTable
> + */
> +EFI_STATUS
> +AddMadtTable (
> + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> + )
> +{
> + EFI_STATUS Status;
> + UINTN TableHandle;
> + UINT32 TableSize;
> + EFI_PHYSICAL_ADDRESS PageAddress;
> + UINT8 *New;
> + UINT32 NumCores;
> +
> + // Initialize MADT ACPI Header
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = {
> + SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER,
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
> + 0, 0 };
> +
> + // Initialize GICC Structure
> + EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT (
> + 0, /* GicID */
> + 0, /* AcpiCpuUid */
> + 0, /* Mpidr */
> + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */
> + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */
> + FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */
> + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */
> + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */
> + 25, /* GsivId */
> + 0, /* GicRBase */
> + 0 /* Efficiency */
> + );
> +
> + // Initialize GIC Distributor Structure
> + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =
> + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (
> + 0,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0,
> + 3 /* GicVersion */
> + );
> +
> + // Initialize GIC Redistributor Structure
> + EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
> +
> + // Get CoreCount which was determined eariler after parsing device tree
> + NumCores = PcdGet32 (PcdCoreCount);
> +
> + // Calculate the new table size based on the number of cores
> + TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
> + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
> + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
> + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> +
> + Status = gBS->AllocatePages (
> + AllocateAnyPages,
> + EfiACPIReclaimMemory,
> + EFI_SIZE_TO_PAGES (TableSize),
> + &PageAddress
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG ((EFI_D_ERROR, "Failed to allocate pages for MADT table\n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + New = (UINT8 *)(UINTN) PageAddress;
> + ZeroMem (New, TableSize);
> +
> + // Add the ACPI Description table header
> + CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
> + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
> + New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
> +
> + // Add new GICC structures for the Cores
> + for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) {
> + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr;
> +
> + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
> + GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
> + GiccPtr->AcpiProcessorUid = NumCores;
> + GiccPtr->MPIDR = NumCores;
> + New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE);
> + }
> +
> + // GIC Distributor Structure
> + CopyMem (New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE));
> + New += sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE);
> +
> + // GIC ReDistributor Structure
> + CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE));
> + New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> +
> + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
> +
> + Status = AcpiTable->InstallAcpiTable (
> + AcpiTable,
> + (EFI_ACPI_COMMON_HEADER *)PageAddress,
> + TableSize,
> + &TableHandle
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG ((EFI_D_ERROR, "Failed to install MADT table\n"));
> + }
> +
> + return Status;
> +}
> +
> EFI_STATUS
> EFIAPI
> InitializeSbsaQemuAcpiDxe (
> @@ -69,8 +209,27 @@ InitializeSbsaQemuAcpiDxe (
> IN EFI_SYSTEM_TABLE *SystemTable
> )
> {
> + EFI_STATUS Status;
> + EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
> +
> // Parse the device tree and get the number of CPUs
> CountCpusFromFdt ();
>
> + // Check if ACPI Table Protocol has been installed
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiTableProtocolGuid,
> + NULL,
> + (VOID **)&AcpiTable
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((EFI_D_ERROR, "Failed to locate ACPI Table Protocol\n"));
> + return Status;
> + }
> +
> + Status = AddMadtTable (AcpiTable);
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "Failed to add MADT table\n"));
> + }
> +
> return EFI_SUCCESS;
> }
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> index efc4d295bfb7..16bc1b0c8cb1 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> @@ -41,9 +41,27 @@ [LibraryClasses]
> UefiRuntimeServicesTableLib
>
> [Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
>
> [Depex]
> - TRUE
> + gEfiAcpiTableProtocolGuid ## CONSUMES
> +
> +[Guids]
> + gEdkiiPlatformHasAcpiGuid
> +
> +[Protocols]
> + gEfiAcpiTableProtocolGuid ## CONSUMES
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> index eac195b0585c..7a9a0061675f 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -22,6 +22,21 @@
> FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \
> }
>
> +// Defines for MADT
> +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
> +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
> +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
> +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000
> +
> +// Macro for MADT GIC Redistributor Structure
> +#define SBSAQEMU_MADT_GICR_INIT() { \
> + EFI_ACPI_6_0_GICR, /* Type */ \
> + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ \
> + EFI_ACPI_RESERVED_WORD, /* Reserved */ \
> + FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress */ \
> + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ \
> + }
> +
> #define SBSAQEMU_UART0_BASE 0x60000000
>
> #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH edk2-platforms 5/7] SbsaQemu: AcpiDxe: Create SSDT table at runtime
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (3 preceding siblings ...)
2020-08-19 14:30 ` [PATCH edk2-platforms 4/7] SbsaQemu: AcpiDxe: Create MADT table at runtime Tanmay Jagdale
@ 2020-08-19 14:30 ` Tanmay Jagdale
2020-08-20 12:09 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT " Tanmay Jagdale
` (2 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Tanmay Jagdale @ 2020-08-19 14:30 UTC (permalink / raw)
To: leif, graeme, shashi.mallela, devel; +Cc: paul.isaacs, tanmay, Tanmay Jagdale
- Add support to create SSDT table at runtime. Since SSDT
table is a data table, added a few helper macros to create
the AML entries.
- Also added a function to calculate the length of Packages.
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 144 ++++++++++++++++++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 29 ++++
2 files changed, 173 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 569cda8b6474..d90ce0c2a718 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -9,6 +9,7 @@
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/Acpi10.h>
#include <IndustryStandard/Acpi60.h>
+#include <IndustryStandard/AcpiAml.h>
#include <IndustryStandard/SbsaQemuAcpi.h>
#include <Library/AcpiLib.h>
#include <Library/BaseMemoryLib.h>
@@ -202,6 +203,144 @@ AddMadtTable (
return Status;
}
+/*
+ * Function to calculate the PkgLength field in ACPI tables
+ */
+STATIC
+UINT32
+SetPkgLength (
+ IN UINT8 *TablePtr,
+ IN UINT32 Length
+)
+{
+ UINT8 ByteCount;
+ UINT8 *PkgLeadByte = TablePtr;
+
+ if (Length < 64) {
+ *TablePtr = Length;
+ return 1;
+ }
+
+ // Set the LSB of Length in PkgLeadByte and advance Length
+ *PkgLeadByte = Length & 0xF;
+ Length = Length >> 4;
+
+ while (Length) {
+ TablePtr++;
+ *TablePtr = (Length & 0xFF);
+ Length = (Length >> 8);
+ }
+
+ // Calculate the number of bytes the Length field uses
+ // and set the ByteCount field in PkgLeadByte.
+ ByteCount = (TablePtr - PkgLeadByte) & 0xF;
+ *PkgLeadByte |= (ByteCount << 6);
+
+ return ByteCount + 1;
+}
+
+/*
+ * A function that adds SSDT ACPI table.
+ */
+EFI_STATUS
+AddSsdtTable (
+ IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN TableHandle;
+ UINT32 TableSize;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINT8 *New;
+ UINT32 CpuId;
+ UINT32 Offset;
+ UINT8 ScopeOpName[] = SBSAQEMU_ACPI_SCOPE_NAME;
+ UINT32 NumCores = PcdGet32 (PcdCoreCount);
+
+ EFI_ACPI_DESCRIPTION_HEADER Header =
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_DESCRIPTION_HEADER,
+ EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION);
+
+ SBSAQEMU_ACPI_CPU_DEVICE CpuDevice = {
+ { AML_EXT_OP, AML_EXT_DEVICE_OP }, /* Device () */
+ SBSAQEMU_ACPI_CPU_DEV_LEN, /* Length */
+ SBSAQEMU_ACPI_CPU_DEV_NAME, /* Device Name "C000" */
+ SBSAQEMU_ACPI_CPU_HID, /* Name (HID, "ACPI0007") */
+ SBSAQEMU_ACPI_CPU_UID, /* Name (UID, 0) */
+ };
+
+ // Calculate the new table size based on the number of cores
+ TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
+ SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH + sizeof (ScopeOpName) +
+ (sizeof (CpuDevice) * NumCores);
+
+ Status = gBS->AllocatePages (
+ AllocateAnyPages,
+ EfiACPIReclaimMemory,
+ EFI_SIZE_TO_PAGES (TableSize),
+ &PageAddress
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Failed to allocate pages for SSDT table\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ New = (UINT8 *)(UINTN) PageAddress;
+ ZeroMem (New, TableSize);
+
+ // Add the ACPI Description table header
+ CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
+ ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
+ New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
+
+ // Insert the top level ScopeOp
+ *New = AML_SCOPE_OP;
+ New++;
+ Offset = SetPkgLength (New,
+ (TableSize - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - 1));
+ New += Offset;
+ CopyMem (New, &ScopeOpName, sizeof (ScopeOpName));
+ New += sizeof (ScopeOpName);
+
+ // Add new Device structures for the Cores
+ for (CpuId = 0; CpuId < NumCores; CpuId++) {
+ SBSAQEMU_ACPI_CPU_DEVICE *CpuDevicePtr;
+ UINT8 CpuIdByte1, CpuIdByte2, CpuIdByte3;
+
+ CopyMem (New, &CpuDevice, sizeof (SBSAQEMU_ACPI_CPU_DEVICE));
+ CpuDevicePtr = (SBSAQEMU_ACPI_CPU_DEVICE *) New;
+
+ CpuIdByte1 = CpuId & 0xF;
+ CpuIdByte2 = (CpuId >> 4) & 0xF;
+ CpuIdByte3 = (CpuId >> 8) & 0xF;
+
+ CpuDevicePtr->dev_name[1] = SBSAQEMU_ACPI_ITOA(CpuIdByte3);
+ CpuDevicePtr->dev_name[2] = SBSAQEMU_ACPI_ITOA(CpuIdByte2);
+ CpuDevicePtr->dev_name[3] = SBSAQEMU_ACPI_ITOA(CpuIdByte1);
+
+ CpuDevicePtr->uid[6] = CpuIdByte1 | CpuIdByte2;
+ CpuDevicePtr->uid[7] = CpuIdByte3;
+ New += sizeof (SBSAQEMU_ACPI_CPU_DEVICE);
+ }
+
+ // Perform Checksum
+ AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ (EFI_ACPI_COMMON_HEADER *)PageAddress,
+ TableSize,
+ &TableHandle
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Failed to install SSDT table\n"));
+ }
+
+ return Status;
+}
+
EFI_STATUS
EFIAPI
InitializeSbsaQemuAcpiDxe (
@@ -231,5 +370,10 @@ InitializeSbsaQemuAcpiDxe (
DEBUG((EFI_D_ERROR, "Failed to add MADT table\n"));
}
+ Status = AddSsdtTable (AcpiTable);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n"));
+ }
+
return EFI_SUCCESS;
}
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 7a9a0061675f..60acc083ddbb 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -43,4 +43,33 @@
#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00
#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF
+#define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5
+
+#define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' }
+
+#define SBSAQEMU_ACPI_CPU_DEV_LEN 0x1C
+#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' }
+
+// Macro to convert Integer to Character
+#define SBSAQEMU_ACPI_ITOA(Byte) (0x30 + (Byte > 9 ? (Byte + 1) : Byte))
+
+#define SBSAQEMU_ACPI_CPU_HID { \
+ AML_NAME_OP, AML_NAME_CHAR__, 'H', 'I', 'D', \
+ AML_STRING_PREFIX, 'A', 'C', 'P', 'I', '0', '0', '0', '7', \
+ AML_ZERO_OP \
+ }
+
+#define SBSAQEMU_ACPI_CPU_UID { \
+ AML_NAME_OP, AML_NAME_CHAR__, 'U', 'I', 'D', AML_BYTE_PREFIX, \
+ AML_ZERO_OP, AML_ZERO_OP \
+ }
+
+typedef struct {
+ UINT8 device_header[2];
+ UINT8 length;
+ UINT8 dev_name[4];
+ UINT8 hid[15];
+ UINT8 uid[8];
+} SBSAQEMU_ACPI_CPU_DEVICE;
+
#endif
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH edk2-platforms 5/7] SbsaQemu: AcpiDxe: Create SSDT table at runtime
2020-08-19 14:30 ` [PATCH edk2-platforms 5/7] SbsaQemu: AcpiDxe: Create SSDT " Tanmay Jagdale
@ 2020-08-20 12:09 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2020-08-20 12:09 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: graeme, shashi.mallela, devel, paul.isaacs, tanmay
On Wed, Aug 19, 2020 at 20:00:03 +0530, Tanmay Jagdale wrote:
> - Add support to create SSDT table at runtime. Since SSDT
> table is a data table, added a few helper macros to create
> the AML entries.
> - Also added a function to calculate the length of Packages.
>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 144 ++++++++++++++++++
> .../Include/IndustryStandard/SbsaQemuAcpi.h | 29 ++++
> 2 files changed, 173 insertions(+)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index 569cda8b6474..d90ce0c2a718 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -9,6 +9,7 @@
> #include <IndustryStandard/Acpi.h>
> #include <IndustryStandard/Acpi10.h>
> #include <IndustryStandard/Acpi60.h>
> +#include <IndustryStandard/AcpiAml.h>
> #include <IndustryStandard/SbsaQemuAcpi.h>
> #include <Library/AcpiLib.h>
> #include <Library/BaseMemoryLib.h>
> @@ -202,6 +203,144 @@ AddMadtTable (
> return Status;
> }
>
> +/*
> + * Function to calculate the PkgLength field in ACPI tables
> + */
> +STATIC
> +UINT32
> +SetPkgLength (
> + IN UINT8 *TablePtr,
> + IN UINT32 Length
> +)
> +{
> + UINT8 ByteCount;
> + UINT8 *PkgLeadByte = TablePtr;
> +
> + if (Length < 64) {
> + *TablePtr = Length;
> + return 1;
> + }
> +
> + // Set the LSB of Length in PkgLeadByte and advance Length
> + *PkgLeadByte = Length & 0xF;
> + Length = Length >> 4;
> +
> + while (Length) {
> + TablePtr++;
> + *TablePtr = (Length & 0xFF);
> + Length = (Length >> 8);
> + }
> +
> + // Calculate the number of bytes the Length field uses
> + // and set the ByteCount field in PkgLeadByte.
> + ByteCount = (TablePtr - PkgLeadByte) & 0xF;
> + *PkgLeadByte |= (ByteCount << 6);
> +
> + return ByteCount + 1;
> +}
> +
> +/*
> + * A function that adds SSDT ACPI table.
> + */
> +EFI_STATUS
> +AddSsdtTable (
> + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> + )
> +{
> + EFI_STATUS Status;
> + UINTN TableHandle;
> + UINT32 TableSize;
> + EFI_PHYSICAL_ADDRESS PageAddress;
> + UINT8 *New;
> + UINT32 CpuId;
> + UINT32 Offset;
> + UINT8 ScopeOpName[] = SBSAQEMU_ACPI_SCOPE_NAME;
> + UINT32 NumCores = PcdGet32 (PcdCoreCount);
> +
> + EFI_ACPI_DESCRIPTION_HEADER Header =
> + SBSAQEMU_ACPI_HEADER (
> + EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_DESCRIPTION_HEADER,
> + EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION);
> +
> + SBSAQEMU_ACPI_CPU_DEVICE CpuDevice = {
> + { AML_EXT_OP, AML_EXT_DEVICE_OP }, /* Device () */
> + SBSAQEMU_ACPI_CPU_DEV_LEN, /* Length */
> + SBSAQEMU_ACPI_CPU_DEV_NAME, /* Device Name "C000" */
> + SBSAQEMU_ACPI_CPU_HID, /* Name (HID, "ACPI0007") */
> + SBSAQEMU_ACPI_CPU_UID, /* Name (UID, 0) */
> + };
> +
> + // Calculate the new table size based on the number of cores
> + TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> + SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH + sizeof (ScopeOpName) +
> + (sizeof (CpuDevice) * NumCores);
Above line contains a tab. <edk2>/BaseTools/Scripts/PatchCheck.py will
find this (and some other issues) for you. Please run over whole set
and fix any reporeted issues before submitting v2.
/
Leif
> +
> + Status = gBS->AllocatePages (
> + AllocateAnyPages,
> + EfiACPIReclaimMemory,
> + EFI_SIZE_TO_PAGES (TableSize),
> + &PageAddress
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "Failed to allocate pages for SSDT table\n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + New = (UINT8 *)(UINTN) PageAddress;
> + ZeroMem (New, TableSize);
> +
> + // Add the ACPI Description table header
> + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
> + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
> + New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> +
> + // Insert the top level ScopeOp
> + *New = AML_SCOPE_OP;
> + New++;
> + Offset = SetPkgLength (New,
> + (TableSize - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - 1));
> + New += Offset;
> + CopyMem (New, &ScopeOpName, sizeof (ScopeOpName));
> + New += sizeof (ScopeOpName);
> +
> + // Add new Device structures for the Cores
> + for (CpuId = 0; CpuId < NumCores; CpuId++) {
> + SBSAQEMU_ACPI_CPU_DEVICE *CpuDevicePtr;
> + UINT8 CpuIdByte1, CpuIdByte2, CpuIdByte3;
> +
> + CopyMem (New, &CpuDevice, sizeof (SBSAQEMU_ACPI_CPU_DEVICE));
> + CpuDevicePtr = (SBSAQEMU_ACPI_CPU_DEVICE *) New;
> +
> + CpuIdByte1 = CpuId & 0xF;
> + CpuIdByte2 = (CpuId >> 4) & 0xF;
> + CpuIdByte3 = (CpuId >> 8) & 0xF;
> +
> + CpuDevicePtr->dev_name[1] = SBSAQEMU_ACPI_ITOA(CpuIdByte3);
> + CpuDevicePtr->dev_name[2] = SBSAQEMU_ACPI_ITOA(CpuIdByte2);
> + CpuDevicePtr->dev_name[3] = SBSAQEMU_ACPI_ITOA(CpuIdByte1);
> +
> + CpuDevicePtr->uid[6] = CpuIdByte1 | CpuIdByte2;
> + CpuDevicePtr->uid[7] = CpuIdByte3;
> + New += sizeof (SBSAQEMU_ACPI_CPU_DEVICE);
> + }
> +
> + // Perform Checksum
> + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
> +
> + Status = AcpiTable->InstallAcpiTable (
> + AcpiTable,
> + (EFI_ACPI_COMMON_HEADER *)PageAddress,
> + TableSize,
> + &TableHandle
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "Failed to install SSDT table\n"));
> + }
> +
> + return Status;
> +}
> +
> EFI_STATUS
> EFIAPI
> InitializeSbsaQemuAcpiDxe (
> @@ -231,5 +370,10 @@ InitializeSbsaQemuAcpiDxe (
> DEBUG((EFI_D_ERROR, "Failed to add MADT table\n"));
> }
>
> + Status = AddSsdtTable (AcpiTable);
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n"));
> + }
> +
> return EFI_SUCCESS;
> }
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> index 7a9a0061675f..60acc083ddbb 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -43,4 +43,33 @@
> #define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00
> #define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF
>
> +#define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5
> +
> +#define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' }
> +
> +#define SBSAQEMU_ACPI_CPU_DEV_LEN 0x1C
> +#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' }
> +
> +// Macro to convert Integer to Character
> +#define SBSAQEMU_ACPI_ITOA(Byte) (0x30 + (Byte > 9 ? (Byte + 1) : Byte))
> +
> +#define SBSAQEMU_ACPI_CPU_HID { \
> + AML_NAME_OP, AML_NAME_CHAR__, 'H', 'I', 'D', \
> + AML_STRING_PREFIX, 'A', 'C', 'P', 'I', '0', '0', '0', '7', \
> + AML_ZERO_OP \
> + }
> +
> +#define SBSAQEMU_ACPI_CPU_UID { \
> + AML_NAME_OP, AML_NAME_CHAR__, 'U', 'I', 'D', AML_BYTE_PREFIX, \
> + AML_ZERO_OP, AML_ZERO_OP \
> + }
> +
> +typedef struct {
> + UINT8 device_header[2];
> + UINT8 length;
> + UINT8 dev_name[4];
> + UINT8 hid[15];
> + UINT8 uid[8];
> +} SBSAQEMU_ACPI_CPU_DEVICE;
> +
> #endif
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT table at runtime
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (4 preceding siblings ...)
2020-08-19 14:30 ` [PATCH edk2-platforms 5/7] SbsaQemu: AcpiDxe: Create SSDT " Tanmay Jagdale
@ 2020-08-19 14:30 ` Tanmay Jagdale
2020-08-20 12:12 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 7/7] SbsaQemu: AcpiTables: Add DBG2 Table Tanmay Jagdale
2020-08-20 12:15 ` [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Leif Lindholm
7 siblings, 1 reply; 16+ messages in thread
From: Tanmay Jagdale @ 2020-08-19 14:30 UTC (permalink / raw)
To: leif, graeme, shashi.mallela, devel; +Cc: paul.isaacs, tanmay, Tanmay Jagdale
Add support to create Processor Properties Topology Table at
runtime. The cache topology of each CPU is as follows:
CPU N
------------------------
| -------- -------- |
| | L1-I | | L1-D | |
| | 32KB | | 32KB | |
| -------- -------- |
| ------------------ |
| | L2 512KB | |
| ------------------ |
------------------------
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 111 ++++++++++++++++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 124 ++++++++++++++++++
2 files changed, 235 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index d90ce0c2a718..8527b976ee33 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -9,6 +9,7 @@
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/Acpi10.h>
#include <IndustryStandard/Acpi60.h>
+#include <IndustryStandard/Acpi63.h>
#include <IndustryStandard/AcpiAml.h>
#include <IndustryStandard/SbsaQemuAcpi.h>
#include <Library/AcpiLib.h>
@@ -341,6 +342,111 @@ AddSsdtTable (
return Status;
}
+/*
+ * A function that adds the SSDT ACPI table.
+ */
+EFI_STATUS
+AddPpttTable (
+ IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN TableHandle;
+ UINT32 TableSize;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINT8 *New;
+ UINT32 CpuId;
+ UINT32 NumCores = PcdGet32 (PcdCoreCount);
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT;
+
+ EFI_ACPI_DESCRIPTION_HEADER Header =
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_DESCRIPTION_HEADER,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION);
+
+ TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) +
+ (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) +
+ (sizeof (UINT32) * 2 * NumCores);
+
+ Status = gBS->AllocatePages (
+ AllocateAnyPages,
+ EfiACPIReclaimMemory,
+ EFI_SIZE_TO_PAGES (TableSize),
+ &PageAddress
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Failed to allocate pages for PPTT table\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ New = (UINT8 *)(UINTN) PageAddress;
+ ZeroMem (New, TableSize);
+
+ // Add the ACPI Description table header
+ CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
+ ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
+ New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
+
+ // Add the Cluster PPTT structure
+ CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ // Add L1 D Cache structure
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = 0; /* L2 is LLC */
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ for (CpuId = 0; CpuId < NumCores; CpuId++) {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr;
+ UINT32 *PrivateResourcePtr;
+
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New;
+ CorePtr->Parent = CLUSTER_INDEX;
+ CorePtr->AcpiProcessorId = CpuId;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ PrivateResourcePtr = (UINT32 *) New;
+ PrivateResourcePtr[0] = L1_D_CACHE_INDEX;
+ PrivateResourcePtr[1] = L1_I_CACHE_INDEX;
+ New += (2 * sizeof (UINT32));
+ }
+
+ // Perform Checksum
+ AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ (EFI_ACPI_COMMON_HEADER *)PageAddress,
+ TableSize,
+ &TableHandle
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Failed to install PPTT table\n"));
+ }
+
+ return Status;
+}
+
EFI_STATUS
EFIAPI
InitializeSbsaQemuAcpiDxe (
@@ -375,5 +481,10 @@ InitializeSbsaQemuAcpiDxe (
DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n"));
}
+ Status = AddPpttTable (AcpiTable);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Failed to add PPTT table\n"));
+ }
+
return EFI_SUCCESS;
}
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 60acc083ddbb..95cfca4727a6 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -72,4 +72,128 @@ typedef struct {
UINT8 uid[8];
} SBSAQEMU_ACPI_CPU_DEVICE;
+#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB
+#define SBSAQEMU_L1_D_CACHE_SETS 256
+#define SBSAQEMU_L1_D_CACHE_ASSC 2
+
+#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB
+#define SBSAQEMU_L1_I_CACHE_SETS 256
+#define SBSAQEMU_L1_I_CACHE_ASSC 2
+
+#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB
+#define SBSAQEMU_L2_CACHE_SETS 1024
+#define SBSAQEMU_L2_CACHE_ASSC 8
+
+#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
+#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+
+#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
+ SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
+ SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }
+
+#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 0, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
+ SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
+ SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ 0, \
+ }, \
+ 64 /* LineSize */ \
+ }
+
+#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
+ SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
+ SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }
+
+#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
+ }, \
+ 0, /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 0, /* NumberOfPrivateResources */ \
+ }
+
+#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
+ (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
+ }, \
+ 0, /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 2, /* NumberOfPrivateResources */ \
+ }
+
#endif
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT table at runtime
2020-08-19 14:30 ` [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT " Tanmay Jagdale
@ 2020-08-20 12:12 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2020-08-20 12:12 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: graeme, shashi.mallela, devel, paul.isaacs, tanmay
On Wed, Aug 19, 2020 at 20:00:04 +0530, Tanmay Jagdale wrote:
> Add support to create Processor Properties Topology Table at
> runtime. The cache topology of each CPU is as follows:
>
> CPU N
> ------------------------
> | -------- -------- |
> | | L1-I | | L1-D | |
> | | 32KB | | 32KB | |
> | -------- -------- |
> | ------------------ |
> | | L2 512KB | |
> | ------------------ |
> ------------------------
>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 111 ++++++++++++++++
> .../Include/IndustryStandard/SbsaQemuAcpi.h | 124 ++++++++++++++++++
> 2 files changed, 235 insertions(+)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index d90ce0c2a718..8527b976ee33 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -9,6 +9,7 @@
> #include <IndustryStandard/Acpi.h>
> #include <IndustryStandard/Acpi10.h>
> #include <IndustryStandard/Acpi60.h>
> +#include <IndustryStandard/Acpi63.h>
So, if your edk2 tree is newer than Wed May 15 2020, this will
automatically be pulled in by Acpi.h.
/
Leif
> #include <IndustryStandard/AcpiAml.h>
> #include <IndustryStandard/SbsaQemuAcpi.h>
> #include <Library/AcpiLib.h>
> @@ -341,6 +342,111 @@ AddSsdtTable (
> return Status;
> }
>
> +/*
> + * A function that adds the SSDT ACPI table.
> + */
> +EFI_STATUS
> +AddPpttTable (
> + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> + )
> +{
> + EFI_STATUS Status;
> + UINTN TableHandle;
> + UINT32 TableSize;
> + EFI_PHYSICAL_ADDRESS PageAddress;
> + UINT8 *New;
> + UINT32 CpuId;
> + UINT32 NumCores = PcdGet32 (PcdCoreCount);
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT;
> +
> + EFI_ACPI_DESCRIPTION_HEADER Header =
> + SBSAQEMU_ACPI_HEADER (
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_DESCRIPTION_HEADER,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION);
> +
> + TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) +
> + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) +
> + (sizeof (UINT32) * 2 * NumCores);
> +
> + Status = gBS->AllocatePages (
> + AllocateAnyPages,
> + EfiACPIReclaimMemory,
> + EFI_SIZE_TO_PAGES (TableSize),
> + &PageAddress
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "Failed to allocate pages for PPTT table\n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + New = (UINT8 *)(UINTN) PageAddress;
> + ZeroMem (New, TableSize);
> +
> + // Add the ACPI Description table header
> + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
> + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
> + New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> +
> + // Add the Cluster PPTT structure
> + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> +
> + // Add L1 D Cache structure
> + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX;
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + // Add L1 I Cache structure
> + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX;
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + // Add L2 Cache structure
> + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = 0; /* L2 is LLC */
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + for (CpuId = 0; CpuId < NumCores; CpuId++) {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr;
> + UINT32 *PrivateResourcePtr;
> +
> + CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> + CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New;
> + CorePtr->Parent = CLUSTER_INDEX;
> + CorePtr->AcpiProcessorId = CpuId;
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> +
> + PrivateResourcePtr = (UINT32 *) New;
> + PrivateResourcePtr[0] = L1_D_CACHE_INDEX;
> + PrivateResourcePtr[1] = L1_I_CACHE_INDEX;
> + New += (2 * sizeof (UINT32));
> + }
> +
> + // Perform Checksum
> + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
> +
> + Status = AcpiTable->InstallAcpiTable (
> + AcpiTable,
> + (EFI_ACPI_COMMON_HEADER *)PageAddress,
> + TableSize,
> + &TableHandle
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "Failed to install PPTT table\n"));
> + }
> +
> + return Status;
> +}
> +
> EFI_STATUS
> EFIAPI
> InitializeSbsaQemuAcpiDxe (
> @@ -375,5 +481,10 @@ InitializeSbsaQemuAcpiDxe (
> DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n"));
> }
>
> + Status = AddPpttTable (AcpiTable);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((EFI_D_ERROR, "Failed to add PPTT table\n"));
> + }
> +
> return EFI_SUCCESS;
> }
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> index 60acc083ddbb..95cfca4727a6 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -72,4 +72,128 @@ typedef struct {
> UINT8 uid[8];
> } SBSAQEMU_ACPI_CPU_DEVICE;
>
> +#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB
> +#define SBSAQEMU_L1_D_CACHE_SETS 256
> +#define SBSAQEMU_L1_D_CACHE_ASSC 2
> +
> +#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB
> +#define SBSAQEMU_L1_I_CACHE_SETS 256
> +#define SBSAQEMU_L1_I_CACHE_ASSC 2
> +
> +#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB
> +#define SBSAQEMU_L2_CACHE_SETS 1024
> +#define SBSAQEMU_L2_CACHE_ASSC 8
> +
> +#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
> +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
> +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
> +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
> +
> +#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + 1, /* SizePropertyValid */ \
> + 1, /* NumberOfSetsValid */ \
> + 1, /* AssociativityValid */ \
> + 1, /* AllocationTypeValid */ \
> + 1, /* CacheTypeValid */ \
> + 1, /* WritePolicyValid */ \
> + 1, /* LineSizeValid */ \
> + }, \
> + 0, /* NextLevelOfCache */ \
> + SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
> + SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
> + SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
> + { \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
> + }, \
> + 64 /* LineSize */ \
> + }
> +
> +#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + 1, /* SizePropertyValid */ \
> + 1, /* NumberOfSetsValid */ \
> + 1, /* AssociativityValid */ \
> + 1, /* AllocationTypeValid */ \
> + 1, /* CacheTypeValid */ \
> + 0, /* WritePolicyValid */ \
> + 1, /* LineSizeValid */ \
> + }, \
> + 0, /* NextLevelOfCache */ \
> + SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
> + SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
> + SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
> + { \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
> + 0, \
> + }, \
> + 64 /* LineSize */ \
> + }
> +
> +#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + 1, /* SizePropertyValid */ \
> + 1, /* NumberOfSetsValid */ \
> + 1, /* AssociativityValid */ \
> + 1, /* AllocationTypeValid */ \
> + 1, /* CacheTypeValid */ \
> + 1, /* WritePolicyValid */ \
> + 1, /* LineSizeValid */ \
> + }, \
> + 0, /* NextLevelOfCache */ \
> + SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
> + SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
> + SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
> + { \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
> + }, \
> + 64 /* LineSize */ \
> + }
> +
> +#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
> + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
> + }, \
> + 0, /* Parent */ \
> + 0, /* AcpiProcessorId */ \
> + 0, /* NumberOfPrivateResources */ \
> + }
> +
> +#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
> + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
> + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
> + }, \
> + 0, /* Parent */ \
> + 0, /* AcpiProcessorId */ \
> + 2, /* NumberOfPrivateResources */ \
> + }
> +
> #endif
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH edk2-platforms 7/7] SbsaQemu: AcpiTables: Add DBG2 Table
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (5 preceding siblings ...)
2020-08-19 14:30 ` [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT " Tanmay Jagdale
@ 2020-08-19 14:30 ` Tanmay Jagdale
2020-08-20 12:13 ` Leif Lindholm
2020-08-20 12:15 ` [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Leif Lindholm
7 siblings, 1 reply; 16+ messages in thread
From: Tanmay Jagdale @ 2020-08-19 14:30 UTC (permalink / raw)
To: leif, graeme, shashi.mallela, devel; +Cc: paul.isaacs, tanmay, Tanmay Jagdale
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 68 +++++++++++++++++++
2 files changed, 69 insertions(+)
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 0b5017ce81c5..cf6628c9e491 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -17,6 +17,7 @@ [Defines]
[Sources]
Dsdt.asl
+ Dbg2.aslc
Fadt.aslc
Gtdt.aslc
Spcr.aslc
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
new file mode 100644
index 000000000000..801b05b59a42
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
@@ -0,0 +1,68 @@
+/** @file
+* Debug Port Table (DBG2)
+*
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/Acpi63.h>
+#include <IndustryStandard/DebugPort2Table.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+
+#pragma pack(1)
+
+#define SBSAQEMU_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '0', 0x00 }
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[10];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;
+} DBG2_TABLE;
+
+
+STATIC DBG2_TABLE Dbg2 = {
+ {
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+ DBG2_TABLE,
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION
+ ),
+ OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),
+ 1 /* NumberOfDebugPorts */
+ },
+ {
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION),
+ 1, /* NumberofGenericAddressRegisters */
+ 10, /* NameSpaceStringLength */
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),
+ 0, /* OemDataLength */
+ 0, /* OemDataOffset */
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)
+ },
+ ARM_GAS32 (SBSAQEMU_UART0_BASE), /* BaseAddressRegister */
+ 0x1000, /* AddressSize */
+ SBSAQEMU_UART_STR, /* NameSpaceString */
+ }
+};
+
+#pragma pack()
+
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Dbg2;
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH edk2-platforms 7/7] SbsaQemu: AcpiTables: Add DBG2 Table
2020-08-19 14:30 ` [PATCH edk2-platforms 7/7] SbsaQemu: AcpiTables: Add DBG2 Table Tanmay Jagdale
@ 2020-08-20 12:13 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2020-08-20 12:13 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: graeme, shashi.mallela, devel, paul.isaacs, tanmay
On Wed, Aug 19, 2020 at 20:00:05 +0530, Tanmay Jagdale wrote:
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
> Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 68 +++++++++++++++++++
> 2 files changed, 69 insertions(+)
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
>
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> index 0b5017ce81c5..cf6628c9e491 100644
> --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> @@ -17,6 +17,7 @@ [Defines]
>
> [Sources]
> Dsdt.asl
> + Dbg2.aslc
That should go before Dsdt.asl.
> Fadt.aslc
> Gtdt.aslc
> Spcr.aslc
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
> new file mode 100644
> index 000000000000..801b05b59a42
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
> @@ -0,0 +1,68 @@
> +/** @file
> +* Debug Port Table (DBG2)
> +*
> +* Copyright (c) 2020 Linaro Ltd. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +#include <IndustryStandard/Acpi.h>
> +#include <IndustryStandard/Acpi63.h>
Can drop Acpi63.h.
/
Leif
> +#include <IndustryStandard/DebugPort2Table.h>
> +#include <IndustryStandard/SbsaQemuAcpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/PcdLib.h>
> +
> +#pragma pack(1)
> +
> +#define SBSAQEMU_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '0', 0x00 }
> +
> +typedef struct {
> + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
> + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
> + UINT32 AddressSize;
> + UINT8 NameSpaceString[10];
> +} DBG2_DEBUG_DEVICE_INFORMATION;
> +
> +typedef struct {
> + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
> + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;
> +} DBG2_TABLE;
> +
> +
> +STATIC DBG2_TABLE Dbg2 = {
> + {
> + SBSAQEMU_ACPI_HEADER (
> + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
> + DBG2_TABLE,
> + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION
> + ),
> + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),
> + 1 /* NumberOfDebugPorts */
> + },
> + {
> + {
> + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
> + sizeof (DBG2_DEBUG_DEVICE_INFORMATION),
> + 1, /* NumberofGenericAddressRegisters */
> + 10, /* NameSpaceStringLength */
> + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),
> + 0, /* OemDataLength */
> + 0, /* OemDataOffset */
> + EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
> + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
> + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
> + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),
> + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)
> + },
> + ARM_GAS32 (SBSAQEMU_UART0_BASE), /* BaseAddressRegister */
> + 0x1000, /* AddressSize */
> + SBSAQEMU_UART_STR, /* NameSpaceString */
> + }
> +};
> +
> +#pragma pack()
> +
> +// Reference the table being generated to prevent the optimizer from removing
> +// the data structure from the executable
> +VOID* CONST ReferenceAcpiTable = &Dbg2;
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (6 preceding siblings ...)
2020-08-19 14:30 ` [PATCH edk2-platforms 7/7] SbsaQemu: AcpiTables: Add DBG2 Table Tanmay Jagdale
@ 2020-08-20 12:15 ` Leif Lindholm
7 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2020-08-20 12:15 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: graeme, shashi.mallela, devel, paul.isaacs, tanmay
Thanks.
All done reviewing. On the whole, it looks good, but there are some
minor things left to clean up. So please send out a v2 based on the
comments I made.
Best Regards,
Leif
On Wed, Aug 19, 2020 at 19:59:58 +0530, Tanmay Jagdale wrote:
> This patch series adds ACPI tables support for the SbsaQemu platform.
> We are using a pseudo static approach to create the ACPI tables.
>
> The ACPI tables namely DBG2, DSDT, MCFG, SPCR, GTDT are created in a
> static way at compile time because they hold a fixed configuration
> and there are no changes at runtime.
>
> The MADT, SSDT and PPTT tables are dependant on the number of CPUs and
> hence they are created at runtime based on the number of CPUs the user
> has requested.
>
> Tanmay Jagdale (7):
> SbsaQemu: Initial support for static ACPI tables
> SbsaQemu: AcpiTables: Add PCI support and MCFG Table
> SbsaQemu: Add new ACPI driver and FDT parser to count CPUs
> SbsaQemu: AcpiDxe: Create MADT table at runtime
> SbsaQemu: AcpiDxe: Create SSDT table at runtime
> SbsaQemu: AcpiDxe: Create PPTT table at runtime
> SbsaQemu: AcpiTables: Add DBG2 Table
>
> Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 12 +-
> Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 9 +
> Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 36 ++
> .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 47 ++
> Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 68 +++
> Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 449 ++++++++++++++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 80 +++
> Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 67 +++
> Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 ++
> Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 53 ++
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 490 ++++++++++++++++++
> .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 67 +++
> .../Include/IndustryStandard/SbsaQemuAcpi.h | 199 +++++++
> Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 8 +-
> 14 files changed, 1624 insertions(+), 4 deletions(-)
> create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> create mode 100644 Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
>
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread