From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.groups.io with SMTP id smtpd.web11.108572.1597923655512902711 for ; Thu, 20 Aug 2020 04:40:55 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=daHPYEMR; spf=pass (domain: nuviainc.com, ip: 209.85.221.68, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f68.google.com with SMTP id l2so1701921wrc.7 for ; Thu, 20 Aug 2020 04:40:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=eW7eCGNYaGnPFRB+kIgwyphRTgU6HjFeQxJxX0N8TuU=; b=daHPYEMRNVoBdQQVDwduSZiZzQn3oZ4cBGz2xl+IfrAGDWy0f+XNl68LclRiVWeR5T 5qqogK4KIvGy/CusH6+vuP2RQcoNLXGj0GwE6N5OEIrv+QZvPfuZhXp9jQ14fGi73ybZ xxeRosK6NzU+dacp7Y0X9oKVRRg6pk5SUpEls4spKciyJCiPM645Lej0SXdVyyt1N4JL KlfOgZN8FcyPU+49HBS3qusNyIDhGj4bi9kxZNMSOwC4CVMNjDRPd/ngDmpce5pHZFZ1 HNgmSx+pFFu6Ac7BIJApUNo8hD4i7SsEkqhszjcDhz3KIOFUzObDbPqE9Kq8LMbDIeEF kDLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=eW7eCGNYaGnPFRB+kIgwyphRTgU6HjFeQxJxX0N8TuU=; b=OqLm2n0GZpLPyqGqsLFa44PNtI4jBVcAEHFXJo4uLBLPYc6+WIH83AOjast8yJcMCN Xl17rhYzZrro3fYjubeJ7uXJG22pJUsRn0atpslRvq/gg9vmLWMyJ7fsjfQp8+uB3UMw X6oHcP4LNUAsDni+wKYh6BKY2k4DDyk8G0nQxHDc+wODmU+LJwAppLlqxgrWak1D3zg/ 8UKsuiwW7ojVv66pjy8XHTkjjqabOxfqSjrKmXoaADWW/TUe1iJoqhQThKkCnw00g1so PgPPUyg5oBQQAHZb2FHVwoRalxUvOYtOJmU01j46FoV8eczxdBj10POD97TyeCn1ufEq TpSA== X-Gm-Message-State: AOAM531Fr2bnmIMqcPx3udmCaoi4w63EYjGbOdnmLNJowgLfdPl7xPsy Zvm5gQnT3fjH23nsbhrkC+6oDg== X-Google-Smtp-Source: ABdhPJzGA81NFO0dgF4mjjqjy2N+gHzXabsHUcE0b3cUYibOCMeec57wYD1m0mST+56qX8zQemiEGg== X-Received: by 2002:a5d:6744:: with SMTP id l4mr2803072wrw.284.1597923653818; Thu, 20 Aug 2020 04:40:53 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id j11sm3807068wrw.79.2020.08.20.04.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2020 04:40:53 -0700 (PDT) Date: Thu, 20 Aug 2020 12:40:51 +0100 From: "Leif Lindholm" To: Tanmay Jagdale Cc: graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io, paul.isaacs@linaro.org, tanmay@marvell.com, Graeme Gregory Subject: Re: [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Message-ID: <20200820114051.GC1191@vanye> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> <20200819143005.13999-3-tanmay.jagdale@linaro.org> MIME-Version: 1.0 In-Reply-To: <20200819143005.13999-3-tanmay.jagdale@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Aug 19, 2020 at 20:00:00 +0530, Tanmay Jagdale wrote: > Add PCI related entries to DSDT table along with the routing > entries. Also add the MCFG table. > > Co-authored-by: Graeme Gregory > Signed-off-by: Tanmay Jagdale > --- > .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + > Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 316 ++++++++++++++++++ > Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 +++ > 3 files changed, 360 insertions(+) > create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc > > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > index ee524895524e..0b5017ce81c5 100644 > --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > @@ -20,6 +20,7 @@ [Sources] > Fadt.aslc > Gtdt.aslc > Spcr.aslc > + Mcfg.aslc Please insert alphabetically sorted. > > [Packages] > ArmPlatformPkg/ArmPlatformPkg.dec > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl > index 85339d4559d3..2d3d4a2ddedc 100644 > --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl > @@ -8,6 +8,23 @@ > > #include > > +#define LINK_DEVICE(Uid, LinkName, Irq) \ > + Device (LinkName) { \ > + Name (_HID, EISAID("PNP0C0F")) \ > + Name (_UID, Uid) \ > + Name (_PRS, ResourceTemplate() { \ > + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \ > + }) \ > + Method (_CRS, 0) { Return (_PRS) } \ > + Method (_SRS, 1) { } \ > + Method (_DIS) { } \ > + } > + > +#define PRT_ENTRY(Address, Pin, Link) \ > + Package (4) { \ > + Address, Pin, Link, Zero \ > + } > + > DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU", > FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { > Scope (_SB) { > @@ -129,5 +146,304 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU", > } // USB0_RHUB > } // USB0 > > + Device (PCI0) > + { > + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge > + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge > + Name (_SEG, Zero) // PCI Segment Group number > + Name (_BBN, Zero) // PCI Base Bus Number > + Name (_ADR, Zero) > + Name (_UID, "PCI0") > + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) > + > + Method (_CBA, 0, NotSerialized) { > + return (0xf0000000) > + } > + > + LINK_DEVICE(0, GSI0, 0x23) > + LINK_DEVICE(1, GSI1, 0x24) > + LINK_DEVICE(2, GSI2, 0x25) > + LINK_DEVICE(3, GSI3, 0x26) > + > + Name (_PRT, Package () // _PRT: PCI Routing Table > + { > + PRT_ENTRY(0x0000FFFF, 0, GSI0), > + PRT_ENTRY(0x0000FFFF, 0, GSI1), > + PRT_ENTRY(0x0000FFFF, 0, GSI2), > + PRT_ENTRY(0x0000FFFF, 0, GSI3), > + > + PRT_ENTRY(0x0001FFFF, 0, GSI1), > + PRT_ENTRY(0x0001FFFF, 1, GSI2), > + PRT_ENTRY(0x0001FFFF, 2, GSI3), > + PRT_ENTRY(0x0001FFFF, 3, GSI0), > + > + PRT_ENTRY(0x0002FFFF, 0, GSI2), > + PRT_ENTRY(0x0002FFFF, 1, GSI3), > + PRT_ENTRY(0x0002FFFF, 2, GSI0), > + PRT_ENTRY(0x0002FFFF, 3, GSI1), > + > + PRT_ENTRY(0x0003FFFF, 0, GSI3), > + PRT_ENTRY(0x0003FFFF, 1, GSI0), > + PRT_ENTRY(0x0003FFFF, 2, GSI1), > + PRT_ENTRY(0x0003FFFF, 3, GSI2), > + > + PRT_ENTRY(0x0004FFFF, 0, GSI0), > + PRT_ENTRY(0x0004FFFF, 1, GSI1), > + PRT_ENTRY(0x0004FFFF, 2, GSI2), > + PRT_ENTRY(0x0004FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0005FFFF, 0, GSI1), > + PRT_ENTRY(0x0005FFFF, 1, GSI2), > + PRT_ENTRY(0x0005FFFF, 2, GSI3), > + PRT_ENTRY(0x0005FFFF, 3, GSI0), > + > + PRT_ENTRY(0x0006FFFF, 0, GSI2), > + PRT_ENTRY(0x0006FFFF, 1, GSI3), > + PRT_ENTRY(0x0006FFFF, 2, GSI0), > + PRT_ENTRY(0x0006FFFF, 3, GSI1), > + > + PRT_ENTRY(0x0007FFFF, 0, GSI3), > + PRT_ENTRY(0x0007FFFF, 1, GSI0), > + PRT_ENTRY(0x0007FFFF, 2, GSI1), > + PRT_ENTRY(0x0007FFFF, 3, GSI2), > + > + PRT_ENTRY(0x0008FFFF, 0, GSI0), > + PRT_ENTRY(0x0008FFFF, 1, GSI1), > + PRT_ENTRY(0x0008FFFF, 2, GSI2), > + PRT_ENTRY(0x0008FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0009FFFF, 0, GSI1), > + PRT_ENTRY(0x0009FFFF, 1, GSI2), > + PRT_ENTRY(0x0009FFFF, 2, GSI3), > + PRT_ENTRY(0x0009FFFF, 3, GSI0), > + > + PRT_ENTRY(0x000AFFFF, 0, GSI2), > + PRT_ENTRY(0x000AFFFF, 1, GSI3), > + PRT_ENTRY(0x000AFFFF, 2, GSI0), > + PRT_ENTRY(0x000AFFFF, 3, GSI1), > + > + PRT_ENTRY(0x000BFFFF, 0, GSI3), > + PRT_ENTRY(0x000BFFFF, 1, GSI0), > + PRT_ENTRY(0x000BFFFF, 2, GSI1), > + PRT_ENTRY(0x000BFFFF, 3, GSI2), > + > + PRT_ENTRY(0x000CFFFF, 0, GSI0), > + PRT_ENTRY(0x000CFFFF, 1, GSI1), > + PRT_ENTRY(0x000CFFFF, 2, GSI2), > + PRT_ENTRY(0x000CFFFF, 3, GSI3), > + > + PRT_ENTRY(0x000DFFFF, 0, GSI1), > + PRT_ENTRY(0x000DFFFF, 1, GSI2), > + PRT_ENTRY(0x000DFFFF, 2, GSI3), > + PRT_ENTRY(0x000DFFFF, 3, GSI0), > + > + PRT_ENTRY(0x000EFFFF, 0, GSI2), > + PRT_ENTRY(0x000EFFFF, 1, GSI3), > + PRT_ENTRY(0x000EFFFF, 2, GSI0), > + PRT_ENTRY(0x000EFFFF, 3, GSI1), > + > + PRT_ENTRY(0x000FFFFF, 0, GSI3), > + PRT_ENTRY(0x000FFFFF, 1, GSI0), > + PRT_ENTRY(0x000FFFFF, 2, GSI1), > + PRT_ENTRY(0x000FFFFF, 3, GSI2), > + > + PRT_ENTRY(0x0010FFFF, 0, GSI0), > + PRT_ENTRY(0x0010FFFF, 1, GSI1), > + PRT_ENTRY(0x0010FFFF, 2, GSI2), > + PRT_ENTRY(0x0010FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0011FFFF, 0, GSI1), > + PRT_ENTRY(0x0011FFFF, 1, GSI2), > + PRT_ENTRY(0x0011FFFF, 2, GSI3), > + PRT_ENTRY(0x0011FFFF, 3, GSI0), > + > + PRT_ENTRY(0x0012FFFF, 0, GSI2), > + PRT_ENTRY(0x0012FFFF, 1, GSI3), > + PRT_ENTRY(0x0012FFFF, 2, GSI0), > + PRT_ENTRY(0x0012FFFF, 3, GSI1), > + > + PRT_ENTRY(0x0013FFFF, 0, GSI3), > + PRT_ENTRY(0x0013FFFF, 1, GSI0), > + PRT_ENTRY(0x0013FFFF, 2, GSI1), > + PRT_ENTRY(0x0013FFFF, 3, GSI2), > + > + PRT_ENTRY(0x0014FFFF, 0, GSI0), > + PRT_ENTRY(0x0014FFFF, 1, GSI1), > + PRT_ENTRY(0x0014FFFF, 2, GSI2), > + PRT_ENTRY(0x0014FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0015FFFF, 0, GSI1), > + PRT_ENTRY(0x0015FFFF, 1, GSI2), > + PRT_ENTRY(0x0015FFFF, 2, GSI3), > + PRT_ENTRY(0x0015FFFF, 3, GSI0), > + > + PRT_ENTRY(0x0016FFFF, 0, GSI2), > + PRT_ENTRY(0x0016FFFF, 1, GSI3), > + PRT_ENTRY(0x0016FFFF, 2, GSI0), > + PRT_ENTRY(0x0016FFFF, 3, GSI1), > + > + PRT_ENTRY(0x0017FFFF, 0, GSI3), > + PRT_ENTRY(0x0017FFFF, 1, GSI0), > + PRT_ENTRY(0x0017FFFF, 2, GSI1), > + PRT_ENTRY(0x0017FFFF, 3, GSI2), > + > + PRT_ENTRY(0x0018FFFF, 0, GSI0), > + PRT_ENTRY(0x0018FFFF, 1, GSI1), > + PRT_ENTRY(0x0018FFFF, 2, GSI2), > + PRT_ENTRY(0x0018FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0019FFFF, 0, GSI1), > + PRT_ENTRY(0x0019FFFF, 1, GSI2), > + PRT_ENTRY(0x0019FFFF, 2, GSI3), > + PRT_ENTRY(0x0019FFFF, 3, GSI0), > + > + PRT_ENTRY(0x001AFFFF, 0, GSI2), > + PRT_ENTRY(0x001AFFFF, 1, GSI3), > + PRT_ENTRY(0x001AFFFF, 2, GSI0), > + PRT_ENTRY(0x001AFFFF, 3, GSI1), > + > + PRT_ENTRY(0x001BFFFF, 0, GSI3), > + PRT_ENTRY(0x001BFFFF, 1, GSI0), > + PRT_ENTRY(0x001BFFFF, 2, GSI1), > + PRT_ENTRY(0x001BFFFF, 3, GSI2), > + > + PRT_ENTRY(0x001CFFFF, 0, GSI0), > + PRT_ENTRY(0x001CFFFF, 1, GSI1), > + PRT_ENTRY(0x001CFFFF, 2, GSI2), > + PRT_ENTRY(0x001CFFFF, 3, GSI3), > + > + PRT_ENTRY(0x001DFFFF, 0, GSI1), > + PRT_ENTRY(0x001DFFFF, 1, GSI2), > + PRT_ENTRY(0x001DFFFF, 2, GSI3), > + PRT_ENTRY(0x001DFFFF, 3, GSI0), > + > + PRT_ENTRY(0x001EFFFF, 0, GSI2), > + PRT_ENTRY(0x001EFFFF, 1, GSI3), > + PRT_ENTRY(0x001EFFFF, 2, GSI0), > + PRT_ENTRY(0x001EFFFF, 3, GSI1), > + > + PRT_ENTRY(0x001FFFFF, 0, GSI3), > + PRT_ENTRY(0x001FFFFF, 1, GSI0), > + PRT_ENTRY(0x001FFFFF, 2, GSI1), > + PRT_ENTRY(0x001FFFFF, 3, GSI2), > + }) > + > + // Root complex resources > + Method (_CRS, 0, Serialized) { > + Name (RBUF, ResourceTemplate () { > + WordBusNumber ( // Bus numbers assigned to this root > + ResourceProducer, > + MinFixed, MaxFixed, PosDecode, > + 0, // AddressGranularity > + 0, // AddressMinimum - Minimum Bus Number > + 255, // AddressMaximum - Maximum Bus Number > + 0, // AddressTranslation - Set to 0 > + 256 // RangeLength - Number of Busses > + ) > + > + DWordMemory ( // 32-bit BAR Windows > + ResourceProducer, PosDecode, > + MinFixed, MaxFixed, > + Cacheable, ReadWrite, > + 0x00000000, // Granularity > + 0x80000000, // Min Base Address > + 0xEFFFFFFF, // Max Base Address > + 0x00000000, // Translate > + 0x70000000 // Length > + ) > + > + QWordMemory ( // 64-bit BAR Windows > + ResourceProducer, PosDecode, > + MinFixed, MaxFixed, > + Cacheable, ReadWrite, > + 0x00000000, // Granularity > + 0x100000000, // Min Base Address > + 0xFFFFFFFFFF, // Max Base Address > + 0x00000000, // Translate > + 0xFF00000000 // Length Plese clean up horizontal alignment of comments. / Leif > + ) > + > + DWordIo ( // IO window > + ResourceProducer, > + MinFixed, > + MaxFixed, > + PosDecode, > + EntireRange, > + 0x00000000, // Granularity > + 0x00000000, // Min Base Address > + 0x0000ffff, // Max Base Address > + 0x7fff0000, // Translate > + 0x00010000, // Length > + ,,,TypeTranslation > + ) > + }) // Name(RBUF) > + > + Return (RBUF) > + } // Method(_CRS) > + > + Device (RES0) > + { > + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID > + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > + { > + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, > + 0x0000000000000000, // Granularity > + 0x00000000F0000000, // Range Minimum > + 0x00000000FFFFFFFF, // Range Maximum > + 0x0000000000000000, // Translation Offset > + 0x0000000010000000, // Length > + ,, , AddressRangeMemory, TypeStatic) > + }) > + } > + > + // OS Control Handoff > + Name (SUPP, Zero) // PCI _OSC Support Field value > + Name (CTRL, Zero) // PCI _OSC Control Field value > + > + /* > + * See [1] 6.2.10, [2] 4.5 > + */ > + Method (_OSC,4) { > + // Check for proper UUID > + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + // Create DWord-adressable fields from the Capabilities Buffer > + CreateDWordField (Arg3,0,CDW1) > + CreateDWordField (Arg3,4,CDW2) > + CreateDWordField (Arg3,8,CDW3) > + > + // Save Capabilities DWord2 & 3 > + Store (CDW2,SUPP) > + Store (CDW3,CTRL) > + > + // Only allow native hot plug control if OS supports: > + // * ASPM > + // * Clock PM > + // * MSI/MSI-X > + If (LNotEqual(And(SUPP, 0x16), 0x16)) { > + And (CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) > + } > + > + // Always allow native PME, AER (no dependencies) > + > + // Never allow SHPC (no SHPC controller in this system) > + And (CTRL,0x1D,CTRL) > + > + If (LNotEqual(Arg1,One)) { // Unknown revision > + Or (CDW1,0x08,CDW1) > + } > + > + If (LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked > + Or (CDW1,0x10,CDW1) > + } > + > + // Update DWORD3 in the buffer > + Store (CTRL,CDW3) > + Return (Arg3) > + } Else { > + Or (CDW1,4,CDW1) // Unrecognized UUID > + Return (Arg3) > + } > + } // End _OSC > + } > } // Scope (_SB) > } > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc > new file mode 100644 > index 000000000000..e78061f9fe1c > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc > @@ -0,0 +1,43 @@ > +/** @file > +* ACPI Memory mapped configuration space base address Description Table (MCFG). > +* > +* Copyright (c) 2020, Linaro Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > + > +#pragma pack(push, 1) > + > +typedef struct { > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; > + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2]; > +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; > + > +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { > + { > + SBSAQEMU_ACPI_HEADER ( > + EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), > + EFI_ACPI_RESERVED_QWORD > + }, > + { > + { > + SBSAQEMU_PCI_SEG0_CONFIG_BASE, > + 0, > + SBSAQEMU_PCI_SEG0_BUSNUM_MIN, > + SBSAQEMU_PCI_SEG0_BUSNUM_MAX, > + EFI_ACPI_RESERVED_DWORD > + } > + } > +}; > + > +#pragma pack(pop) > + > +// Reference the table being generated to prevent the optimizer > +// from removing the data structure from the executable > +VOID* CONST ReferenceAcpiTable = &Mcfg; > -- > 2.28.0 >