From: "Leif Lindholm" <leif@nuviainc.com>
To: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Cc: graeme@nuviainc.com, shashi.mallela@linaro.org,
devel@edk2.groups.io, paul.isaacs@linaro.org, tanmay@marvell.com
Subject: Re: [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT table at runtime
Date: Thu, 20 Aug 2020 13:12:14 +0100 [thread overview]
Message-ID: <20200820121214.GG1191@vanye> (raw)
In-Reply-To: <20200819143005.13999-7-tanmay.jagdale@linaro.org>
On Wed, Aug 19, 2020 at 20:00:04 +0530, Tanmay Jagdale wrote:
> Add support to create Processor Properties Topology Table at
> runtime. The cache topology of each CPU is as follows:
>
> CPU N
> ------------------------
> | -------- -------- |
> | | L1-I | | L1-D | |
> | | 32KB | | 32KB | |
> | -------- -------- |
> | ------------------ |
> | | L2 512KB | |
> | ------------------ |
> ------------------------
>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 111 ++++++++++++++++
> .../Include/IndustryStandard/SbsaQemuAcpi.h | 124 ++++++++++++++++++
> 2 files changed, 235 insertions(+)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index d90ce0c2a718..8527b976ee33 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -9,6 +9,7 @@
> #include <IndustryStandard/Acpi.h>
> #include <IndustryStandard/Acpi10.h>
> #include <IndustryStandard/Acpi60.h>
> +#include <IndustryStandard/Acpi63.h>
So, if your edk2 tree is newer than Wed May 15 2020, this will
automatically be pulled in by Acpi.h.
/
Leif
> #include <IndustryStandard/AcpiAml.h>
> #include <IndustryStandard/SbsaQemuAcpi.h>
> #include <Library/AcpiLib.h>
> @@ -341,6 +342,111 @@ AddSsdtTable (
> return Status;
> }
>
> +/*
> + * A function that adds the SSDT ACPI table.
> + */
> +EFI_STATUS
> +AddPpttTable (
> + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> + )
> +{
> + EFI_STATUS Status;
> + UINTN TableHandle;
> + UINT32 TableSize;
> + EFI_PHYSICAL_ADDRESS PageAddress;
> + UINT8 *New;
> + UINT32 CpuId;
> + UINT32 NumCores = PcdGet32 (PcdCoreCount);
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT;
> +
> + EFI_ACPI_DESCRIPTION_HEADER Header =
> + SBSAQEMU_ACPI_HEADER (
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_DESCRIPTION_HEADER,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION);
> +
> + TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) +
> + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) +
> + (sizeof (UINT32) * 2 * NumCores);
> +
> + Status = gBS->AllocatePages (
> + AllocateAnyPages,
> + EfiACPIReclaimMemory,
> + EFI_SIZE_TO_PAGES (TableSize),
> + &PageAddress
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "Failed to allocate pages for PPTT table\n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + New = (UINT8 *)(UINTN) PageAddress;
> + ZeroMem (New, TableSize);
> +
> + // Add the ACPI Description table header
> + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
> + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
> + New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> +
> + // Add the Cluster PPTT structure
> + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> +
> + // Add L1 D Cache structure
> + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX;
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + // Add L1 I Cache structure
> + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX;
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + // Add L2 Cache structure
> + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
> + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = 0; /* L2 is LLC */
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
> +
> + for (CpuId = 0; CpuId < NumCores; CpuId++) {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr;
> + UINT32 *PrivateResourcePtr;
> +
> + CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
> + CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New;
> + CorePtr->Parent = CLUSTER_INDEX;
> + CorePtr->AcpiProcessorId = CpuId;
> + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
> +
> + PrivateResourcePtr = (UINT32 *) New;
> + PrivateResourcePtr[0] = L1_D_CACHE_INDEX;
> + PrivateResourcePtr[1] = L1_I_CACHE_INDEX;
> + New += (2 * sizeof (UINT32));
> + }
> +
> + // Perform Checksum
> + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
> +
> + Status = AcpiTable->InstallAcpiTable (
> + AcpiTable,
> + (EFI_ACPI_COMMON_HEADER *)PageAddress,
> + TableSize,
> + &TableHandle
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG((EFI_D_ERROR, "Failed to install PPTT table\n"));
> + }
> +
> + return Status;
> +}
> +
> EFI_STATUS
> EFIAPI
> InitializeSbsaQemuAcpiDxe (
> @@ -375,5 +481,10 @@ InitializeSbsaQemuAcpiDxe (
> DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n"));
> }
>
> + Status = AddPpttTable (AcpiTable);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((EFI_D_ERROR, "Failed to add PPTT table\n"));
> + }
> +
> return EFI_SUCCESS;
> }
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> index 60acc083ddbb..95cfca4727a6 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -72,4 +72,128 @@ typedef struct {
> UINT8 uid[8];
> } SBSAQEMU_ACPI_CPU_DEVICE;
>
> +#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB
> +#define SBSAQEMU_L1_D_CACHE_SETS 256
> +#define SBSAQEMU_L1_D_CACHE_ASSC 2
> +
> +#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB
> +#define SBSAQEMU_L1_I_CACHE_SETS 256
> +#define SBSAQEMU_L1_I_CACHE_ASSC 2
> +
> +#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB
> +#define SBSAQEMU_L2_CACHE_SETS 1024
> +#define SBSAQEMU_L2_CACHE_ASSC 8
> +
> +#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
> +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
> +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
> +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
> +
> +#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + 1, /* SizePropertyValid */ \
> + 1, /* NumberOfSetsValid */ \
> + 1, /* AssociativityValid */ \
> + 1, /* AllocationTypeValid */ \
> + 1, /* CacheTypeValid */ \
> + 1, /* WritePolicyValid */ \
> + 1, /* LineSizeValid */ \
> + }, \
> + 0, /* NextLevelOfCache */ \
> + SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
> + SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
> + SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
> + { \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
> + }, \
> + 64 /* LineSize */ \
> + }
> +
> +#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + 1, /* SizePropertyValid */ \
> + 1, /* NumberOfSetsValid */ \
> + 1, /* AssociativityValid */ \
> + 1, /* AllocationTypeValid */ \
> + 1, /* CacheTypeValid */ \
> + 0, /* WritePolicyValid */ \
> + 1, /* LineSizeValid */ \
> + }, \
> + 0, /* NextLevelOfCache */ \
> + SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
> + SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
> + SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
> + { \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
> + 0, \
> + }, \
> + 64 /* LineSize */ \
> + }
> +
> +#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + 1, /* SizePropertyValid */ \
> + 1, /* NumberOfSetsValid */ \
> + 1, /* AssociativityValid */ \
> + 1, /* AllocationTypeValid */ \
> + 1, /* CacheTypeValid */ \
> + 1, /* WritePolicyValid */ \
> + 1, /* LineSizeValid */ \
> + }, \
> + 0, /* NextLevelOfCache */ \
> + SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
> + SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
> + SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
> + { \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
> + }, \
> + 64 /* LineSize */ \
> + }
> +
> +#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
> + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
> + }, \
> + 0, /* Parent */ \
> + 0, /* AcpiProcessorId */ \
> + 0, /* NumberOfPrivateResources */ \
> + }
> +
> +#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \
> + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
> + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
> + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
> + }, \
> + 0, /* Parent */ \
> + 0, /* AcpiProcessorId */ \
> + 2, /* NumberOfPrivateResources */ \
> + }
> +
> #endif
> --
> 2.28.0
>
next prev parent reply other threads:[~2020-08-20 12:12 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-19 14:29 [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Tanmay Jagdale
2020-08-19 14:29 ` [PATCH edk2-platforms 1/7] SbsaQemu: Initial support for static ACPI tables Tanmay Jagdale
2020-08-20 11:35 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Tanmay Jagdale
2020-08-20 11:40 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 3/7] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs Tanmay Jagdale
2020-08-20 11:46 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 4/7] SbsaQemu: AcpiDxe: Create MADT table at runtime Tanmay Jagdale
2020-08-20 12:02 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 5/7] SbsaQemu: AcpiDxe: Create SSDT " Tanmay Jagdale
2020-08-20 12:09 ` Leif Lindholm
2020-08-19 14:30 ` [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT " Tanmay Jagdale
2020-08-20 12:12 ` Leif Lindholm [this message]
2020-08-19 14:30 ` [PATCH edk2-platforms 7/7] SbsaQemu: AcpiTables: Add DBG2 Table Tanmay Jagdale
2020-08-20 12:13 ` Leif Lindholm
2020-08-20 12:15 ` [PATCH edk2-platforms 0/7] Add ACPI tables support for SbsaQemu Leif Lindholm
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