From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by mx.groups.io with SMTP id smtpd.web12.108442.1597925538242129723 for ; Thu, 20 Aug 2020 05:12:18 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=m+TYvvxV; spf=pass (domain: nuviainc.com, ip: 209.85.128.68, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f68.google.com with SMTP id p14so1380736wmg.1 for ; Thu, 20 Aug 2020 05:12:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=+tvklHPYnK6sCCGc2QJxc0ZP3TC/CvD80elIDDVFQMo=; b=m+TYvvxVDfWJXMRCb1nq/gwsmlWQjAMRljNRgn77+E+WE/QswN0scPgmLPE6KEsZqC fD/W9QkwZkTV1ae/XU4FlD/i1Q4Ixpu7RXXE0ocJ1N4olFyLrwCVgoXG9Kvc+1yLJ2lb 0UmzPNdybWP5sGskDeAwNYTCqYwqgD5lQmiRl9yK337kD/o66J17MlA1O5ESa0Cg+vx8 qz5yw2u2QA81JRDtw/pvY5CkWgfET/7e1ITnVQdenrzKNbIV226AFigxm2XJAprGltAP glhQsqne97OytGJeu0Y8W86l4g4cKncaTx9UridBFuufZFR51ilT2UaX7Jlw8PY7nCPq 7DrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=+tvklHPYnK6sCCGc2QJxc0ZP3TC/CvD80elIDDVFQMo=; b=h7a14ZQMRM7pSKQXyuOj8fnggvGLFVn2h+lx6Lf5SZjM0Wj3s1AInOpih6x05Txf1/ yFIU4uxx+OailZeh+Mr462+oQ50ZB5M7j7m9ScJ/t1JpsxmGgjP4CzclO/QbwnRgZJuj Eo4gK3IVKUClWV02aqy0S0dnLldW+n0gk/PpmRyhMmP55P25lrwddcWiHNJuwzKqvnaF Ddlp7FpEXE3eFt2QDZWzI0ZkLasZ+2fk+mnsuD8ofQ2oP3/llJMGCkRbPUUiiceB3PcO 4J/ZcKUaxWyT7oPmYXFeANeOPrLi1Fc6cPR6Uw9awzyPhbr8O6uUaa2D3HWTe/nr/AsS ZLcw== X-Gm-Message-State: AOAM533HqczvJA1zR1t0+DFa8u5QvO7OGmLOx/7Sea407xhjnspn9q4b LWo/mpZJSHolZzPMHfovbnp7pw== X-Google-Smtp-Source: ABdhPJzPXibE/3kAsSmO2txe+2/x13f5VmQJ6RUYwrAvi9FOjYEziN7jQV2wU+2JTsyw+xTTyXgFJQ== X-Received: by 2002:a1c:28d5:: with SMTP id o204mr3426048wmo.104.1597925536675; Thu, 20 Aug 2020 05:12:16 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id k1sm4114905wrw.91.2020.08.20.05.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2020 05:12:16 -0700 (PDT) Date: Thu, 20 Aug 2020 13:12:14 +0100 From: "Leif Lindholm" To: Tanmay Jagdale Cc: graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io, paul.isaacs@linaro.org, tanmay@marvell.com Subject: Re: [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT table at runtime Message-ID: <20200820121214.GG1191@vanye> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> <20200819143005.13999-7-tanmay.jagdale@linaro.org> MIME-Version: 1.0 In-Reply-To: <20200819143005.13999-7-tanmay.jagdale@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Aug 19, 2020 at 20:00:04 +0530, Tanmay Jagdale wrote: > Add support to create Processor Properties Topology Table at > runtime. The cache topology of each CPU is as follows: > > CPU N > ------------------------ > | -------- -------- | > | | L1-I | | L1-D | | > | | 32KB | | 32KB | | > | -------- -------- | > | ------------------ | > | | L2 512KB | | > | ------------------ | > ------------------------ > > Signed-off-by: Tanmay Jagdale > --- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 111 ++++++++++++++++ > .../Include/IndustryStandard/SbsaQemuAcpi.h | 124 ++++++++++++++++++ > 2 files changed, 235 insertions(+) > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > index d90ce0c2a718..8527b976ee33 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include So, if your edk2 tree is newer than Wed May 15 2020, this will automatically be pulled in by Acpi.h. / Leif > #include > #include > #include > @@ -341,6 +342,111 @@ AddSsdtTable ( > return Status; > } > > +/* > + * A function that adds the SSDT ACPI table. > + */ > +EFI_STATUS > +AddPpttTable ( > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > + ) > +{ > + EFI_STATUS Status; > + UINTN TableHandle; > + UINT32 TableSize; > + EFI_PHYSICAL_ADDRESS PageAddress; > + UINT8 *New; > + UINT32 CpuId; > + UINT32 NumCores = PcdGet32 (PcdCoreCount); > + > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT; > + > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT; > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT; > + > + EFI_ACPI_DESCRIPTION_HEADER Header = > + SBSAQEMU_ACPI_HEADER ( > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, > + EFI_ACPI_DESCRIPTION_HEADER, > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION); > + > + TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) + > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + > + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) + > + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) + > + (sizeof (UINT32) * 2 * NumCores); > + > + Status = gBS->AllocatePages ( > + AllocateAnyPages, > + EfiACPIReclaimMemory, > + EFI_SIZE_TO_PAGES (TableSize), > + &PageAddress > + ); > + if (EFI_ERROR(Status)) { > + DEBUG((EFI_D_ERROR, "Failed to allocate pages for PPTT table\n")); > + return EFI_OUT_OF_RESOURCES; > + } > + > + New = (UINT8 *)(UINTN) PageAddress; > + ZeroMem (New, TableSize); > + > + // Add the ACPI Description table header > + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER)); > + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize; > + New += sizeof (EFI_ACPI_DESCRIPTION_HEADER); > + > + // Add the Cluster PPTT structure > + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); > + > + // Add L1 D Cache structure > + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); > + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX; > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > + > + // Add L1 I Cache structure > + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); > + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX; > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > + > + // Add L2 Cache structure > + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); > + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = 0; /* L2 is LLC */ > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > + > + for (CpuId = 0; CpuId < NumCores; CpuId++) { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr; > + UINT32 *PrivateResourcePtr; > + > + CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); > + CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New; > + CorePtr->Parent = CLUSTER_INDEX; > + CorePtr->AcpiProcessorId = CpuId; > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); > + > + PrivateResourcePtr = (UINT32 *) New; > + PrivateResourcePtr[0] = L1_D_CACHE_INDEX; > + PrivateResourcePtr[1] = L1_I_CACHE_INDEX; > + New += (2 * sizeof (UINT32)); > + } > + > + // Perform Checksum > + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > + > + Status = AcpiTable->InstallAcpiTable ( > + AcpiTable, > + (EFI_ACPI_COMMON_HEADER *)PageAddress, > + TableSize, > + &TableHandle > + ); > + if (EFI_ERROR(Status)) { > + DEBUG((EFI_D_ERROR, "Failed to install PPTT table\n")); > + } > + > + return Status; > +} > + > EFI_STATUS > EFIAPI > InitializeSbsaQemuAcpiDxe ( > @@ -375,5 +481,10 @@ InitializeSbsaQemuAcpiDxe ( > DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n")); > } > > + Status = AddPpttTable (AcpiTable); > + if (EFI_ERROR (Status)) { > + DEBUG ((EFI_D_ERROR, "Failed to add PPTT table\n")); > + } > + > return EFI_SUCCESS; > } > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > index 60acc083ddbb..95cfca4727a6 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > @@ -72,4 +72,128 @@ typedef struct { > UINT8 uid[8]; > } SBSAQEMU_ACPI_CPU_DEVICE; > > +#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB > +#define SBSAQEMU_L1_D_CACHE_SETS 256 > +#define SBSAQEMU_L1_D_CACHE_ASSC 2 > + > +#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB > +#define SBSAQEMU_L1_I_CACHE_SETS 256 > +#define SBSAQEMU_L1_I_CACHE_ASSC 2 > + > +#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB > +#define SBSAQEMU_L2_CACHE_SETS 1024 > +#define SBSAQEMU_L2_CACHE_ASSC 8 > + > +#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) > +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)) > +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)) > +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)) > + > +#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \ > + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ > + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 1, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \ > + SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \ > + SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \ > + { \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + } > + > +#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \ > + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ > + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 1, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 0, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \ > + SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \ > + SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \ > + { \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ > + 0, \ > + }, \ > + 64 /* LineSize */ \ > + } > + > +#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { \ > + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ > + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 1, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + SBSAQEMU_L2_CACHE_SIZE, /* Size */ \ > + SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \ > + SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \ > + { \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + } > + > +#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \ > + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \ > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \ > + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \ > + { \ > + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \ > + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \ > + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \ > + }, \ > + 0, /* Parent */ \ > + 0, /* AcpiProcessorId */ \ > + 0, /* NumberOfPrivateResources */ \ > + } > + > +#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \ > + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \ > + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \ > + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \ > + { \ > + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \ > + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \ > + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \ > + }, \ > + 0, /* Parent */ \ > + 0, /* AcpiProcessorId */ \ > + 2, /* NumberOfPrivateResources */ \ > + } > + > #endif > -- > 2.28.0 >