* [PATCH v3 edk2-platforms 1/8] SbsaQemu: Initial support for static ACPI tables
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
@ 2020-08-25 13:39 ` Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 2/8] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Tanmay Jagdale
` (7 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-25 13:39 UTC (permalink / raw)
To: leif, graeme, devel
Cc: shashi.mallela, Tanmay Jagdale, Graeme Gregory, Jonathan Cameron
- Add the following ACPI tables for SbsaQemu platform
DSDT, FADT, GTDT, SPCR
- Created an Include directory to hold common header files.
- Also included the Acpiview shell utility.
Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Co-authored-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 +-
Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 35 ++++++
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 8 ++
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 45 +++++++
Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 31 +++++
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 133 ++++++++++++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 80 ++++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 67 ++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 53 ++++++++
10 files changed, 460 insertions(+), 2 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index cd879f4dbd96..71ba55a082e2 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -21,8 +21,8 @@ [Defines]
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
-#[Includes.common]
-# Include # Root include for the package
+[Includes]
+ Include # Root include for the package
[Guids.common]
gArmVirtSbsaQemuPlatformTokenSpaceGuid = { 0xaab3bea9, 0xa8e8, 0x4e76, { 0xb5, 0x3a, 0x35, 0x22, 0x11, 0xce, 0xf7, 0xf7 } }
diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
new file mode 100644
index 000000000000..c4a8d7a27b78
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2020, Linaro Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LINARO"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x554D455141534253 #SBSAQEMU
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20200810
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c #LNRO
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+
+[Components.common]
+ #
+ # ACPI support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 4db3ab465163..4739443cae93 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -516,6 +516,7 @@ [Components.common]
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
@@ -675,3 +676,8 @@ [Components.common]
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # ACPI Support
+!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
+ MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
index be7c78acebfd..4526eaaa02c5 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
@@ -227,6 +227,14 @@ [FV.FvMain]
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ #
+ # ACPI support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+ INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+
#
# PCI support
#
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000000..ee524895524e
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -0,0 +1,45 @@
+## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2020, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SbsaAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
new file mode 100644
index 000000000000..eac195b0585c
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -0,0 +1,31 @@
+/** @file
+*
+* Copyright (c) 2020, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef SBSAQEMUACPI_H
+#define SBSAQEMUACPI_H
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define SBSAQEMU_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { 'L', 'I', 'N', 'A', 'R', 'O' }, /* UINT8 OemId[6] */ \
+ FixedPcdGet64 (PcdAcpiDefaultOemTableId), /* UINT64 OemTableId */ \
+ FixedPcdGet32 (PcdAcpiDefaultOemRevision), /* UINT32 OemRevision */ \
+ FixedPcdGet32 (PcdAcpiDefaultCreatorId), /* UINT32 CreatorId */ \
+ FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \
+ }
+
+#define SBSAQEMU_UART0_BASE 0x60000000
+
+#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
+#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00
+#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF
+
+#endif
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
new file mode 100644
index 000000000000..85339d4559d3
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -0,0 +1,133 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT).
+*
+* Copyright (c) 2020, Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <IndustryStandard/SbsaQemuAcpi.h>
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
+ FixedPcdGet32 (PcdAcpiDefaultOemRevision)) {
+ Scope (_SB) {
+ // UART PL011
+ Device (COM0) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, Zero)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x60000000, 0x00001000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
+ })
+ }
+
+ // AHCI Host Controller
+ Device (AHC0) {
+ Name (_HID, "LNRO001E")
+ Name (_CLS, Package (3) {
+ 0x01,
+ 0x06,
+ 0x01,
+ })
+ Name (_CCA, 1)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, 0x60100000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
+ })
+ }
+
+ // USB EHCI Host Controller
+ Device (USB0) {
+ Name (_HID, "LNRO0D20")
+ Name (_CID, "PNP0D20")
+
+ Method (_CRS, 0x0, Serialized) {
+ Name (RBUF, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, 0x60110000, 0x00010000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
+ })
+ Return (RBUF)
+ }
+
+ // Root Hub
+ Device (RHUB) {
+ Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec
+
+ // Ports connected to Root Hub
+ Device (HUB1) {
+ Name (_ADR, 0x00000001)
+ Name (_UPC, Package() {
+ 0x00, // Port is NOT connectable
+ 0xFF, // Don't care
+ 0x00000000, // Reserved 0 must be zero
+ 0x00000000 // Reserved 1 must be zero
+ })
+
+ Device (PRT1) {
+ Name (_ADR, 0x00000001)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer(0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT1
+ Device (PRT2) {
+ Name (_ADR, 0x00000002)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer(0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT2
+
+ Device (PRT3) {
+ Name (_ADR, 0x00000003)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer (0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT3
+
+ Device (PRT4) {
+ Name (_ADR, 0x00000004)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer (0x10){
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT4
+ } // USB0_RHUB_HUB1
+ } // USB0_RHUB
+ } // USB0
+
+ } // Scope (_SB)
+}
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
new file mode 100644
index 000000000000..894b848db8bb
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
@@ -0,0 +1,80 @@
+/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2020, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_0_HW_REDUCED_ACPI |
+ EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // GAS ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
+ // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // GAS XPm1aEvtBlk
+ NULL_GAS, // GAS XPm1bEvtBlk
+ NULL_GAS, // GAS XPm1aCntBlk
+ NULL_GAS, // GAS XPm1bCntBlk
+ NULL_GAS, // GAS XPm2CntBlk
+ NULL_GAS, // GAS XPmTmrBlk
+ NULL_GAS, // GAS XGpe0Blk
+ NULL_GAS, // GAS XGpe1Blk
+ NULL_GAS, // GAS SleepControlReg
+ NULL_GAS, // GAS SleepStatusReg
+ 0 // UINT64 HypervisorVendorId
+};
+
+// Reference the table being generated to prevent the optimizer
+// from removing the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
new file mode 100644
index 000000000000..52496acc449b
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
@@ -0,0 +1,67 @@
+/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyrignt (c) 2020, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+ #pragma pack (1)
+
+ typedef struct {
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ } GENERIC_TIMER_DESCRIPTION_TABLE;
+
+ #pragma pack ()
+
+ GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
+ {
+ SBSAQEMU_ACPI_HEADER(
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ GENERIC_TIMER_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+ 0, // UINT32 PlatformTimerCount
+ 0
+ },
+ };
+
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
new file mode 100644
index 000000000000..7498fd8c0a98
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
@@ -0,0 +1,53 @@
+/** @file
+* Serial Port Console Redirection Table (SPCR).
+*
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ 2), /* New MS definition for PL011 support */
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
+ {
+ EFI_ACPI_6_0_SYSTEM_MEMORY,
+ 32,
+ 0,
+ EFI_ACPI_6_0_DWORD,
+ SBSAQEMU_UART0_BASE
+ },
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+ 0, /* Irq */
+ 33, /* GlobalSystemInterrupt */
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ 0, /* Flow Control */
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ EFI_ACPI_RESERVED_BYTE, /* Language */
+ 0xFFFF, /* PciDeviceId */
+ 0xFFFF, /* PciVendorId */
+ 0x00, /* PciBusNumber */
+ 0x00, /* PciDeviceNumber */
+ 0x00, /* PciFunctionNumber */
+ 0, /* PciFlags */
+ 0, /* PciSegment */
+ EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Spcr;
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 edk2-platforms 2/8] SbsaQemu: AcpiTables: Add PCI support and MCFG Table
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 1/8] SbsaQemu: Initial support for static ACPI tables Tanmay Jagdale
@ 2020-08-25 13:39 ` Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 3/8] SbsaQemu: SbsaQemu.dsc: Move CoreCount and Fdtlib Tanmay Jagdale
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-25 13:39 UTC (permalink / raw)
To: leif, graeme, devel; +Cc: shashi.mallela, Tanmay Jagdale, Graeme Gregory
Add PCI related entries to DSDT table along with the routing
entries. Also add the MCFG table.
Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 316 ++++++++++++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 +++
3 files changed, 360 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index ee524895524e..57d717fefafc 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -19,6 +19,7 @@ [Sources]
Dsdt.asl
Fadt.aslc
Gtdt.aslc
+ Mcfg.aslc
Spcr.aslc
[Packages]
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index 85339d4559d3..d9ca2f69dc9c 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -8,6 +8,23 @@
#include <IndustryStandard/SbsaQemuAcpi.h>
+#define LINK_DEVICE(Uid, LinkName, Irq) \
+ Device (LinkName) { \
+ Name (_HID, EISAID("PNP0C0F")) \
+ Name (_UID, Uid) \
+ Name (_PRS, ResourceTemplate() { \
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, Pin, Link, Zero \
+ }
+
DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
FixedPcdGet32 (PcdAcpiDefaultOemRevision)) {
Scope (_SB) {
@@ -129,5 +146,304 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
} // USB0_RHUB
} // USB0
+ Device (PCI0)
+ {
+ Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_ADR, Zero)
+ Name (_UID, "PCI0")
+ Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1)
+
+ Method (_CBA, 0, NotSerialized) {
+ return (0xf0000000)
+ }
+
+ LINK_DEVICE(0, GSI0, 0x23)
+ LINK_DEVICE(1, GSI1, 0x24)
+ LINK_DEVICE(2, GSI2, 0x25)
+ LINK_DEVICE(3, GSI3, 0x26)
+
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ PRT_ENTRY(0x0000FFFF, 0, GSI0),
+ PRT_ENTRY(0x0000FFFF, 0, GSI1),
+ PRT_ENTRY(0x0000FFFF, 0, GSI2),
+ PRT_ENTRY(0x0000FFFF, 0, GSI3),
+
+ PRT_ENTRY(0x0001FFFF, 0, GSI1),
+ PRT_ENTRY(0x0001FFFF, 1, GSI2),
+ PRT_ENTRY(0x0001FFFF, 2, GSI3),
+ PRT_ENTRY(0x0001FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0002FFFF, 0, GSI2),
+ PRT_ENTRY(0x0002FFFF, 1, GSI3),
+ PRT_ENTRY(0x0002FFFF, 2, GSI0),
+ PRT_ENTRY(0x0002FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0003FFFF, 0, GSI3),
+ PRT_ENTRY(0x0003FFFF, 1, GSI0),
+ PRT_ENTRY(0x0003FFFF, 2, GSI1),
+ PRT_ENTRY(0x0003FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0004FFFF, 0, GSI0),
+ PRT_ENTRY(0x0004FFFF, 1, GSI1),
+ PRT_ENTRY(0x0004FFFF, 2, GSI2),
+ PRT_ENTRY(0x0004FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0005FFFF, 0, GSI1),
+ PRT_ENTRY(0x0005FFFF, 1, GSI2),
+ PRT_ENTRY(0x0005FFFF, 2, GSI3),
+ PRT_ENTRY(0x0005FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0006FFFF, 0, GSI2),
+ PRT_ENTRY(0x0006FFFF, 1, GSI3),
+ PRT_ENTRY(0x0006FFFF, 2, GSI0),
+ PRT_ENTRY(0x0006FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0007FFFF, 0, GSI3),
+ PRT_ENTRY(0x0007FFFF, 1, GSI0),
+ PRT_ENTRY(0x0007FFFF, 2, GSI1),
+ PRT_ENTRY(0x0007FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0008FFFF, 0, GSI0),
+ PRT_ENTRY(0x0008FFFF, 1, GSI1),
+ PRT_ENTRY(0x0008FFFF, 2, GSI2),
+ PRT_ENTRY(0x0008FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0009FFFF, 0, GSI1),
+ PRT_ENTRY(0x0009FFFF, 1, GSI2),
+ PRT_ENTRY(0x0009FFFF, 2, GSI3),
+ PRT_ENTRY(0x0009FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x000AFFFF, 0, GSI2),
+ PRT_ENTRY(0x000AFFFF, 1, GSI3),
+ PRT_ENTRY(0x000AFFFF, 2, GSI0),
+ PRT_ENTRY(0x000AFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x000BFFFF, 0, GSI3),
+ PRT_ENTRY(0x000BFFFF, 1, GSI0),
+ PRT_ENTRY(0x000BFFFF, 2, GSI1),
+ PRT_ENTRY(0x000BFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x000CFFFF, 0, GSI0),
+ PRT_ENTRY(0x000CFFFF, 1, GSI1),
+ PRT_ENTRY(0x000CFFFF, 2, GSI2),
+ PRT_ENTRY(0x000CFFFF, 3, GSI3),
+
+ PRT_ENTRY(0x000DFFFF, 0, GSI1),
+ PRT_ENTRY(0x000DFFFF, 1, GSI2),
+ PRT_ENTRY(0x000DFFFF, 2, GSI3),
+ PRT_ENTRY(0x000DFFFF, 3, GSI0),
+
+ PRT_ENTRY(0x000EFFFF, 0, GSI2),
+ PRT_ENTRY(0x000EFFFF, 1, GSI3),
+ PRT_ENTRY(0x000EFFFF, 2, GSI0),
+ PRT_ENTRY(0x000EFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x000FFFFF, 0, GSI3),
+ PRT_ENTRY(0x000FFFFF, 1, GSI0),
+ PRT_ENTRY(0x000FFFFF, 2, GSI1),
+ PRT_ENTRY(0x000FFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0010FFFF, 0, GSI0),
+ PRT_ENTRY(0x0010FFFF, 1, GSI1),
+ PRT_ENTRY(0x0010FFFF, 2, GSI2),
+ PRT_ENTRY(0x0010FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0011FFFF, 0, GSI1),
+ PRT_ENTRY(0x0011FFFF, 1, GSI2),
+ PRT_ENTRY(0x0011FFFF, 2, GSI3),
+ PRT_ENTRY(0x0011FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0012FFFF, 0, GSI2),
+ PRT_ENTRY(0x0012FFFF, 1, GSI3),
+ PRT_ENTRY(0x0012FFFF, 2, GSI0),
+ PRT_ENTRY(0x0012FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0013FFFF, 0, GSI3),
+ PRT_ENTRY(0x0013FFFF, 1, GSI0),
+ PRT_ENTRY(0x0013FFFF, 2, GSI1),
+ PRT_ENTRY(0x0013FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0014FFFF, 0, GSI0),
+ PRT_ENTRY(0x0014FFFF, 1, GSI1),
+ PRT_ENTRY(0x0014FFFF, 2, GSI2),
+ PRT_ENTRY(0x0014FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0015FFFF, 0, GSI1),
+ PRT_ENTRY(0x0015FFFF, 1, GSI2),
+ PRT_ENTRY(0x0015FFFF, 2, GSI3),
+ PRT_ENTRY(0x0015FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0016FFFF, 0, GSI2),
+ PRT_ENTRY(0x0016FFFF, 1, GSI3),
+ PRT_ENTRY(0x0016FFFF, 2, GSI0),
+ PRT_ENTRY(0x0016FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0017FFFF, 0, GSI3),
+ PRT_ENTRY(0x0017FFFF, 1, GSI0),
+ PRT_ENTRY(0x0017FFFF, 2, GSI1),
+ PRT_ENTRY(0x0017FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0018FFFF, 0, GSI0),
+ PRT_ENTRY(0x0018FFFF, 1, GSI1),
+ PRT_ENTRY(0x0018FFFF, 2, GSI2),
+ PRT_ENTRY(0x0018FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0019FFFF, 0, GSI1),
+ PRT_ENTRY(0x0019FFFF, 1, GSI2),
+ PRT_ENTRY(0x0019FFFF, 2, GSI3),
+ PRT_ENTRY(0x0019FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x001AFFFF, 0, GSI2),
+ PRT_ENTRY(0x001AFFFF, 1, GSI3),
+ PRT_ENTRY(0x001AFFFF, 2, GSI0),
+ PRT_ENTRY(0x001AFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x001BFFFF, 0, GSI3),
+ PRT_ENTRY(0x001BFFFF, 1, GSI0),
+ PRT_ENTRY(0x001BFFFF, 2, GSI1),
+ PRT_ENTRY(0x001BFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x001CFFFF, 0, GSI0),
+ PRT_ENTRY(0x001CFFFF, 1, GSI1),
+ PRT_ENTRY(0x001CFFFF, 2, GSI2),
+ PRT_ENTRY(0x001CFFFF, 3, GSI3),
+
+ PRT_ENTRY(0x001DFFFF, 0, GSI1),
+ PRT_ENTRY(0x001DFFFF, 1, GSI2),
+ PRT_ENTRY(0x001DFFFF, 2, GSI3),
+ PRT_ENTRY(0x001DFFFF, 3, GSI0),
+
+ PRT_ENTRY(0x001EFFFF, 0, GSI2),
+ PRT_ENTRY(0x001EFFFF, 1, GSI3),
+ PRT_ENTRY(0x001EFFFF, 2, GSI0),
+ PRT_ENTRY(0x001EFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x001FFFFF, 0, GSI3),
+ PRT_ENTRY(0x001FFFFF, 1, GSI0),
+ PRT_ENTRY(0x001FFFFF, 2, GSI1),
+ PRT_ENTRY(0x001FFFFF, 3, GSI2),
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x80000000, // Min Base Address
+ 0xEFFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0x70000000 // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x100000000, // Min Base Address
+ 0xFFFFFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0xFF00000000 // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Min Base Address
+ 0x0000ffff, // Max Base Address
+ 0x7fff0000, // Translate
+ 0x00010000, // Length
+ ,,,TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x00000000F0000000, // Range Minimum
+ 0x00000000FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000010000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ }
+
+ // OS Control Handoff
+ Name (SUPP, Zero) // PCI _OSC Support Field value
+ Name (CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ * See [1] 6.2.10, [2] 4.5
+ */
+ Method (_OSC,4) {
+ // Check for proper UUID
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField (Arg3,0,CDW1)
+ CreateDWordField (Arg3,4,CDW2)
+ CreateDWordField (Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store (CDW2,SUPP)
+ Store (CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If (LNotEqual(And(SUPP, 0x16), 0x16)) {
+ And (CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ And (CTRL,0x1D,CTRL)
+
+ If (LNotEqual(Arg1,One)) { // Unknown revision
+ Or (CDW1,0x08,CDW1)
+ }
+
+ If (LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or (CDW1,0x10,CDW1)
+ }
+
+ // Update DWORD3 in the buffer
+ Store (CTRL,CDW3)
+ Return (Arg3)
+ } Else {
+ Or (CDW1,4,CDW1) // Unrecognized UUID
+ Return (Arg3)
+ }
+ } // End _OSC
+ }
} // Scope (_SB)
}
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
new file mode 100644
index 000000000000..5744884a4ad6
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
@@ -0,0 +1,43 @@
+/** @file
+* ACPI Memory mapped configuration space base address Description Table (MCFG).
+*
+* Copyright (c) 2020, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+
+#pragma pack(push, 1)
+
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
+ {
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD
+ },
+ {
+ {
+ SBSAQEMU_PCI_SEG0_CONFIG_BASE,
+ 0,
+ SBSAQEMU_PCI_SEG0_BUSNUM_MIN,
+ SBSAQEMU_PCI_SEG0_BUSNUM_MAX,
+ EFI_ACPI_RESERVED_DWORD
+ }
+ }
+};
+
+#pragma pack(pop)
+
+// Reference the table being generated to prevent the optimizer
+// from removing the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Mcfg;
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 edk2-platforms 3/8] SbsaQemu: SbsaQemu.dsc: Move CoreCount and Fdtlib
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 1/8] SbsaQemu: Initial support for static ACPI tables Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 2/8] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Tanmay Jagdale
@ 2020-08-25 13:39 ` Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 4/8] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs Tanmay Jagdale
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-25 13:39 UTC (permalink / raw)
To: leif, graeme, devel; +Cc: shashi.mallela, Tanmay Jagdale
- Since the core count is dynamic and controlled by Qemu, move the
PcdCoreCount from [PcdsFixedAtBuild] to [PcdsDynamic] section.
- Move FdtLib from [LibraryClasses.common.PEIM] to [LibraryClasses.common]
section so that driver DXEs can use the device tree APIs.
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 ++++
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 ++++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index 71ba55a082e2..ed87d15de003 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -35,3 +35,7 @@ [PcdsFixedAtBuild.common]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x00000003
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT32|0x00000004
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000|UINT64|0x00000005
+
+[PcdsDynamic.common]
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000006
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x00000007
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 4739443cae93..d42b9cd4de49 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -75,6 +75,7 @@ [LibraryClasses.common]
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
@@ -217,7 +218,6 @@ [LibraryClasses.common.PEIM]
PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
- FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
ArmPlatformLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf
[LibraryClasses.common.DXE_CORE]
@@ -376,7 +376,6 @@ [PcdsFixedAtBuild.common]
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
- gArmPlatformTokenSpaceGuid.PcdCoreCount|1
gArmTokenSpaceGuid.PcdVFPEnabled|1
# System Memory Base -- fixed
@@ -477,6 +476,9 @@ [PcdsFixedAtBuild.common]
[PcdsDynamicDefault.common]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+ # Core and Cluster Count
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|1
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|1
# System Memory Size -- 128 MB initially, actual size will be fetched from DT
# TODO as no DT will be used we should pass this by some other method
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 edk2-platforms 4/8] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (2 preceding siblings ...)
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 3/8] SbsaQemu: SbsaQemu.dsc: Move CoreCount and Fdtlib Tanmay Jagdale
@ 2020-08-25 13:39 ` Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime Tanmay Jagdale
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-25 13:39 UTC (permalink / raw)
To: leif, graeme, devel; +Cc: shashi.mallela, Tanmay Jagdale
- Add a new ACPI driver for the SbsaQemu platform which would
handle any modifications needed for the ACPI tables.
- Add a parser function in this driver which parses the FDT created
by Qemu to determine the number of CPUs and hence update the
PcdCoreCount variable.
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 1 +
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 49 +++++++++++++
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 75 ++++++++++++++++++++
4 files changed, 126 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
index c4a8d7a27b78..593670383750 100644
--- a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
+++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
@@ -33,3 +33,4 @@ [Components.common]
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
index 4526eaaa02c5..3bcf0bf0040a 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
@@ -232,6 +232,7 @@ [FV.FvMain]
#
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
new file mode 100644
index 000000000000..3795a7e11639
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -0,0 +1,49 @@
+## @file
+# This driver modifies ACPI tables for the Qemu SBSA platform
+#
+# Copyright (c) 2020, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001d
+ BASE_NAME = SbsaQemuAcpiDxe
+ FILE_GUID = 6c592dc9-76c8-474f-93b2-bf1e8f15ae35
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeSbsaQemuAcpiDxe
+
+[Sources]
+ SbsaQemuAcpiDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmVirtPkg/ArmVirtPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ DxeServicesLib
+ FdtLib
+ PcdLib
+ UefiDriverEntryPoint
+ UefiLib
+ UefiRuntimeServicesTableLib
+
+[Pcd]
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
+
+[Depex]
+ TRUE
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
new file mode 100644
index 000000000000..75abdae3b8ce
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -0,0 +1,75 @@
+/** @file
+* This file is an ACPI driver for the Qemu SBSA platform.
+*
+* Copyright (c) 2020, Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <Protocol/FdtClient.h>
+#include <libfdt.h>
+
+/*
+ * A function that walks through the Device Tree created
+ * by Qemu and counts the number of CPUs present in it.
+ */
+STATIC
+VOID
+CountCpusFromFdt (
+ VOID
+)
+{
+ VOID *DeviceTreeBase;
+ INT32 Node, Prev;
+ RETURN_STATUS PcdStatus;
+ INT32 CpuNode;
+ INT32 CpuCount;
+
+ DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress);
+ ASSERT (DeviceTreeBase != NULL);
+
+ // Make sure we have a valid device tree blob
+ ASSERT (fdt_check_header (DeviceTreeBase) == 0);
+
+ CpuNode = fdt_path_offset (DeviceTreeBase, "/cpus");
+ if (CpuNode <= 0) {
+ DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n"));
+ return;
+ }
+
+ CpuCount = 0;
+
+ // Walk through /cpus node and count the number of subnodes.
+ // The count of these subnodes corresponds to the number of
+ // CPUs created by Qemu.
+ Prev = fdt_first_subnode (DeviceTreeBase, CpuNode);
+ while (1) {
+ CpuCount++;
+ Node = fdt_next_subnode (DeviceTreeBase, Prev);
+ if (Node < 0) {
+ break;
+ }
+ Prev = Node;
+ }
+
+ PcdStatus = PcdSet32S (PcdCoreCount, CpuCount);
+ ASSERT_RETURN_ERROR (PcdStatus);
+}
+
+EFI_STATUS
+EFIAPI
+InitializeSbsaQemuAcpiDxe (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ // Parse the device tree and get the number of CPUs
+ CountCpusFromFdt ();
+
+ return EFI_SUCCESS;
+}
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (3 preceding siblings ...)
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 4/8] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs Tanmay Jagdale
@ 2020-08-25 13:39 ` Tanmay Jagdale
2020-08-26 15:35 ` graeme
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 6/8] SbsaQemu: AcpiDxe: Create SSDT " Tanmay Jagdale
` (3 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-25 13:39 UTC (permalink / raw)
To: leif, graeme, devel; +Cc: shashi.mallela, Tanmay Jagdale
- Add support to create MADT table at runtime.
- Included a macro for GIC Redistributor structure initialisation.
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++-
Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 156 ++++++++++++++++++++
3 files changed, 190 insertions(+), 1 deletion(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index 3795a7e11639..8125e8ba7553 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -41,9 +41,27 @@ [LibraryClasses]
UefiRuntimeServicesTableLib
[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
[Depex]
- TRUE
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+
+[Guids]
+ gEdkiiPlatformHasAcpiGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index eac195b0585c..7a9a0061675f 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -22,6 +22,21 @@
FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \
}
+// Defines for MADT
+#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
+#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
+#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
+#define SBSAQEMU_MADT_GICR_SIZE 0x4000000
+
+// Macro for MADT GIC Redistributor Structure
+#define SBSAQEMU_MADT_GICR_INIT() { \
+ EFI_ACPI_6_0_GICR, /* Type */ \
+ sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ \
+ EFI_ACPI_RESERVED_WORD, /* Reserved */ \
+ FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress */ \
+ SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ \
+ }
+
#define SBSAQEMU_UART0_BASE 0x60000000
#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 75abdae3b8ce..16cb4e904e6f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -6,11 +6,17 @@
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiLib.h>
+#include <Protocol/AcpiTable.h>
#include <Protocol/FdtClient.h>
#include <libfdt.h>
@@ -61,6 +67,137 @@ CountCpusFromFdt (
ASSERT_RETURN_ERROR (PcdStatus);
}
+/*
+ * A Function to Compute the ACPI Table Checksum
+ */
+VOID
+AcpiPlatformChecksum (
+ IN UINT8 *Buffer,
+ IN UINTN Size
+ )
+{
+ UINTN ChecksumOffset;
+
+ ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
+
+ // Set checksum field to 0 since it is used as part of the calculation
+ Buffer[ChecksumOffset] = 0;
+
+ Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
+}
+
+/*
+ * A function that add the MADT ACPI table.
+ IN EFI_ACPI_COMMON_HEADER *CurrentTable
+ */
+EFI_STATUS
+AddMadtTable (
+ IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN TableHandle;
+ UINT32 TableSize;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINT8 *New;
+ UINT32 NumCores;
+
+ // Initialize MADT ACPI Header
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = {
+ SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+ 0, 0 };
+
+ // Initialize GICC Structure
+ EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT (
+ 0, /* GicID */
+ 0, /* AcpiCpuUid */
+ 0, /* Mpidr */
+ EFI_ACPI_6_0_GIC_ENABLED, /* Flags */
+ SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */
+ FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */
+ SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */
+ SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */
+ 25, /* GsivId */
+ 0, /* GicRBase */
+ 0 /* Efficiency */
+ );
+
+ // Initialize GIC Distributor Structure
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (
+ 0,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0,
+ 3 /* GicVersion */
+ );
+
+ // Initialize GIC Redistributor Structure
+ EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
+
+ // Get CoreCount which was determined eariler after parsing device tree
+ NumCores = PcdGet32 (PcdCoreCount);
+
+ // Calculate the new table size based on the number of cores
+ TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
+ (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
+ sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
+ sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
+
+ Status = gBS->AllocatePages (
+ AllocateAnyPages,
+ EfiACPIReclaimMemory,
+ EFI_SIZE_TO_PAGES (TableSize),
+ &PageAddress
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MADT table\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ New = (UINT8 *)(UINTN) PageAddress;
+ ZeroMem (New, TableSize);
+
+ // Add the ACPI Description table header
+ CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
+ ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
+ New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
+
+ // Add new GICC structures for the Cores
+ for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) {
+ EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr;
+
+ CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
+ GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
+ GiccPtr->AcpiProcessorUid = NumCores;
+ GiccPtr->MPIDR = NumCores;
+ New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE);
+ }
+
+ // GIC Distributor Structure
+ CopyMem (New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE));
+ New += sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE);
+
+ // GIC ReDistributor Structure
+ CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE));
+ New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
+
+ AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ (EFI_ACPI_COMMON_HEADER *)PageAddress,
+ TableSize,
+ &TableHandle
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to install MADT table\n"));
+ }
+
+ return Status;
+}
+
EFI_STATUS
EFIAPI
InitializeSbsaQemuAcpiDxe (
@@ -68,8 +205,27 @@ InitializeSbsaQemuAcpiDxe (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
+ EFI_STATUS Status;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
// Parse the device tree and get the number of CPUs
CountCpusFromFdt ();
+ // Check if ACPI Table Protocol has been installed
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTable
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to locate ACPI Table Protocol\n"));
+ return Status;
+ }
+
+ Status = AddMadtTable (AcpiTable);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n"));
+ }
+
return EFI_SUCCESS;
}
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime Tanmay Jagdale
@ 2020-08-26 15:35 ` graeme
2020-08-26 22:48 ` Graeme Gregory
0 siblings, 1 reply; 14+ messages in thread
From: graeme @ 2020-08-26 15:35 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: leif, devel, shashi.mallela
On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote:
> - Add support to create MADT table at runtime.
> - Included a macro for GIC Redistributor structure initialisation.
>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++-
> Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++
> Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 156 ++++++++++++++++++++
> 3 files changed, 190 insertions(+), 1 deletion(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> index 3795a7e11639..8125e8ba7553 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> @@ -41,9 +41,27 @@ [LibraryClasses]
> UefiRuntimeServicesTableLib
>
> [Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
>
> [Depex]
> - TRUE
> + gEfiAcpiTableProtocolGuid ## CONSUMES
> +
> +[Guids]
> + gEdkiiPlatformHasAcpiGuid
> +
> +[Protocols]
> + gEfiAcpiTableProtocolGuid ## CONSUMES
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> index eac195b0585c..7a9a0061675f 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -22,6 +22,21 @@
> FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \
> }
>
> +// Defines for MADT
> +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
> +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
> +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
> +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000
> +
> +// Macro for MADT GIC Redistributor Structure
> +#define SBSAQEMU_MADT_GICR_INIT() { \
> + EFI_ACPI_6_0_GICR, /* Type */ \
> + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ \
> + EFI_ACPI_RESERVED_WORD, /* Reserved */ \
> + FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress */ \
> + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ \
> + }
> +
> #define SBSAQEMU_UART0_BASE 0x60000000
>
> #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index 75abdae3b8ce..16cb4e904e6f 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -6,11 +6,17 @@
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> **/
> +#include <IndustryStandard/Acpi.h>
> +#include <IndustryStandard/SbsaQemuAcpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/BaseMemoryLib.h>
> #include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> #include <Library/PcdLib.h>
> #include <Library/UefiBootServicesTableLib.h>
> #include <Library/UefiDriverEntryPoint.h>
> #include <Library/UefiLib.h>
> +#include <Protocol/AcpiTable.h>
> #include <Protocol/FdtClient.h>
> #include <libfdt.h>
>
> @@ -61,6 +67,137 @@ CountCpusFromFdt (
> ASSERT_RETURN_ERROR (PcdStatus);
> }
>
> +/*
> + * A Function to Compute the ACPI Table Checksum
> + */
> +VOID
> +AcpiPlatformChecksum (
> + IN UINT8 *Buffer,
> + IN UINTN Size
> + )
> +{
> + UINTN ChecksumOffset;
> +
> + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
> +
> + // Set checksum field to 0 since it is used as part of the calculation
> + Buffer[ChecksumOffset] = 0;
> +
> + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
> +}
> +
> +/*
> + * A function that add the MADT ACPI table.
> + IN EFI_ACPI_COMMON_HEADER *CurrentTable
> + */
> +EFI_STATUS
> +AddMadtTable (
> + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> + )
> +{
> + EFI_STATUS Status;
> + UINTN TableHandle;
> + UINT32 TableSize;
> + EFI_PHYSICAL_ADDRESS PageAddress;
> + UINT8 *New;
> + UINT32 NumCores;
> +
> + // Initialize MADT ACPI Header
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = {
> + SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER,
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
> + 0, 0 };
> +
> + // Initialize GICC Structure
> + EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT (
> + 0, /* GicID */
> + 0, /* AcpiCpuUid */
> + 0, /* Mpidr */
> + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */
> + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */
> + FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */
> + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */
> + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */
> + 25, /* GsivId */
> + 0, /* GicRBase */
> + 0 /* Efficiency */
> + );
> +
> + // Initialize GIC Distributor Structure
> + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =
> + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (
> + 0,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0,
> + 3 /* GicVersion */
> + );
> +
> + // Initialize GIC Redistributor Structure
> + EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
> +
> + // Get CoreCount which was determined eariler after parsing device tree
> + NumCores = PcdGet32 (PcdCoreCount);
> +
> + // Calculate the new table size based on the number of cores
> + TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
> + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
> + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
> + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> +
> + Status = gBS->AllocatePages (
> + AllocateAnyPages,
> + EfiACPIReclaimMemory,
> + EFI_SIZE_TO_PAGES (TableSize),
> + &PageAddress
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MADT table\n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + New = (UINT8 *)(UINTN) PageAddress;
> + ZeroMem (New, TableSize);
> +
> + // Add the ACPI Description table header
> + CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
> + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
> + New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
> +
> + // Add new GICC structures for the Cores
> + for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) {
> + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr;
> +
> + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
> + GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
> + GiccPtr->AcpiProcessorUid = NumCores;
> + GiccPtr->MPIDR = NumCores;
This does not seem to be quite correct, if I dump the MPIDRs from ARM-TF when
booting with 12 cpus this is what I get.
NOTICE: MPIDR 0
NOTICE: MPIDR 1
NOTICE: MPIDR 2
NOTICE: MPIDR 3
NOTICE: MPIDR 4
NOTICE: MPIDR 5
NOTICE: MPIDR 6
NOTICE: MPIDR 7
NOTICE: MPIDR 100
NOTICE: MPIDR 101
NOTICE: MPIDR 102
NOTICE: MPIDR 103
I think this will make PSCI operations from CPU8 onwards fail.
Thanks
Graeme
> + New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE);
> + }
> +
> + // GIC Distributor Structure
> + CopyMem (New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE));
> + New += sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE);
> +
> + // GIC ReDistributor Structure
> + CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE));
> + New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> +
> + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
> +
> + Status = AcpiTable->InstallAcpiTable (
> + AcpiTable,
> + (EFI_ACPI_COMMON_HEADER *)PageAddress,
> + TableSize,
> + &TableHandle
> + );
> + if (EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_ERROR, "Failed to install MADT table\n"));
> + }
> +
> + return Status;
> +}
> +
> EFI_STATUS
> EFIAPI
> InitializeSbsaQemuAcpiDxe (
> @@ -68,8 +205,27 @@ InitializeSbsaQemuAcpiDxe (
> IN EFI_SYSTEM_TABLE *SystemTable
> )
> {
> + EFI_STATUS Status;
> + EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
> +
> // Parse the device tree and get the number of CPUs
> CountCpusFromFdt ();
>
> + // Check if ACPI Table Protocol has been installed
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiTableProtocolGuid,
> + NULL,
> + (VOID **)&AcpiTable
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Failed to locate ACPI Table Protocol\n"));
> + return Status;
> + }
> +
> + Status = AddMadtTable (AcpiTable);
> + if (EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n"));
> + }
> +
> return EFI_SUCCESS;
> }
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime
2020-08-26 15:35 ` graeme
@ 2020-08-26 22:48 ` Graeme Gregory
2020-08-27 2:56 ` Tanmay Jagdale
0 siblings, 1 reply; 14+ messages in thread
From: Graeme Gregory @ 2020-08-26 22:48 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: leif, devel, shashi.mallela
On Wed, Aug 26, 2020 at 04:35:22PM +0100, Graeme Gregory wrote:
> On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote:
> > - Add support to create MADT table at runtime.
> > - Included a macro for GIC Redistributor structure initialisation.
> >
> > Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> > ---
> > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++-
> > Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++
> > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 156 ++++++++++++++++++++
> > 3 files changed, 190 insertions(+), 1 deletion(-)
> >
> > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > index 3795a7e11639..8125e8ba7553 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > @@ -41,9 +41,27 @@ [LibraryClasses]
> > UefiRuntimeServicesTableLib
> >
> > [Pcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
> > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
> > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
> > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
> >
> > [Depex]
> > - TRUE
> > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > +
> > +[Guids]
> > + gEdkiiPlatformHasAcpiGuid
> > +
> > +[Protocols]
> > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > +
> > +[FixedPcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > + gArmTokenSpaceGuid.PcdGicDistributorBase
> > + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> > +
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > index eac195b0585c..7a9a0061675f 100644
> > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > @@ -22,6 +22,21 @@
> > FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \
> > }
> >
> > +// Defines for MADT
> > +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
> > +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
> > +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
> > +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000
> > +
> > +// Macro for MADT GIC Redistributor Structure
> > +#define SBSAQEMU_MADT_GICR_INIT() { \
> > + EFI_ACPI_6_0_GICR, /* Type */ \
> > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ \
> > + EFI_ACPI_RESERVED_WORD, /* Reserved */ \
> > + FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress */ \
> > + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ \
> > + }
> > +
> > #define SBSAQEMU_UART0_BASE 0x60000000
> >
> > #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
> > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > index 75abdae3b8ce..16cb4e904e6f 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > @@ -6,11 +6,17 @@
> > * SPDX-License-Identifier: BSD-2-Clause-Patent
> > *
> > **/
> > +#include <IndustryStandard/Acpi.h>
> > +#include <IndustryStandard/SbsaQemuAcpi.h>
> > +#include <Library/AcpiLib.h>
> > +#include <Library/BaseMemoryLib.h>
> > #include <Library/DebugLib.h>
> > +#include <Library/MemoryAllocationLib.h>
> > #include <Library/PcdLib.h>
> > #include <Library/UefiBootServicesTableLib.h>
> > #include <Library/UefiDriverEntryPoint.h>
> > #include <Library/UefiLib.h>
> > +#include <Protocol/AcpiTable.h>
> > #include <Protocol/FdtClient.h>
> > #include <libfdt.h>
> >
> > @@ -61,6 +67,137 @@ CountCpusFromFdt (
> > ASSERT_RETURN_ERROR (PcdStatus);
> > }
> >
> > +/*
> > + * A Function to Compute the ACPI Table Checksum
> > + */
> > +VOID
> > +AcpiPlatformChecksum (
> > + IN UINT8 *Buffer,
> > + IN UINTN Size
> > + )
> > +{
> > + UINTN ChecksumOffset;
> > +
> > + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
> > +
> > + // Set checksum field to 0 since it is used as part of the calculation
> > + Buffer[ChecksumOffset] = 0;
> > +
> > + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
> > +}
> > +
> > +/*
> > + * A function that add the MADT ACPI table.
> > + IN EFI_ACPI_COMMON_HEADER *CurrentTable
> > + */
> > +EFI_STATUS
> > +AddMadtTable (
> > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINTN TableHandle;
> > + UINT32 TableSize;
> > + EFI_PHYSICAL_ADDRESS PageAddress;
> > + UINT8 *New;
> > + UINT32 NumCores;
> > +
> > + // Initialize MADT ACPI Header
> > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = {
> > + SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER,
> > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
> > + 0, 0 };
> > +
> > + // Initialize GICC Structure
> > + EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT (
> > + 0, /* GicID */
> > + 0, /* AcpiCpuUid */
> > + 0, /* Mpidr */
> > + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */
> > + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */
> > + FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */
> > + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */
> > + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */
> > + 25, /* GsivId */
> > + 0, /* GicRBase */
> > + 0 /* Efficiency */
> > + );
> > +
> > + // Initialize GIC Distributor Structure
> > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =
> > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (
> > + 0,
> > + FixedPcdGet32 (PcdGicDistributorBase),
> > + 0,
> > + 3 /* GicVersion */
> > + );
> > +
> > + // Initialize GIC Redistributor Structure
> > + EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
> > +
> > + // Get CoreCount which was determined eariler after parsing device tree
> > + NumCores = PcdGet32 (PcdCoreCount);
> > +
> > + // Calculate the new table size based on the number of cores
> > + TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
> > + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
> > + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
> > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> > +
> > + Status = gBS->AllocatePages (
> > + AllocateAnyPages,
> > + EfiACPIReclaimMemory,
> > + EFI_SIZE_TO_PAGES (TableSize),
> > + &PageAddress
> > + );
> > + if (EFI_ERROR(Status)) {
> > + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MADT table\n"));
> > + return EFI_OUT_OF_RESOURCES;
> > + }
> > +
> > + New = (UINT8 *)(UINTN) PageAddress;
> > + ZeroMem (New, TableSize);
> > +
> > + // Add the ACPI Description table header
> > + CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
> > + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
> > + New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
> > +
> > + // Add new GICC structures for the Cores
> > + for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) {
> > + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr;
> > +
> > + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
> > + GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
> > + GiccPtr->AcpiProcessorUid = NumCores;
> > + GiccPtr->MPIDR = NumCores;
>
> This does not seem to be quite correct, if I dump the MPIDRs from ARM-TF when
> booting with 12 cpus this is what I get.
>
> NOTICE: MPIDR 0
> NOTICE: MPIDR 1
> NOTICE: MPIDR 2
> NOTICE: MPIDR 3
> NOTICE: MPIDR 4
> NOTICE: MPIDR 5
> NOTICE: MPIDR 6
> NOTICE: MPIDR 7
> NOTICE: MPIDR 100
> NOTICE: MPIDR 101
> NOTICE: MPIDR 102
> NOTICE: MPIDR 103
>
> I think this will make PSCI operations from CPU8 onwards fail.
>
I can confirm this is wrong
I did a quick hack
GiccPtr->MPIDR = ((NumCores / 8) << 8) | (NumCores % 8);
and I can boot 128 cores (MPIDR also needs fixed in SSDT I think)
[ 12.637579] GICv3: CPU127: found redistributor f07 region
0:0x0000000041060000
[ 12.640185] CPU127: Booted secondary processor 0x0000000f07
[0x411fd070]
[ 12.676961] smp: Brought up 1 node, 128 CPUs
Considering this patch is in the works
https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg06223.html
which add MPIDR to the DT, i think you will when that is accepted be
able to use the MPIDR from there and then you are protected for the
CPU topology changing.
Thanks
Graeme
> Thanks
>
> Graeme
>
>
> > + New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE);
> > + }
> > +
> > + // GIC Distributor Structure
> > + CopyMem (New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE));
> > + New += sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE);
> > +
> > + // GIC ReDistributor Structure
> > + CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE));
> > + New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> > +
> > + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
> > +
> > + Status = AcpiTable->InstallAcpiTable (
> > + AcpiTable,
> > + (EFI_ACPI_COMMON_HEADER *)PageAddress,
> > + TableSize,
> > + &TableHandle
> > + );
> > + if (EFI_ERROR(Status)) {
> > + DEBUG ((DEBUG_ERROR, "Failed to install MADT table\n"));
> > + }
> > +
> > + return Status;
> > +}
> > +
> > EFI_STATUS
> > EFIAPI
> > InitializeSbsaQemuAcpiDxe (
> > @@ -68,8 +205,27 @@ InitializeSbsaQemuAcpiDxe (
> > IN EFI_SYSTEM_TABLE *SystemTable
> > )
> > {
> > + EFI_STATUS Status;
> > + EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
> > +
> > // Parse the device tree and get the number of CPUs
> > CountCpusFromFdt ();
> >
> > + // Check if ACPI Table Protocol has been installed
> > + Status = gBS->LocateProtocol (
> > + &gEfiAcpiTableProtocolGuid,
> > + NULL,
> > + (VOID **)&AcpiTable
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "Failed to locate ACPI Table Protocol\n"));
> > + return Status;
> > + }
> > +
> > + Status = AddMadtTable (AcpiTable);
> > + if (EFI_ERROR(Status)) {
> > + DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n"));
> > + }
> > +
> > return EFI_SUCCESS;
> > }
> > --
> > 2.28.0
> >
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime
2020-08-26 22:48 ` Graeme Gregory
@ 2020-08-27 2:56 ` Tanmay Jagdale
2020-08-27 9:41 ` Graeme Gregory
0 siblings, 1 reply; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-27 2:56 UTC (permalink / raw)
To: Graeme Gregory; +Cc: Leif Lindholm, devel, Shashi Mallela
[-- Attachment #1: Type: text/plain, Size: 12564 bytes --]
Hi Graeme,
On Thu, 27 Aug 2020 at 04:18, Graeme Gregory <graeme@nuviainc.com> wrote:
> On Wed, Aug 26, 2020 at 04:35:22PM +0100, Graeme Gregory wrote:
> > On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote:
> > > - Add support to create MADT table at runtime.
> > > - Included a macro for GIC Redistributor structure initialisation.
> > >
> > > Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> > > ---
> > > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |
> 20 ++-
> > > Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h |
> 15 ++
> > > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c |
> 156 ++++++++++++++++++++
> > > 3 files changed, 190 insertions(+), 1 deletion(-)
> > >
> > > diff --git
> a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > > index 3795a7e11639..8125e8ba7553 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > > @@ -41,9 +41,27 @@ [LibraryClasses]
> > > UefiRuntimeServicesTableLib
> > >
> > > [Pcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
> > >
> > > [Depex]
> > > - TRUE
> > > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > > +
> > > +[Guids]
> > > + gEdkiiPlatformHasAcpiGuid
> > > +
> > > +[Protocols]
> > > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > > +
> > > +[FixedPcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > > + gArmTokenSpaceGuid.PcdGicDistributorBase
> > > + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> > > +
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > > diff --git
> a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > > index eac195b0585c..7a9a0061675f 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > > @@ -22,6 +22,21 @@
> > > FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32
> CreatorRevision */ \
> > > }
> > >
> > > +// Defines for MADT
> > > +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
> > > +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
> > > +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
> > > +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000
> > > +
> > > +// Macro for MADT GIC Redistributor Structure
> > > +#define SBSAQEMU_MADT_GICR_INIT() {
> \
> > > + EFI_ACPI_6_0_GICR, /* Type */
> \
> > > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */
> \
> > > + EFI_ACPI_RESERVED_WORD, /* Reserved */
> \
> > > + FixedPcdGet32 (PcdGicRedistributorsBase), /*
> DiscoveryRangeBaseAddress */ \
> > > + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength
> */ \
> > > + }
> > > +
> > > #define SBSAQEMU_UART0_BASE 0x60000000
> > >
> > > #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
> > > diff --git
> a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > index 75abdae3b8ce..16cb4e904e6f 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > @@ -6,11 +6,17 @@
> > > * SPDX-License-Identifier: BSD-2-Clause-Patent
> > > *
> > > **/
> > > +#include <IndustryStandard/Acpi.h>
> > > +#include <IndustryStandard/SbsaQemuAcpi.h>
> > > +#include <Library/AcpiLib.h>
> > > +#include <Library/BaseMemoryLib.h>
> > > #include <Library/DebugLib.h>
> > > +#include <Library/MemoryAllocationLib.h>
> > > #include <Library/PcdLib.h>
> > > #include <Library/UefiBootServicesTableLib.h>
> > > #include <Library/UefiDriverEntryPoint.h>
> > > #include <Library/UefiLib.h>
> > > +#include <Protocol/AcpiTable.h>
> > > #include <Protocol/FdtClient.h>
> > > #include <libfdt.h>
> > >
> > > @@ -61,6 +67,137 @@ CountCpusFromFdt (
> > > ASSERT_RETURN_ERROR (PcdStatus);
> > > }
> > >
> > > +/*
> > > + * A Function to Compute the ACPI Table Checksum
> > > + */
> > > +VOID
> > > +AcpiPlatformChecksum (
> > > + IN UINT8 *Buffer,
> > > + IN UINTN Size
> > > + )
> > > +{
> > > + UINTN ChecksumOffset;
> > > +
> > > + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
> > > +
> > > + // Set checksum field to 0 since it is used as part of the
> calculation
> > > + Buffer[ChecksumOffset] = 0;
> > > +
> > > + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
> > > +}
> > > +
> > > +/*
> > > + * A function that add the MADT ACPI table.
> > > + IN EFI_ACPI_COMMON_HEADER *CurrentTable
> > > + */
> > > +EFI_STATUS
> > > +AddMadtTable (
> > > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> > > + )
> > > +{
> > > + EFI_STATUS Status;
> > > + UINTN TableHandle;
> > > + UINT32 TableSize;
> > > + EFI_PHYSICAL_ADDRESS PageAddress;
> > > + UINT8 *New;
> > > + UINT32 NumCores;
> > > +
> > > + // Initialize MADT ACPI Header
> > > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = {
> > > + SBSAQEMU_ACPI_HEADER
> (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> > > +
> EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER,
> > > +
> EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
> > > + 0, 0 };
> > > +
> > > + // Initialize GICC Structure
> > > + EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT (
> > > + 0, /* GicID */
> > > + 0, /* AcpiCpuUid */
> > > + 0, /* Mpidr */
> > > + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */
> > > + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */
> > > + FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */
> > > + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */
> > > + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */
> > > + 25, /* GsivId */
> > > + 0, /* GicRBase */
> > > + 0 /* Efficiency */
> > > + );
> > > +
> > > + // Initialize GIC Distributor Structure
> > > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =
> > > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (
> > > + 0,
> > > + FixedPcdGet32 (PcdGicDistributorBase),
> > > + 0,
> > > + 3 /* GicVersion */
> > > + );
> > > +
> > > + // Initialize GIC Redistributor Structure
> > > + EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
> > > +
> > > + // Get CoreCount which was determined eariler after parsing device
> tree
> > > + NumCores = PcdGet32 (PcdCoreCount);
> > > +
> > > + // Calculate the new table size based on the number of cores
> > > + TableSize = sizeof
> (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
> > > + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
> > > + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
> > > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> > > +
> > > + Status = gBS->AllocatePages (
> > > + AllocateAnyPages,
> > > + EfiACPIReclaimMemory,
> > > + EFI_SIZE_TO_PAGES (TableSize),
> > > + &PageAddress
> > > + );
> > > + if (EFI_ERROR(Status)) {
> > > + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MADT
> table\n"));
> > > + return EFI_OUT_OF_RESOURCES;
> > > + }
> > > +
> > > + New = (UINT8 *)(UINTN) PageAddress;
> > > + ZeroMem (New, TableSize);
> > > +
> > > + // Add the ACPI Description table header
> > > + CopyMem (New, &Header, sizeof
> (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
> > > + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
> > > + New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
> > > +
> > > + // Add new GICC structures for the Cores
> > > + for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) {
> > > + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr;
> > > +
> > > + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
> > > + GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
> > > + GiccPtr->AcpiProcessorUid = NumCores;
> > > + GiccPtr->MPIDR = NumCores;
> >
> > This does not seem to be quite correct, if I dump the MPIDRs from ARM-TF
> when
> > booting with 12 cpus this is what I get.
> >
> > NOTICE: MPIDR 0
> > NOTICE: MPIDR 1
> > NOTICE: MPIDR 2
> > NOTICE: MPIDR 3
> > NOTICE: MPIDR 4
> > NOTICE: MPIDR 5
> > NOTICE: MPIDR 6
> > NOTICE: MPIDR 7
> > NOTICE: MPIDR 100
> > NOTICE: MPIDR 101
> > NOTICE: MPIDR 102
> > NOTICE: MPIDR 103
> >
> > I think this will make PSCI operations from CPU8 onwards fail.
> >
>
> I can confirm this is wrong
>
> I did a quick hack
>
> GiccPtr->MPIDR = ((NumCores / 8) << 8) | (NumCores % 8);
>
> Thanks for the fix.
> and I can boot 128 cores (MPIDR also needs fixed in SSDT I think)
>
> [ 12.637579] GICv3: CPU127: found redistributor f07 region
> 0:0x0000000041060000
> [ 12.640185] CPU127: Booted secondary processor 0x0000000f07
> [0x411fd070]
> [ 12.676961] smp: Brought up 1 node, 128 CPUs
>
> Considering this patch is in the works
>
> https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg06223.html
>
> which add MPIDR to the DT, i think you will when that is accepted be
> able to use the MPIDR from there and then you are protected for the
> CPU topology changing.
>
> So shall I push an interim patch that uses the aforementioned formula
to derive the MPIDR ? Or wait for the qemu patch to get merged and
then read MPIDR directly from there ?
Thanks,
Tanmay
Thanks
>
> Graeme
>
>
> > Thanks
> >
> > Graeme
> >
> >
> > > + New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE);
> > > + }
> > > +
> > > + // GIC Distributor Structure
> > > + CopyMem (New, &Gicd, sizeof
> (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE));
> > > + New += sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE);
> > > +
> > > + // GIC ReDistributor Structure
> > > + CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE));
> > > + New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> > > +
> > > + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
> > > +
> > > + Status = AcpiTable->InstallAcpiTable (
> > > + AcpiTable,
> > > + (EFI_ACPI_COMMON_HEADER *)PageAddress,
> > > + TableSize,
> > > + &TableHandle
> > > + );
> > > + if (EFI_ERROR(Status)) {
> > > + DEBUG ((DEBUG_ERROR, "Failed to install MADT table\n"));
> > > + }
> > > +
> > > + return Status;
> > > +}
> > > +
> > > EFI_STATUS
> > > EFIAPI
> > > InitializeSbsaQemuAcpiDxe (
> > > @@ -68,8 +205,27 @@ InitializeSbsaQemuAcpiDxe (
> > > IN EFI_SYSTEM_TABLE *SystemTable
> > > )
> > > {
> > > + EFI_STATUS Status;
> > > + EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
> > > +
> > > // Parse the device tree and get the number of CPUs
> > > CountCpusFromFdt ();
> > >
> > > + // Check if ACPI Table Protocol has been installed
> > > + Status = gBS->LocateProtocol (
> > > + &gEfiAcpiTableProtocolGuid,
> > > + NULL,
> > > + (VOID **)&AcpiTable
> > > + );
> > > + if (EFI_ERROR (Status)) {
> > > + DEBUG ((DEBUG_ERROR, "Failed to locate ACPI Table Protocol\n"));
> > > + return Status;
> > > + }
> > > +
> > > + Status = AddMadtTable (AcpiTable);
> > > + if (EFI_ERROR(Status)) {
> > > + DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n"));
> > > + }
> > > +
> > > return EFI_SUCCESS;
> > > }
> > > --
> > > 2.28.0
> > >
>
[-- Attachment #2: Type: text/html, Size: 17779 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime
2020-08-27 2:56 ` Tanmay Jagdale
@ 2020-08-27 9:41 ` Graeme Gregory
0 siblings, 0 replies; 14+ messages in thread
From: Graeme Gregory @ 2020-08-27 9:41 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: Leif Lindholm, devel, Shashi Mallela
On Thu, Aug 27, 2020 at 08:26:21AM +0530, Tanmay Jagdale wrote:
> Hi Graeme,
>
>
> On Thu, 27 Aug 2020 at 04:18, Graeme Gregory <[1]graeme@nuviainc.com> wrote:
>
> On Wed, Aug 26, 2020 at 04:35:22PM +0100, Graeme Gregory wrote:
> > On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote:
> > > - Add support to create MADT table at runtime.
> > > - Included a macro for GIC Redistributor structure initialisation.
> > >
> > > Signed-off-by: Tanmay Jagdale <[2]tanmay.jagdale@linaro.org>
> > > ---
> > > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |
> 20 ++-
> > > Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h |
> 15 ++
> > > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c |
> 156 ++++++++++++++++++++
> > > 3 files changed, 190 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/
> SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/
> SbsaQemuAcpiDxe.inf
> > > index 3795a7e11639..8125e8ba7553 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > > @@ -41,9 +41,27 @@ [LibraryClasses]
> > > UefiRuntimeServicesTableLib
> > >
> > > [Pcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
> > >
> > > [Depex]
> > > - TRUE
> > > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > > +
> > > +[Guids]
> > > + gEdkiiPlatformHasAcpiGuid
> > > +
> > > +[Protocols]
> > > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > > +
> > > +[FixedPcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > > + gArmTokenSpaceGuid.PcdGicDistributorBase
> > > + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> > > +
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/
> SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/
> SbsaQemuAcpi.h
> > > index eac195b0585c..7a9a0061675f 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > > @@ -22,6 +22,21 @@
> > > FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32
> CreatorRevision */ \
> > > }
> > >
> > > +// Defines for MADT
> > > +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
> > > +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
> > > +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
> > > +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000
> > > +
> > > +// Macro for MADT GIC Redistributor Structure
> > > +#define SBSAQEMU_MADT_GICR_INIT() {
> \
> > > + EFI_ACPI_6_0_GICR, /* Type */
> \
> > > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */
> \
> > > + EFI_ACPI_RESERVED_WORD, /* Reserved */
> \
> > > + FixedPcdGet32 (PcdGicRedistributorsBase), /*
> DiscoveryRangeBaseAddress */ \
> > > + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength *
> / \
> > > + }
> > > +
> > > #define SBSAQEMU_UART0_BASE 0x60000000
> > >
> > > #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
> > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/
> SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/
> SbsaQemuAcpiDxe.c
> > > index 75abdae3b8ce..16cb4e904e6f 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > @@ -6,11 +6,17 @@
> > > * SPDX-License-Identifier: BSD-2-Clause-Patent
> > > *
> > > **/
> > > +#include <IndustryStandard/Acpi.h>
> > > +#include <IndustryStandard/SbsaQemuAcpi.h>
> > > +#include <Library/AcpiLib.h>
> > > +#include <Library/BaseMemoryLib.h>
> > > #include <Library/DebugLib.h>
> > > +#include <Library/MemoryAllocationLib.h>
> > > #include <Library/PcdLib.h>
> > > #include <Library/UefiBootServicesTableLib.h>
> > > #include <Library/UefiDriverEntryPoint.h>
> > > #include <Library/UefiLib.h>
> > > +#include <Protocol/AcpiTable.h>
> > > #include <Protocol/FdtClient.h>
> > > #include <libfdt.h>
> > >
> > > @@ -61,6 +67,137 @@ CountCpusFromFdt (
> > > ASSERT_RETURN_ERROR (PcdStatus);
> > > }
> > >
> > > +/*
> > > + * A Function to Compute the ACPI Table Checksum
> > > + */
> > > +VOID
> > > +AcpiPlatformChecksum (
> > > + IN UINT8 *Buffer,
> > > + IN UINTN Size
> > > + )
> > > +{
> > > + UINTN ChecksumOffset;
> > > +
> > > + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
> > > +
> > > + // Set checksum field to 0 since it is used as part of the
> calculation
> > > + Buffer[ChecksumOffset] = 0;
> > > +
> > > + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
> > > +}
> > > +
> > > +/*
> > > + * A function that add the MADT ACPI table.
> > > + IN EFI_ACPI_COMMON_HEADER *CurrentTable
> > > + */
> > > +EFI_STATUS
> > > +AddMadtTable (
> > > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> > > + )
> > > +{
> > > + EFI_STATUS Status;
> > > + UINTN TableHandle;
> > > + UINT32 TableSize;
> > > + EFI_PHYSICAL_ADDRESS PageAddress;
> > > + UINT8 *New;
> > > + UINT32 NumCores;
> > > +
> > > + // Initialize MADT ACPI Header
> > > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = {
> > > + SBSAQEMU_ACPI_HEADER
> (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> > > +
> EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER,
> > > +
> EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
> > > + 0, 0 };
> > > +
> > > + // Initialize GICC Structure
> > > + EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT (
> > > + 0, /* GicID */
> > > + 0, /* AcpiCpuUid */
> > > + 0, /* Mpidr */
> > > + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */
> > > + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */
> > > + FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */
> > > + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */
> > > + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */
> > > + 25, /* GsivId */
> > > + 0, /* GicRBase */
> > > + 0 /* Efficiency */
> > > + );
> > > +
> > > + // Initialize GIC Distributor Structure
> > > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =
> > > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (
> > > + 0,
> > > + FixedPcdGet32 (PcdGicDistributorBase),
> > > + 0,
> > > + 3 /* GicVersion */
> > > + );
> > > +
> > > + // Initialize GIC Redistributor Structure
> > > + EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
> > > +
> > > + // Get CoreCount which was determined eariler after parsing device
> tree
> > > + NumCores = PcdGet32 (PcdCoreCount);
> > > +
> > > + // Calculate the new table size based on the number of cores
> > > + TableSize = sizeof
> (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
> > > + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
> > > + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
> > > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> > > +
> > > + Status = gBS->AllocatePages (
> > > + AllocateAnyPages,
> > > + EfiACPIReclaimMemory,
> > > + EFI_SIZE_TO_PAGES (TableSize),
> > > + &PageAddress
> > > + );
> > > + if (EFI_ERROR(Status)) {
> > > + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MADT table\
> n"));
> > > + return EFI_OUT_OF_RESOURCES;
> > > + }
> > > +
> > > + New = (UINT8 *)(UINTN) PageAddress;
> > > + ZeroMem (New, TableSize);
> > > +
> > > + // Add the ACPI Description table header
> > > + CopyMem (New, &Header, sizeof
> (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
> > > + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
> > > + New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
> > > +
> > > + // Add new GICC structures for the Cores
> > > + for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) {
> > > + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr;
> > > +
> > > + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
> > > + GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
> > > + GiccPtr->AcpiProcessorUid = NumCores;
> > > + GiccPtr->MPIDR = NumCores;
> >
> > This does not seem to be quite correct, if I dump the MPIDRs from ARM-TF
> when
> > booting with 12 cpus this is what I get.
> >
> > NOTICE: MPIDR 0
> > NOTICE: MPIDR 1
> > NOTICE: MPIDR 2
> > NOTICE: MPIDR 3
> > NOTICE: MPIDR 4
> > NOTICE: MPIDR 5
> > NOTICE: MPIDR 6
> > NOTICE: MPIDR 7
> > NOTICE: MPIDR 100
> > NOTICE: MPIDR 101
> > NOTICE: MPIDR 102
> > NOTICE: MPIDR 103
> >
> > I think this will make PSCI operations from CPU8 onwards fail.
> >
>
> I can confirm this is wrong
>
> I did a quick hack
>
> GiccPtr->MPIDR = ((NumCores / 8) << 8) | (NumCores % 8);
>
>
> Thanks for the fix.
>
>
> and I can boot 128 cores (MPIDR also needs fixed in SSDT I think)
>
> [ 12.637579] GICv3: CPU127: found redistributor f07 region
> 0:0x0000000041060000
> [ 12.640185] CPU127: Booted secondary processor 0x0000000f07
> [0x411fd070]
> [ 12.676961] smp: Brought up 1 node, 128 CPUs
>
> Considering this patch is in the works
>
> [3]https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg06223.html
>
> which add MPIDR to the DT, i think you will when that is accepted be
> able to use the MPIDR from there and then you are protected for the
> CPU topology changing.
>
>
> So shall I push an interim patch that uses the aforementioned formula
> to derive the MPIDR ? Or wait for the qemu patch to get merged and
> then read MPIDR directly from there ?
>
IMHO wait for to see progress on Leif's patch, then issue an update to
read the MPIDR from the FDT. Obviously you can start the
development/review process for that before patch lands.
The formula only works because I happen to know what qemu generates today.
This might change with a qemu change in future though.
Graeme
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 edk2-platforms 6/8] SbsaQemu: AcpiDxe: Create SSDT table at runtime
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (4 preceding siblings ...)
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime Tanmay Jagdale
@ 2020-08-25 13:39 ` Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 7/8] SbsaQemu: AcpiDxe: Create PPTT " Tanmay Jagdale
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-25 13:39 UTC (permalink / raw)
To: leif, graeme, devel; +Cc: shashi.mallela, Tanmay Jagdale
- Add support to create SSDT table at runtime. Since SSDT
table is a data table, added a few helper macros to create
the AML entries.
- Also added a function to calculate the length of Packages.
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 29 ++++
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 144 ++++++++++++++++++++
2 files changed, 173 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 7a9a0061675f..00c7c68256fd 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -43,4 +43,33 @@
#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00
#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF
+#define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5
+
+#define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' }
+
+#define SBSAQEMU_ACPI_CPU_DEV_LEN 0x1C
+#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' }
+
+// Macro to convert Integer to Character
+#define SBSAQEMU_ACPI_ITOA(Byte) (0x30 + (Byte > 9 ? (Byte + 1) : Byte))
+
+#define SBSAQEMU_ACPI_CPU_HID { \
+ AML_NAME_OP, AML_NAME_CHAR__, 'H', 'I', 'D', \
+ AML_STRING_PREFIX, 'A', 'C', 'P', 'I', '0', '0', '0', '7', \
+ AML_ZERO_OP \
+ }
+
+#define SBSAQEMU_ACPI_CPU_UID { \
+ AML_NAME_OP, AML_NAME_CHAR__, 'U', 'I', 'D', AML_BYTE_PREFIX, \
+ AML_ZERO_OP, AML_ZERO_OP \
+ }
+
+typedef struct {
+ UINT8 device_header[2];
+ UINT8 length;
+ UINT8 dev_name[4];
+ UINT8 hid[15];
+ UINT8 uid[8];
+} SBSAQEMU_ACPI_CPU_DEVICE;
+
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 16cb4e904e6f..06e7a5310810 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -7,6 +7,7 @@
*
**/
#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/AcpiAml.h>
#include <IndustryStandard/SbsaQemuAcpi.h>
#include <Library/AcpiLib.h>
#include <Library/BaseMemoryLib.h>
@@ -198,6 +199,144 @@ AddMadtTable (
return Status;
}
+/*
+ * Function to calculate the PkgLength field in ACPI tables
+ */
+STATIC
+UINT32
+SetPkgLength (
+ IN UINT8 *TablePtr,
+ IN UINT32 Length
+)
+{
+ UINT8 ByteCount;
+ UINT8 *PkgLeadByte = TablePtr;
+
+ if (Length < 64) {
+ *TablePtr = Length;
+ return 1;
+ }
+
+ // Set the LSB of Length in PkgLeadByte and advance Length
+ *PkgLeadByte = Length & 0xF;
+ Length = Length >> 4;
+
+ while (Length) {
+ TablePtr++;
+ *TablePtr = (Length & 0xFF);
+ Length = (Length >> 8);
+ }
+
+ // Calculate the number of bytes the Length field uses
+ // and set the ByteCount field in PkgLeadByte.
+ ByteCount = (TablePtr - PkgLeadByte) & 0xF;
+ *PkgLeadByte |= (ByteCount << 6);
+
+ return ByteCount + 1;
+}
+
+/*
+ * A function that adds SSDT ACPI table.
+ */
+EFI_STATUS
+AddSsdtTable (
+ IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN TableHandle;
+ UINT32 TableSize;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINT8 *New;
+ UINT32 CpuId;
+ UINT32 Offset;
+ UINT8 ScopeOpName[] = SBSAQEMU_ACPI_SCOPE_NAME;
+ UINT32 NumCores = PcdGet32 (PcdCoreCount);
+
+ EFI_ACPI_DESCRIPTION_HEADER Header =
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_DESCRIPTION_HEADER,
+ EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION);
+
+ SBSAQEMU_ACPI_CPU_DEVICE CpuDevice = {
+ { AML_EXT_OP, AML_EXT_DEVICE_OP }, /* Device () */
+ SBSAQEMU_ACPI_CPU_DEV_LEN, /* Length */
+ SBSAQEMU_ACPI_CPU_DEV_NAME, /* Device Name "C000" */
+ SBSAQEMU_ACPI_CPU_HID, /* Name (HID, "ACPI0007") */
+ SBSAQEMU_ACPI_CPU_UID, /* Name (UID, 0) */
+ };
+
+ // Calculate the new table size based on the number of cores
+ TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
+ SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH + sizeof (ScopeOpName) +
+ (sizeof (CpuDevice) * NumCores);
+
+ Status = gBS->AllocatePages (
+ AllocateAnyPages,
+ EfiACPIReclaimMemory,
+ EFI_SIZE_TO_PAGES (TableSize),
+ &PageAddress
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate pages for SSDT table\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ New = (UINT8 *)(UINTN) PageAddress;
+ ZeroMem (New, TableSize);
+
+ // Add the ACPI Description table header
+ CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
+ ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
+ New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
+
+ // Insert the top level ScopeOp
+ *New = AML_SCOPE_OP;
+ New++;
+ Offset = SetPkgLength (New,
+ (TableSize - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - 1));
+ New += Offset;
+ CopyMem (New, &ScopeOpName, sizeof (ScopeOpName));
+ New += sizeof (ScopeOpName);
+
+ // Add new Device structures for the Cores
+ for (CpuId = 0; CpuId < NumCores; CpuId++) {
+ SBSAQEMU_ACPI_CPU_DEVICE *CpuDevicePtr;
+ UINT8 CpuIdByte1, CpuIdByte2, CpuIdByte3;
+
+ CopyMem (New, &CpuDevice, sizeof (SBSAQEMU_ACPI_CPU_DEVICE));
+ CpuDevicePtr = (SBSAQEMU_ACPI_CPU_DEVICE *) New;
+
+ CpuIdByte1 = CpuId & 0xF;
+ CpuIdByte2 = (CpuId >> 4) & 0xF;
+ CpuIdByte3 = (CpuId >> 8) & 0xF;
+
+ CpuDevicePtr->dev_name[1] = SBSAQEMU_ACPI_ITOA(CpuIdByte3);
+ CpuDevicePtr->dev_name[2] = SBSAQEMU_ACPI_ITOA(CpuIdByte2);
+ CpuDevicePtr->dev_name[3] = SBSAQEMU_ACPI_ITOA(CpuIdByte1);
+
+ CpuDevicePtr->uid[6] = CpuIdByte1 | CpuIdByte2;
+ CpuDevicePtr->uid[7] = CpuIdByte3;
+ New += sizeof (SBSAQEMU_ACPI_CPU_DEVICE);
+ }
+
+ // Perform Checksum
+ AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ (EFI_ACPI_COMMON_HEADER *)PageAddress,
+ TableSize,
+ &TableHandle
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to install SSDT table\n"));
+ }
+
+ return Status;
+}
+
EFI_STATUS
EFIAPI
InitializeSbsaQemuAcpiDxe (
@@ -227,5 +366,10 @@ InitializeSbsaQemuAcpiDxe (
DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n"));
}
+ Status = AddSsdtTable (AcpiTable);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n"));
+ }
+
return EFI_SUCCESS;
}
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 edk2-platforms 7/8] SbsaQemu: AcpiDxe: Create PPTT table at runtime
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (5 preceding siblings ...)
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 6/8] SbsaQemu: AcpiDxe: Create SSDT " Tanmay Jagdale
@ 2020-08-25 13:39 ` Tanmay Jagdale
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 8/8] SbsaQemu: AcpiTables: Add DBG2 Table Tanmay Jagdale
2020-08-25 13:57 ` [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Leif Lindholm
8 siblings, 0 replies; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-25 13:39 UTC (permalink / raw)
To: leif, graeme, devel; +Cc: shashi.mallela, Tanmay Jagdale
Add support to create Processor Properties Topology Table at
runtime. The cache topology of each CPU is as follows:
CPU N
------------------------
| -------- -------- |
| | L1-I | | L1-D | |
| | 32KB | | 32KB | |
| -------- -------- |
| ------------------ |
| | L2 512KB | |
| ------------------ |
------------------------
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 124 ++++++++++++++++++++
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 110 +++++++++++++++++
2 files changed, 234 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 00c7c68256fd..de6b51ccd034 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -72,4 +72,128 @@ typedef struct {
UINT8 uid[8];
} SBSAQEMU_ACPI_CPU_DEVICE;
+#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB
+#define SBSAQEMU_L1_D_CACHE_SETS 256
+#define SBSAQEMU_L1_D_CACHE_ASSC 2
+
+#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB
+#define SBSAQEMU_L1_I_CACHE_SETS 256
+#define SBSAQEMU_L1_I_CACHE_ASSC 2
+
+#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB
+#define SBSAQEMU_L2_CACHE_SETS 1024
+#define SBSAQEMU_L2_CACHE_ASSC 8
+
+#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
+#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+
+#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
+ SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
+ SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }
+
+#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 0, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
+ SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
+ SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ 0, \
+ }, \
+ 64 /* LineSize */ \
+ }
+
+#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
+ SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
+ SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }
+
+#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
+ }, \
+ 0, /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 0, /* NumberOfPrivateResources */ \
+ }
+
+#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
+ (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
+ }, \
+ 0, /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 2, /* NumberOfPrivateResources */ \
+ }
+
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 06e7a5310810..89c367350e70 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -337,6 +337,111 @@ AddSsdtTable (
return Status;
}
+/*
+ * A function that adds the SSDT ACPI table.
+ */
+EFI_STATUS
+AddPpttTable (
+ IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN TableHandle;
+ UINT32 TableSize;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINT8 *New;
+ UINT32 CpuId;
+ UINT32 NumCores = PcdGet32 (PcdCoreCount);
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT;
+
+ EFI_ACPI_DESCRIPTION_HEADER Header =
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_DESCRIPTION_HEADER,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION);
+
+ TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) +
+ (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) +
+ (sizeof (UINT32) * 2 * NumCores);
+
+ Status = gBS->AllocatePages (
+ AllocateAnyPages,
+ EfiACPIReclaimMemory,
+ EFI_SIZE_TO_PAGES (TableSize),
+ &PageAddress
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate pages for PPTT table\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ New = (UINT8 *)(UINTN) PageAddress;
+ ZeroMem (New, TableSize);
+
+ // Add the ACPI Description table header
+ CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
+ ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
+ New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
+
+ // Add the Cluster PPTT structure
+ CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ // Add L1 D Cache structure
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = 0; /* L2 is LLC */
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ for (CpuId = 0; CpuId < NumCores; CpuId++) {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr;
+ UINT32 *PrivateResourcePtr;
+
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New;
+ CorePtr->Parent = CLUSTER_INDEX;
+ CorePtr->AcpiProcessorId = CpuId;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ PrivateResourcePtr = (UINT32 *) New;
+ PrivateResourcePtr[0] = L1_D_CACHE_INDEX;
+ PrivateResourcePtr[1] = L1_I_CACHE_INDEX;
+ New += (2 * sizeof (UINT32));
+ }
+
+ // Perform Checksum
+ AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ (EFI_ACPI_COMMON_HEADER *)PageAddress,
+ TableSize,
+ &TableHandle
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to install PPTT table\n"));
+ }
+
+ return Status;
+}
+
EFI_STATUS
EFIAPI
InitializeSbsaQemuAcpiDxe (
@@ -371,5 +476,10 @@ InitializeSbsaQemuAcpiDxe (
DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n"));
}
+ Status = AddPpttTable (AcpiTable);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to add PPTT table\n"));
+ }
+
return EFI_SUCCESS;
}
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 edk2-platforms 8/8] SbsaQemu: AcpiTables: Add DBG2 Table
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (6 preceding siblings ...)
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 7/8] SbsaQemu: AcpiDxe: Create PPTT " Tanmay Jagdale
@ 2020-08-25 13:39 ` Tanmay Jagdale
2020-08-25 13:57 ` [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Leif Lindholm
8 siblings, 0 replies; 14+ messages in thread
From: Tanmay Jagdale @ 2020-08-25 13:39 UTC (permalink / raw)
To: leif, graeme, devel; +Cc: shashi.mallela, Tanmay Jagdale
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 67 ++++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 57d717fefafc..7216a53304df 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -16,6 +16,7 @@ [Defines]
VERSION_STRING = 1.0
[Sources]
+ Dbg2.aslc
Dsdt.asl
Fadt.aslc
Gtdt.aslc
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
new file mode 100644
index 000000000000..c9e3ca77ab53
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
@@ -0,0 +1,67 @@
+/** @file
+* Debug Port Table (DBG2)
+*
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+#include <IndustryStandard/SbsaQemuAcpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+
+#pragma pack(1)
+
+#define SBSAQEMU_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '0', 0x00 }
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[10];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;
+} DBG2_TABLE;
+
+
+STATIC DBG2_TABLE Dbg2 = {
+ {
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+ DBG2_TABLE,
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION
+ ),
+ OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),
+ 1 /* NumberOfDebugPorts */
+ },
+ {
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION),
+ 1, /* NumberofGenericAddressRegisters */
+ 10, /* NameSpaceStringLength */
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),
+ 0, /* OemDataLength */
+ 0, /* OemDataOffset */
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)
+ },
+ ARM_GAS32 (SBSAQEMU_UART0_BASE), /* BaseAddressRegister */
+ 0x1000, /* AddressSize */
+ SBSAQEMU_UART_STR, /* NameSpaceString */
+ }
+};
+
+#pragma pack()
+
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Dbg2;
--
2.28.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu
2020-08-25 13:39 [PATCH v3 edk2-platforms 0/8] Add ACPI tables support for SbsaQemu Tanmay Jagdale
` (7 preceding siblings ...)
2020-08-25 13:39 ` [PATCH v3 edk2-platforms 8/8] SbsaQemu: AcpiTables: Add DBG2 Table Tanmay Jagdale
@ 2020-08-25 13:57 ` Leif Lindholm
8 siblings, 0 replies; 14+ messages in thread
From: Leif Lindholm @ 2020-08-25 13:57 UTC (permalink / raw)
To: Tanmay Jagdale; +Cc: graeme, devel, shashi.mallela
On Tue, Aug 25, 2020 at 19:09:50 +0530, Tanmay Jagdale wrote:
> This patch series adds ACPI tables support for the SbsaQemu platform.
> We are using a pseudo static approach to create the ACPI tables.
>
> The ACPI tables namely DBG2, DSDT, MCFG, SPCR, GTDT are created in a
> static way at compile time because they hold a fixed configuration
> and there are no changes at runtime.
>
> The MADT, SSDT and PPTT tables are dependant on the number of CPUs and
> hence they are created at runtime based on the number of CPUs the user
> has requested
>
> Changes in v3:
> - Dropped ASSERT() in CountCpusFromFdt() function in patch 4.
> - Changed EFI_D_ERROR to DEBUG_ERROR
>
> Changes in v2:
> - Moved PcdCoreCount and Fdtlib related changes in SbsaQemu.dsc to a
> separate patch (Patch 3).
> - Removed Acpi6x.h header file includes and used IndustryStandard/Acpi.h
> - Whitespace cleanups
> - Added proper code comments
Thanks for quick respin.
For the series:
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Pushed as 23863e9e9d40..90c3b3bc0c3e.
> Tanmay Jagdale (8):
> SbsaQemu: Initial support for static ACPI tables
> SbsaQemu: AcpiTables: Add PCI support and MCFG Table
> SbsaQemu: SbsaQemu.dsc: Move CoreCount and Fdtlib
> SbsaQemu: Add new ACPI driver and FDT parser to count CPUs
> SbsaQemu: AcpiDxe: Create MADT table at runtime
> SbsaQemu: AcpiDxe: Create SSDT table at runtime
> SbsaQemu: AcpiDxe: Create PPTT table at runtime
> SbsaQemu: AcpiTables: Add DBG2 Table
>
> Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 8 +-
> Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 36 ++
> Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 12 +-
> Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 9 +
> Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 47 ++
> Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 67 +++
> Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 199 ++++++++
> Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 485 ++++++++++++++++++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 67 +++
> Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 449 ++++++++++++++++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 80 ++++
> Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 67 +++
> Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 ++
> Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 53 +++
> 14 files changed, 1618 insertions(+), 4 deletions(-)
> create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> create mode 100644 Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
>
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread