From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.18040.1598532367703031548 for ; Thu, 27 Aug 2020 05:46:07 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0508fb1276=abner.chang@hpe.com) Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07RChl3I020270 for ; Thu, 27 Aug 2020 12:46:07 GMT Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0a-002e3701.pphosted.com with ESMTP id 335kg9aw3b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 27 Aug 2020 12:46:07 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id E96708E for ; Thu, 27 Aug 2020 12:46:06 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.39]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 0208748; Thu, 27 Aug 2020 12:46:05 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer Subject: [edk2-plaforms PATCH 2/3] RISC-V/PlatformPkg: Revise Readme.md Date: Thu, 27 Aug 2020 20:03:04 +0800 Message-Id: <20200827120305.26095-3-abner.chang@hpe.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200827120305.26095-1-abner.chang@hpe.com> References: <20200827120305.26095-1-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-08-27_07:2020-08-27,2020-08-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 suspectscore=0 mlxlogscore=912 impostorscore=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270095 Content-Transfer-Encoding: quoted-printable Update RISC-V PlatformPkg Readme.md to align with the latest implementation. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Daniel Schaefer --- Platform/RISC-V/PlatformPkg/Readme.md | 72 ++++++++++++++------------- 1 file changed, 37 insertions(+), 35 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/Platfo= rmPkg/Readme.md index 2632ebeb28..bd3b823fb4 100644 --- a/Platform/RISC-V/PlatformPkg/Readme.md +++ b/Platform/RISC-V/PlatformPkg/Readme.md @@ -1,49 +1,48 @@ -# Introduction=0D +# Introduction of EDK2 RISC-V Port=0D =0D -## EDK2 RISC-V Platform Packages=0D -RISC-V platform package provides the generic and common modules for RISC-V= =0D -platforms. RISC-V platform package could include RiscPlatformPkg.dec to=0D -use the common drivers, libraries, definitions, PCDs and etc. for the=0D -platform development.=0D +## EDK2 RISC-V Project=0D +The edk2 build architecture which is supported and verified on edk2 code b= ase for RISC-V platforms is `RISCV64`.=0D +The toolchain is on RISC-V GitHub (https://github.com/riscv/riscv-gnu-tool= chain) for building edk2 RISC-V binary.=0D +The corresponding edk2 Toolchain tag for building RISC-V platform is "GCC5= " declared in `tools_def.txt`.=0D =0D -There are two packages to support RISC-V:=0D +There are two packages to support RISC-V edk2 platforms:=0D - `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec`=0D - `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec`=0D =0D -`RiscVPlatformPkg` provides SEC phase and NULL libs.=0D -`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers.=0D +`RiscVPlatformPkg` currently provides the generic SEC driver for all RISC-= V platforms, and some platform level libraries.=0D +`RiscVProcessorPkg` currently provides RISC-V processor related libraries,= PEI modules, DXE drivers and industrial=0D +standard header files.=0D =0D -### Download the sources ###=0D +## EDK2 RISC-V Platform Package=0D +RISC-V platform package provides the common modules for RISC-V platforms. = RISC-V platform vendors could include=0D +RiscPlatformPkg.dec to use the common drivers, libraries, definitions, PCD= s and etc. for the=0D +RISC-V platform development.=0D +=0D +### Download the Source Code ###=0D ```=0D git clone https://github.com/tianocore/edk2.git=0D +git clone https://github.com/tianocore/edk2-platforms.git=0D =0D -git clone https://github.com/changab/edk2-platforms.git=0D -# Check out branch: riscv-smode-lib=0D ```=0D =0D -To build it, you have to follow the regular steps for EDK2 and additionall= y set=0D -an environmen variable to point to your RISC-V toolchain installation,=0D -including the binary prefixes:=0D -=0D +You have to follow the build steps for EDK2 (https://github.com/tianocore/= tianocore.github.io/wiki/Getting-Started-with-EDK-II)=0D +and additionally set an environment variable to point to your RISC-V toolc= hain binaries for building RISC-V=0D +platforms,=0D ```=0D +# e.g. If the toolchain binaries are under /riscv-gnu-toolchain-binaries/b= in=0D export GCC5_RISCV64_PREFIX=3D/riscv-gnu-toolchain-binaries/bin/riscv64-unk= nown-elf-=0D ```=0D =0D -Then you can build the image for the SiFive HifiveUnleashed platform:=0D +Then you can build the edk2 firmware image for RISC-V platforms.=0D =0D ```=0D +# e.g. For building SiFive Hifive Unleashed platform:=0D build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveU= nleashedBoard/U540.dsc=0D ```=0D =0D -### EDK2 project=0D -All changes in edk2 are upstream, however, most of the RISC-V code is in=0D -edk2-platforms. Therefore you have to check out the branch `riscv-smode-li= b` on=0D -`github.com/changab/edk2-platforms`.=0D -=0D -The build architecture which is supported and verified so far is `RISCV64`= .=0D -The latest master of the RISC-V toolchain https://github.com/riscv/riscv-g= nu-toolchain=0D -should work but the latest verified commit is `b468107e701433e1caca3dbc8ae= f8d40`.=0D -Toolchain tag is "GCC5" declared in `tools_def.txt`=0D +## RISC-V OpenSBI Library=0D +RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation o= f [RISC-V SBI (Supervisor Binary Interface) specification](https://github.c= om/riscv/riscv-sbi-doc). For EDK2 UEFI firmware solution, RISC-V OpenSBI is= integrated as a library [(submoudule)](Silicon/RISC-V/ProcessorPkg/Library= /RiscVOpensbiLib/opensbi) in EDK2 RISC-V Processor Package. The RISC-V Open= SBI library is built in SEC driver=0D +without any modifications and provides the interfaces for supervisor mode = execution environment to execute privileged operations.=0D =0D ## RISC-V Platform PCD settings=0D ### EDK2 Firmware Volume Settings=0D @@ -54,9 +53,9 @@ EDK2 Firmware volume related PCDs which declared in platf= orm FDF file. |PcdRiscVSecFvBase| The base address of SEC Firmware Volume|=0D |PcdRiscVSecFvSize| The size of SEC Firmware Volume|=0D |PcdRiscVPeiFvBase| The base address of PEI Firmware Volume|=0D -|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|=0D +|PcdRiscVPeiFvSize| The size of PEI Firmware Volume|=0D |PcdRiscVDxeFvBase| The base address of DXE Firmware Volume|=0D -|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|=0D +|PcdRiscVDxeFvSize| The size of DXE Firmware Volume|=0D =0D ### EDK2 EFI Variable Region Settings=0D The PCD settings regard to EFI Variable=0D @@ -84,21 +83,24 @@ Below PCDs could be set in platform FDF file. |--------------|---------|=0D |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific|=0D |PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS|=0D +|PcdBootableHartNumber|The bootable HART number, which is incorporate with= RISC-V OpenSBI platform hart_index2id value|=0D =0D ### RISC-V OpenSBI Settings=0D =0D | **PCD name** |**Usage**|=0D |--------------|---------|=0D -|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RIS= C-V HARTs|=0D -|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-= V HARTs|=0D -|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use OpenSBI|=0D +|PcdScratchRamBase| The base address of RISC-V OpenSBI scratch buffer for = all RISC-V HARTs|=0D +|PcdScratchRamSize| The total size of RISC-V OpenSBI scratch buffer for al= l RISC-V HARTs|=0D +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use RISC-V OpenSBI|=0D |PcdTemporaryRamBase| The base address of temporary memory for PEI phase|= =0D |PcdTemporaryRamSize| The temporary memory size for PEI phase|=0D +|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI pha= se|=0D =0D ## Supported Operating Systems=0D -Only support to boot to EFI Shell so far.=0D -=0D -Porting GRUB2 and Linux EFISTUB is in progress.=0D +Currently support boot to EFI Shell and Linux kernel.=0D +Refer to below link for more information,=0D +https://github.com/riscv/riscv-uefi-edk2-docs=0D =0D ## Known Issues and Limitations=0D -Only RISC-V RV64 is verified.=0D +Only RISC-V RV64 is verified on edk2.=0D +=0D --=20 2.25.0