From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.groups.io with SMTP id smtpd.web10.18813.1598534630418971254 for ; Thu, 27 Aug 2020 06:23:50 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=BXa26xIF; spf=pass (domain: nuviainc.com, ip: 209.85.128.65, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f65.google.com with SMTP id o21so5101976wmc.0 for ; Thu, 27 Aug 2020 06:23:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=wqRTfdEuLFFohKR8NUcQ1kx3gT5FGZ0Mp1tn3aoGhc8=; b=BXa26xIFdr9WWD/fNUZrzFBWMIvhGACTnCkD50Rt9flUrLVRPYfnIKjQatij/vJVNH eQQ9ysUSjT7xaKpRnHiL+gyamKrfT2BuygBHUQYTa5HgMfsiWDralMskPKsvRbg9O9P1 NIvu6VkdKFpoRE0baelFcFEj1C9JWN1HZPO6IQnHwtmfqopTSNseqQ9goEB9+FWIA7// OMnpMezHtGJkOkoAPCdD6/kkj9gveBPCxE6nMpgdK2lOEq0M+/6Uu8cahXcum7f0HRZ1 7S9hKv+I6aKe6xR96Qc5EAQVT2AQ4VFNrFyssK8lCaukGVWIU1Ck7+kq8M9MoKGsEFo2 IlUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=wqRTfdEuLFFohKR8NUcQ1kx3gT5FGZ0Mp1tn3aoGhc8=; b=nimYhU/pCXti2otiSaEWjjgSGdqrc3PoR2CMQIz5KUp54Edzx0TD8qrhpOdv+M1yre ET5VRa8ZNf6yj09TL0JTNs6zkWhzhklbcvlUR+VyzPo49HfWQTRDiBLGbvMA5VXHgnPv CM6z9HUrAo1nXw1w4r7k4S71ZYodPyzdeMws+jqQHmb8IABs3HclVjLR3fNKGPdPoHyG bECbsT3baVB2GM2tdN50breF4qXIYZe9bpzfnW8RkZqDz4GqXYYE1Nh0KVWtAZMWLVwl YrAf5ypGnvQDiKnKOImvqnaV5i8W0hHotj1j9Q2EoMbns2Vg5fSGBgOJY6/ZQTwJPe4i EXZg== X-Gm-Message-State: AOAM533/i318Tr5qlMs09tVtdj+6FjxVGQDTOsTcbsuAZ3Z+Da3iPLBD 3M8TNRXhx/Nc0UWpEfMAI9CQD1ZlIeKxfi4RinUtaErEAOrpVLjOtP6Md//MotlfPg7pQHW58s+ IKVT9C3mLzKqrkx9P78b/6F46JXWzg0NlKGFm0U1LuyPvGlHTbHT21JDuf+6eHj+TtZdP X-Google-Smtp-Source: ABdhPJy6nQcSCjVY9t2RQto9oKZ2Yfqqd+N7MLJb3HZYqmHF5AI/yEZHYal9s5J8H+0jjEvGdNCQsA== X-Received: by 2002:a7b:cc13:: with SMTP id f19mr11618426wmh.168.1598534628503; Thu, 27 Aug 2020 06:23:48 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id u16sm5069641wmc.7.2020.08.27.06.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2020 06:23:47 -0700 (PDT) Date: Thu, 27 Aug 2020 14:23:45 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Cc: Daniel Schaefer Subject: Re: [edk2-devel] [edk2-plaforms PATCH 2/3] RISC-V/PlatformPkg: Revise Readme.md Message-ID: <20200827132345.GU1191@vanye> References: <20200827120305.26095-1-abner.chang@hpe.com> <20200827120305.26095-3-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <20200827120305.26095-3-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Aug 27, 2020 at 20:03:04 +0800, Abner Chang wrote: > Update RISC-V PlatformPkg Readme.md to align with the latest implementation. > > Signed-off-by: Abner Chang > Co-authored-by: Daniel Schaefer > > Cc: Daniel Schaefer > --- > Platform/RISC-V/PlatformPkg/Readme.md | 72 ++++++++++++++------------- > 1 file changed, 37 insertions(+), 35 deletions(-) > > diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/PlatformPkg/Readme.md > index 2632ebeb28..bd3b823fb4 100644 > --- a/Platform/RISC-V/PlatformPkg/Readme.md > +++ b/Platform/RISC-V/PlatformPkg/Readme.md > @@ -1,49 +1,48 @@ > -# Introduction > +# Introduction of EDK2 RISC-V Port This is edk2-platforms: any introduction of edk2 portions should be in edk2. > > -## EDK2 RISC-V Platform Packages > -RISC-V platform package provides the generic and common modules for RISC-V > -platforms. RISC-V platform package could include RiscPlatformPkg.dec to > -use the common drivers, libraries, definitions, PCDs and etc. for the > -platform development. > +## EDK2 RISC-V Project > +The edk2 build architecture which is supported and verified on edk2 code base for RISC-V platforms is `RISCV64`. > +The toolchain is on RISC-V GitHub (https://github.com/riscv/riscv-gnu-toolchain) for building edk2 RISC-V binary. > +The corresponding edk2 Toolchain tag for building RISC-V platform is "GCC5" declared in `tools_def.txt`. Please wrap long lines, like in the text being replaced. The point of markdown/rst etc is that it can be rendered into auto-reflowed HTML text *or* read directly in a terminal. Wrapping it properly for the latter won't impact the former. > > -There are two packages to support RISC-V: > +There are two packages to support RISC-V edk2 platforms: > - `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec` > - `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec` (I would say edk2-platforms can be left out when referring to the current repository.) > > -`RiscVPlatformPkg` provides SEC phase and NULL libs. > -`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers. > +`RiscVPlatformPkg` currently provides the generic SEC driver for all RISC-V platforms, and some platform level libraries. > +`RiscVProcessorPkg` currently provides RISC-V processor related libraries, PEI modules, DXE drivers and industrial > +standard header files. > > -### Download the sources ### > +## EDK2 RISC-V Platform Package edk2-platforms? > +RISC-V platform package provides the common modules for RISC-V platforms. RISC-V platform vendors could include > +RiscPlatformPkg.dec to use the common drivers, libraries, definitions, PCDs and etc. for the > +RISC-V platform development. > + > +### Download the Source Code ### > ``` > git clone https://github.com/tianocore/edk2.git > +git clone https://github.com/tianocore/edk2-platforms.git > > -git clone https://github.com/changab/edk2-platforms.git > -# Check out branch: riscv-smode-lib > ``` > > -To build it, you have to follow the regular steps for EDK2 and additionally set > -an environmen variable to point to your RISC-V toolchain installation, > -including the binary prefixes: > - > +You have to follow the build steps for EDK2 (https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II) > +and additionally set an environment variable to point to your RISC-V toolchain binaries for building RISC-V > +platforms, > ``` > +# e.g. If the toolchain binaries are under /riscv-gnu-toolchain-binaries/bin > export GCC5_RISCV64_PREFIX=/riscv-gnu-toolchain-binaries/bin/riscv64-unknown-elf- > ``` Look, I realise you guys aren't building natively yet, but I *strongly* recomment that you start seeing that as something normal sooner rather than later. There's nothing wrong with describing cross compilation as well, and in these early days even point to specific "known good" toolchains, but treating it as the only valid way of building feeds complacency. And even while I *did* push for native-is-normal for arm64 from the earliest days, we still get occasional comments about people using some archaologic specific linaro build and think the sky will fall on their heads because it's an ancient build for i686 and no longer runs on current Linux distros. / Leif > > -Then you can build the image for the SiFive HifiveUnleashed platform: > +Then you can build the edk2 firmware image for RISC-V platforms. > > ``` > +# e.g. For building SiFive Hifive Unleashed platform: > build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc > ``` > > -### EDK2 project > -All changes in edk2 are upstream, however, most of the RISC-V code is in > -edk2-platforms. Therefore you have to check out the branch `riscv-smode-lib` on > -`github.com/changab/edk2-platforms`. > - > -The build architecture which is supported and verified so far is `RISCV64`. > -The latest master of the RISC-V toolchain https://github.com/riscv/riscv-gnu-toolchain > -should work but the latest verified commit is `b468107e701433e1caca3dbc8aef8d40`. > -Toolchain tag is "GCC5" declared in `tools_def.txt` > +## RISC-V OpenSBI Library > +RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation of [RISC-V SBI (Supervisor Binary Interface) specification](https://github.com/riscv/riscv-sbi-doc). For EDK2 UEFI firmware solution, RISC-V OpenSBI is integrated as a library [(submoudule)](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi) in EDK2 RISC-V Processor Package. The RISC-V OpenSBI library is built in SEC driver > +without any modifications and provides the interfaces for supervisor mode execution environment to execute privileged operations. > > ## RISC-V Platform PCD settings > ### EDK2 Firmware Volume Settings > @@ -54,9 +53,9 @@ EDK2 Firmware volume related PCDs which declared in platform FDF file. > |PcdRiscVSecFvBase| The base address of SEC Firmware Volume| > |PcdRiscVSecFvSize| The size of SEC Firmware Volume| > |PcdRiscVPeiFvBase| The base address of PEI Firmware Volume| > -|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| > +|PcdRiscVPeiFvSize| The size of PEI Firmware Volume| > |PcdRiscVDxeFvBase| The base address of DXE Firmware Volume| > -|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| > +|PcdRiscVDxeFvSize| The size of DXE Firmware Volume| > > ### EDK2 EFI Variable Region Settings > The PCD settings regard to EFI Variable > @@ -84,21 +83,24 @@ Below PCDs could be set in platform FDF file. > |--------------|---------| > |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific| > |PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS| > +|PcdBootableHartNumber|The bootable HART number, which is incorporate with RISC-V OpenSBI platform hart_index2id value| > > ### RISC-V OpenSBI Settings > > | **PCD name** |**Usage**| > |--------------|---------| > -|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V HARTs| > -|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-V HARTs| > -|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use OpenSBI| > +|PcdScratchRamBase| The base address of RISC-V OpenSBI scratch buffer for all RISC-V HARTs| > +|PcdScratchRamSize| The total size of RISC-V OpenSBI scratch buffer for all RISC-V HARTs| > +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use RISC-V OpenSBI| > |PcdTemporaryRamBase| The base address of temporary memory for PEI phase| > |PcdTemporaryRamSize| The temporary memory size for PEI phase| > +|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI phase| > > ## Supported Operating Systems > -Only support to boot to EFI Shell so far. > - > -Porting GRUB2 and Linux EFISTUB is in progress. > +Currently support boot to EFI Shell and Linux kernel. > +Refer to below link for more information, > +https://github.com/riscv/riscv-uefi-edk2-docs > > ## Known Issues and Limitations > -Only RISC-V RV64 is verified. > +Only RISC-V RV64 is verified on edk2. > + > -- > 2.25.0 > > > >