From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by mx.groups.io with SMTP id smtpd.web12.2750.1598984983209122320 for ; Tue, 01 Sep 2020 11:29:43 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=je6LTJro; spf=pass (domain: linaro.org, ip: 209.85.215.194, mailfrom: tanmay.jagdale@linaro.org) Received: by mail-pg1-f194.google.com with SMTP id d19so1125708pgl.10 for ; Tue, 01 Sep 2020 11:29:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Qi8MZpD5HEFcmRCsWQRouHpFipip38cY3yFiY0B0I7c=; b=je6LTJrohzTciDDBVyP2Svs0rCru9ehbB49M2ZeE2czdCEn26xyvTcS7q+ZuVH9l9d 6dmiH1zZ+uXSFIWs/dbS/MNYB8vSeNSGKcUKXn6UgV/8TnvOZJfhiOH1ZsWdwVHVjdBt jaUI6gfVqWo1Die7dYd8gvK1wUeM0BvGSzdaPqlpUsI9ZD4hfSmw54Xq0tQbgDwKYTyi 42cHRAoZ2Bc9E97GdCga4ohVcVj06rAm9L4CBbxuWnsJweeH2neyzVzOA+p+RvfwF1AM u5mQOelWk2VuYGOW9sw0kcorHwcoaMnZTCQV2Upup1iKosm83jpWDmAr22qIQup/oxOk Mu4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Qi8MZpD5HEFcmRCsWQRouHpFipip38cY3yFiY0B0I7c=; b=pOSMVjS6AD9QbaKRcML4roFKH97zmqUlCzSzFaws9wTWs/I/nIzHwCDnC0iZNHw6C+ SgF+7tKNfMGrn3Kj2fI5/8dVG+iHabIwLH6FEpy6I/gfEF5KLsF9dIt+M0hzaU5hswcr 5rXRPiKFUTDHlgOO2IxI6ouiMYjPVxYQkDPCdA/Sq2pxSQySjSlcSSVk6SizuaB+Jx+Q vQ2FWfhoazKGk3f0dUvMTgGg5fVv3UJX6F7mzSp52nKAprMLbQLoK162h/wBwnVe5fIr 63Xi7/Or9dwmFOiyzBpxM0vkSUe34cOVtWfRKnUPc7rvPthDi2PcuHJLhhrZ1uIS4qxm elxQ== X-Gm-Message-State: AOAM532y771yFUfRLR+3gfsfSqSueJvXFZdyAcCUFbJWkkpR/PtbVrKJ aIv7zp4FlyeDJy+qp1HCKsAnSw== X-Google-Smtp-Source: ABdhPJy1kE6sMb7u8YPAEz7QG7NdhcghToJW0yYhZ21Ap+HF5+OReFheaBBCCWkN+nlASe1YvmVfig== X-Received: by 2002:a62:7789:: with SMTP id s131mr3249789pfc.25.1598984982687; Tue, 01 Sep 2020 11:29:42 -0700 (PDT) Return-Path: Received: from bean-canyon.localdomain ([106.51.141.122]) by smtp.googlemail.com with ESMTPSA id i16sm5433902pjv.0.2020.09.01.11.29.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 11:29:42 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale Subject: [PATCH edk2-platforms 1/1] SbsaQemu: AcpiDxe: Read MPIDR from device tree Date: Tue, 1 Sep 2020 23:59:38 +0530 Message-Id: <20200901182938.76281-1-tanmay.jagdale@linaro.org> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Qemu device tree for Sbsa platform now contains MPIDR value for every CPU in the form of "reg" property under every CPU's node. Hence, add a function that provides support to read this value from the device tree. Signed-off-by: Tanmay Jagdale --- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 47a9bd1d423a..fb7c1835c3d7 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -22,6 +22,9 @@ #include #include +STATIC INT32 FdtFirstCpuOffset; +STATIC INT32 FdtCpuNodeSize; + /* * A function that walks through the Device Tree created * by Qemu and counts the number of CPUs present in it. @@ -56,12 +59,14 @@ CountCpusFromFdt ( // The count of these subnodes corresponds to the number of // CPUs created by Qemu. Prev = fdt_first_subnode (DeviceTreeBase, CpuNode); + FdtFirstCpuOffset = Prev; while (1) { CpuCount++; Node = fdt_next_subnode (DeviceTreeBase, Prev); if (Node < 0) { break; } + FdtCpuNodeSize = Node - Prev; Prev = Node; } @@ -69,6 +74,34 @@ CountCpusFromFdt ( ASSERT_RETURN_ERROR (PcdStatus); } +/* + * Get MPIDR from device tree passed by Qemu + */ +STATIC +UINT64 +GetMpidr ( + IN UINTN CpuId + ) +{ + VOID *DeviceTreeBase; + CONST UINT64 *RegVal; + INT32 Len; + + DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); + ASSERT (DeviceTreeBase != NULL); + + RegVal = fdt_getprop (DeviceTreeBase, + FdtFirstCpuOffset + (CpuId * FdtCpuNodeSize), + "reg", + &Len); + if (!RegVal) { + DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", CpuId)); + return 0; + } + + return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); +} + /* * A Function to Compute the ACPI Table Checksum */ @@ -173,7 +206,7 @@ AddMadtTable ( CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New; GiccPtr->AcpiProcessorUid = NumCores; - GiccPtr->MPIDR = NumCores; + GiccPtr->MPIDR = GetMpidr (NumCores); New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); } -- 2.28.0