From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.groups.io with SMTP id smtpd.web12.15290.1599143371245522299 for ; Thu, 03 Sep 2020 07:29:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=fQiBH53L; spf=pass (domain: nuviainc.com, ip: 209.85.221.68, mailfrom: graeme@nuviainc.com) Received: by mail-wr1-f68.google.com with SMTP id g4so3481620wrs.5 for ; Thu, 03 Sep 2020 07:29:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=anh7syJDXuskQs+xncQw96XgabIs0XpgKlF1Uya6m3c=; b=fQiBH53LqORPpaWMiK69teFXgBaxW3bTuRW5XBDMsBJiRdYeUPnes+uI6PeCDvKaxF ZIh5Uv7nFXQbKOTUzzwKbyI1Pz151bV208/I7I3Ku6feEwUOw8L4Nq4ScDufXwvd6wJJ XEquDIOIZbT8/rfe58iwdFjLc3xoqgY3NGwPlh7dD22o4C2PemmmLVBnvMCHJnpVGVWV zCJEFFyo6wCASso+n3X5ZGyvXJOH638mlAx9+2jLbhs5m/RSUfSScUP41FHohzrm8RQ0 mR7XeDZ8ggyLtC6atwZ0eu7FVBEDAQY3lrR/boeAzqq/sSNiOYABEEGzIXE13mSjc8uo 70jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=anh7syJDXuskQs+xncQw96XgabIs0XpgKlF1Uya6m3c=; b=mCykh3ZV2a/7iGeaAkyrCnUhzlUPlCS7D8ASs12SUPkMuracDkVlBzpsQglT28kNUy 52cdfUC8oqYltUzh9oQVFpfw7tyDPhxphyIfRg9by7Qjuk5jz6UzZipC9O0Q/d0qBbFY aTLD5cGpGEfAB2wJkVLl8naxqtbox5J6Uo+gTOXqOHP1SiODYODlyUZlqYazfWicSsOh iK87lwton43K3DyW0jj/dsMb3QUE6s1yEXtLl7o5j+pB9Qjik/i1ooJ+b/oDtQucDTIZ 0ZVP8AtQIa/qQfploFWMbIixZRKWoqjT+ri4A519JeNiratMls+RIKTMTTAXNfC+yKYQ qVDw== X-Gm-Message-State: AOAM531ZCdoE0ent2zK7pPXUoJwRsSTXoDDQ9fEdVHQXn0WPSkYiRwYD CLa6HcmYQPTK/q0FN6mxEuI5ew== X-Google-Smtp-Source: ABdhPJzJrT/OjjP9GsovtdBIZvdLnjUBaem2XX81cFui0KuO7k0Q7Qlm8FSVuGQemjD3KLdNZbE+fw== X-Received: by 2002:a5d:4e0b:: with SMTP id p11mr2673384wrt.13.1599143369675; Thu, 03 Sep 2020 07:29:29 -0700 (PDT) Return-Path: Received: from xora-monster ([2a02:8010:64d6::1d89]) by smtp.gmail.com with ESMTPSA id c205sm4668997wmd.33.2020.09.03.07.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 07:29:29 -0700 (PDT) Date: Thu, 3 Sep 2020 15:29:27 +0100 From: "Graeme Gregory" To: Tanmay Jagdale Cc: leif@nuviainc.com, devel@edk2.groups.io, shashi.mallela@linaro.org Subject: Re: [PATCH edk2-platforms 1/1] SbsaQemu: AcpiDxe: Read MPIDR from device tree Message-ID: <20200903142927.quxa4empiryapblw@xora-monster> References: <20200901182938.76281-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 In-Reply-To: <20200901182938.76281-1-tanmay.jagdale@linaro.org> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Sep 01, 2020 at 11:59:38PM +0530, Tanmay Jagdale wrote: > The Qemu device tree for Sbsa platform now contains MPIDR value > for every CPU in the form of "reg" property under every CPU's > node. Hence, add a function that provides support to read this > value from the device tree. > > Signed-off-by: Tanmay Jagdale This generates the correct APIC table in my testing Tested-by: Graeme Gregory > --- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 35 ++++++++++++++++++- > 1 file changed, 34 insertions(+), 1 deletion(-) > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > index 47a9bd1d423a..fb7c1835c3d7 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -22,6 +22,9 @@ > #include > #include > > +STATIC INT32 FdtFirstCpuOffset; > +STATIC INT32 FdtCpuNodeSize; > + > /* > * A function that walks through the Device Tree created > * by Qemu and counts the number of CPUs present in it. > @@ -56,12 +59,14 @@ CountCpusFromFdt ( > // The count of these subnodes corresponds to the number of > // CPUs created by Qemu. > Prev = fdt_first_subnode (DeviceTreeBase, CpuNode); > + FdtFirstCpuOffset = Prev; > while (1) { > CpuCount++; > Node = fdt_next_subnode (DeviceTreeBase, Prev); > if (Node < 0) { > break; > } > + FdtCpuNodeSize = Node - Prev; > Prev = Node; > } > > @@ -69,6 +74,34 @@ CountCpusFromFdt ( > ASSERT_RETURN_ERROR (PcdStatus); > } > > +/* > + * Get MPIDR from device tree passed by Qemu > + */ > +STATIC > +UINT64 > +GetMpidr ( > + IN UINTN CpuId > + ) > +{ > + VOID *DeviceTreeBase; > + CONST UINT64 *RegVal; > + INT32 Len; > + > + DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); > + ASSERT (DeviceTreeBase != NULL); > + > + RegVal = fdt_getprop (DeviceTreeBase, > + FdtFirstCpuOffset + (CpuId * FdtCpuNodeSize), > + "reg", > + &Len); > + if (!RegVal) { > + DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", CpuId)); > + return 0; > + } > + > + return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); > +} > + > /* > * A Function to Compute the ACPI Table Checksum > */ > @@ -173,7 +206,7 @@ AddMadtTable ( > CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); > GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New; > GiccPtr->AcpiProcessorUid = NumCores; > - GiccPtr->MPIDR = NumCores; > + GiccPtr->MPIDR = GetMpidr (NumCores); > New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); > } > > -- > 2.28.0 >